An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques - Schmidt, Bernhard; Ziener, Daniel; Teich, Jürgen (In Proceedings of 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, 2014)

An FPGA Implementation of a Threat-based Strategy for Connect6 - Ziermann, Tobias; Schmidt, Bernhard; Mühlenthaler, Moritz; Ziener, Daniel; Angermeier, Josef; Teich, Jürgen (Proceedings of the International Conference on Field-Programmable Technology, 2011)
In this paper, we present a strategy and an FPGA implementation of a Connect6 player submitted to the FPT 2011 Design Competition. Connect6 is a two-player strategy board game. The winner of the game is the player who first gets six pieces of his color in a connected horizontal, vertical or diagonal line. We assign a strategic value to each potential move depending on the current board configuration. Our approach uses a minimal amount of situation dependent game logic in order to take full advantage of the available compute resources and parallelism. The FPGA implementation of this strategy always wins against the software opponent provided for the competition. Additionally, our implementation wins on average against different software AIs from [1], as long as no sophisticated game-tree search is performed by the software. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.anfpga

A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor - Glein, Robert; Schmidt, Bernhard; Rittner, Florian; Teich, Jürgen; Ziener, Daniel (Proceedings of Field-Programmable Custom Computing Machines (FCCM 2014), 2014)
In this paper, we propose a self-adaptive FPGAbased, partially reconfigurable system for space missions in order to mitigate Single Event Upsets in the FPGA configuration and fabric. Dynamic reconfiguration is used here for an on-demand replication of modules in dependence of current and changing radiation levels. More precisely, the idea is to trigger a redundancy scheme such as Dual Modular Redundancy or Triple Modular Redundancy in response to a continuously monitored Single Event Upset rate measured inside the on-chip memories itself, e.g., any subset (even used) internal Block RAMs. Depending on the current radiation level, the minimal number of replicas is determined at runtime under the constraint that a required Safety Integrity Level for a module is ensured and configured accordingly. For signal processing applications it is shown that this autonomous adaption to the different solar conditions realizes a resource efficient mitigation. In our case study, we show that it is possible to triplicate the data throughput at the Solar Maximum condition (no flares) compared to a Triple Modular Redundancy implementation of a single module. We also show the decreasing Probability of Failures Per Hour by 2 × 10 at flare-enhanced conditions compared with a non-redundant system. Our work is a part of the In-Orbit Verification of the Heinrich Hertz communication satellite.

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning - Schmidt, Bernhard; Ziener, Daniel; Teich, Jürgen (Proc. of the Reconfigurable Architectures Workshop (RAW), 2014)
Existing techniques for SEU mitigation on FPGAs by scrubbing do not prevent permanent malfunction of a circuit design in case that the corresponding configuration bits do belong to feedback loops. In this paper, we a) provide a circuit analysis technique to distinguish so-called critical bits from essential bits to determine which parts of a bitstream will need also state-restoring actions after scrubbing and which not. Moreover, b) we will propose floorplanning techniques to reduce the effective number of frames that need to be scrubbed and c), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits may be reduced by up to 48.5% in comparison to a standard approach. For the MTTR calculation, we assume a system with checkpointing using the Xilinx SEM IP core to implement the scrubbing controller.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.minimi

Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning - Schmidt, Bernhard; Ziener, Daniel; Teich, Jürgen; Zöllner, Christian (Integration-The Vlsi Journal, 2017)
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits which will need also state-restoring actions after a recovered SEU and which not. Furthermore, b) an alternative classification approach using fault injection is developed in order to compare both classification techniques. Moreover, c) we will propose a floorplanning approach for reducing the effective number of scrubbed frames and d), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits can be reduced by up to 48.5 % in comparison to standard approaches.
Keywords: Single Event Upsets; FPGA Scrubbing; Configuration Bit Partitioning; Floorplanning; Fault Injection