Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates - Reuben, John Reuben; Pechmann, Stefan (IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 2021)
To overcome the ``von Neumann bottleneck,'' methods to compute in memory are being researched in many emerging memory technologies, including resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/imply logic. In this work, we propose a method to implement a majority gate in a transistor-accessed ReRAM array during the READ operation. Together with not gate, which is also implemented in memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement the Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix (PP) adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how PP adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4·log(n)+6 for n-bit addition and is energy-efficient due to the absence of sneak currents in 1Transistor-1Resistor configuration.
CRIS-Team Scopus Importer:2021-04-16
Keywords: 1Transistor-1Resistor (1T-1R); Adders; Arrays; compute-in-memory; in-memory computing; Logic arrays; Logic gates; logic-in-memory; majority gate; majority logic; memristor; nonvolatile memory (NVM); parallel-prefix (PP) adder; processing-in-memory; readout circuit; Resistance; Resistive RAM; resistive RAM (ReRAM); sense amplifier (SA); Transistors; von Neumann bottleneck.

A Low-Power Ternary Adder Using Ferroelectric Tunnel Junctions - Reuben, John Reuben; Fey, Dietmar; Lancaster, Suzanne; Slesazeck, Stefan (Electronics, 2023)
Computing systems are becoming more and more power-constrained due to unconventional computing requirements like computing on the edge, in-sensor, or simply an insufficient battery. Emerging Non-Volatile Memories are explored to build low-power computing circuits, and adders are one among them. In this work, we propose a low-power adder using a Ferroelectric Tunnel Junction (FTJ). FTJs are two-terminal devices where the data is stored in the polarization state of the device. An FTJ-based majority gate is proposed, which uses a current-mode sensing technique to evaluate the majority of the inputs. By conditionally selecting between the majority and its complement, an XOR operation is implemented, thereby achieving full-adder functionality. Since FTJ-based majority operation is slow, a ternary adder architecture is used to compensate for the speed loss. The ternary adder proposed by us has two stages of full adder and requires O(1) time for n-bit addition. The proposed adder is verified using a simulation in CMOS 130 nm technology. A 32-bit addition can be achieved in 100 μs and consumes 0.78 pJ, which is very power efficient (7.8 nW). The proposed adder can be used in applications where power consumption is crucial, and speed is not a strict requirement.
CRIS-Team Scopus Importer:2023-03-24
Keywords: carry-free addition; Ferroelectric Tunnel Junctions (FTJs); full adder; low-power; majority logic; memristor; sense amplifier; ternary arithmetic

A modeling methodology for resistive RAM based on stanford-PKU model with extended multilevel capability - Reuben, John Reuben; Fey, Dietmar; Wenger, Christian (IEEE Transactions on Nanotechnology, 2019)
Modeling of resistive RAMs (RRAMs) is a herculean task due to its non-linearity. While the exigent need for a model has motivated research groups to formulate realistic models, the diversity in RRAMs' characteristics has created a gap between model developers and model users. This paper bridges the gap by proposing an algorithm by which the parameters of a model are tuned to specific RRAMs. To this end, a physics-based compact model was chosen due to its flexibility, and the proposed algorithm was used to exactly fit the model to different RRAMs, which differed greatly in their material composition and switching behavior. Furthermore, the model was extended to simulate multiple low resistance states (LRS), which is a vital focus of research to increase memory density in RRAMs. The ability of the model to simulate the switching from a high resistance state to multiple LRS was verified by measurements on 1T-1R cells.
CRIS-Team Scopus Importer:2019-07-16
Keywords: 1T-1R; memristor; multilevel modeling; physics-based models; resistive switching; RRAM; SET/RESET process; Stanford model

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic - Lakshmi, Vijaya; Reuben, John Reuben; Pudi, Vikramkumar (IEEE Transactions on Circuits and Systems I-Regular Papers, 2021)
In-memory computing using emerging technologies such as resistive random-access memory (ReRAM) addresses the `von Neumann bottleneck' and strengthens the present research impetus to overcome the memory wall. While many methods have been recently proposed to implement Boolean logic in memory, the latency of arithmetic circuits (adders and consequently multipliers) implemented as a sequence of such Boolean operations increases greatly with bit-width. Existing in-memory multipliers require O(n²) cycles which is inefficient both in terms of latency and energy. In this work, we tackle this exorbitant latency by adopting Wallace Tree multiplier architecture and optimizing the addition operation in each phase of the Wallace Tree. Majority logic primitive was used for addition since it is better than NAND/NOR/IMPLY primitives. Furthermore, high degree of gate-level parallelism is employed at the array level by executing multiple majority gates in the columns of the array. In this manner, an in-memory multiplier of O(n.log(n)) latency is achieved which outperforms all reported in-memory multipliers. Furthermore, the proposed multiplier can be implemented in a regular transistor-accessed memory array without any major modifications to its peripheral circuitry and is also energy-efficient.
CRIS-Team Scopus Importer:2021-12-17
Keywords: 1Transistor-1Resistor (1T-1R); Adders; Arrays; Computer architecture; in-memory computing; Logic arrays; Logic gates; majority logic; Memristor; Microprocessors; Parallel processing; parallel-prefix adder; processing-in-memory; read-out circuit.; resistive random-access memory (ReRAM); sense amplifier; von Neumann bottleneck; Wallace Tree multiplier

A parallel-friendly majority gate to accelerate in-memory computation - Reuben, John Reuben; Pechmann, Stefan (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, 2020)
Efforts to combat the 'von Neumann bottleneck' have been strengthened by Resistive RAMs (RRAMs), which enable computation in the memory array. Majority logic can accelerate computation when compared to NAND/NOR/IMPLY logic due to it's expressive power. In this work, we propose a method to compute majority while reading from a transistor-accessed RRAM array. The proposed gate was verified by simulations using a physics-based model (for RRAM) and industry standard model (for CMOS sense amplifier) and, found to tolerate reasonable variations in the RRAMs' resistive states. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. The parallel-friendly nature of the proposed gate is exploited to implement an eight-bit parallel-prefix adder in memory array. The proposed in-memory adder could achieve a latency reduction of 70% and 50% when compared to IMPLY and NAND/NOR logic-based adders, respectively.
CRIS-Team Scopus Importer:2020-09-25
Keywords: 1 Transistor-1 Resistor(1T-1R); Compute-in-memory; In-memory computing; Majority gate; Majority logic; Memristor; Parallel-prefix adder; Processing-in-memory; Resistive RAM (RRAM); Von Neumann bottleneck

A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories - Reuben, John Reuben; Fey, Dietmar; Slesazeck, Stefan (2023 12th International Conference on Modern Circuits and Systems Technologies, MOCAST 2023 - Proceedings, 2023)
Ferroelectric Tunnel Junction (FTJ) is an emerging non-volatile memory technology with increasing applications in memory and computing. Although the low currents of FTJ memories is an advantage from energy point of view, sensing of these memories is a challenge due to the pA read-out currents. In this work, we propose a Sense Amplifier (SA) specifically designed for FTJ memory technology. The proposed SA accumulates the charge at the gate of a read transistor and thus converts the pA current to hundreds of nA. A Schmitt-Trigger circuit is then used to differentiate between these two currents by using the threshold-voltage of the Schmitt-Trigger as reference. The proposed SA consumes an energy of 82 fJ/bit and also does not require an absolute voltage/current reference for sensing, thus conserving on-chip area.
CRIS-Team Scopus Importer:2023-08-11
Keywords: Ferroelectric Tunnel Junctions (FTJ); low-power; Memristor; non-volatile memory; peripheral circuitry; read-out; Schmitt-Trigger circuit; sense amplifier

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM - Reuben, John Reuben; Fey, Dietmar (2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings, 2019)
The quest to increase memory density in Resistive Random Access Memory (RRAM) has motivated researchers to store more bits/cell by implementing Multi-Level Cell (MLC) or multi-bit RRAM. Implementing multiple states narrows the distance between states, making sensing of MLC RRAM a challenging task. In this paper, we present a circuit which senses the state of a MLC by converting the current drawn from the cell to voltage pulses, where the number of pulses is proportional to the current's magnitude. The circuit distinguishes between the states by the relative current's magnitude and hence does not require an absolute reference. Simulations in IHP's 130 nm CMOS technology confirmed fast (single step) sensing while tolerating appropriate variations in the sensed resistance. The proposed circuit is also area efficient when compared to conventional parallel sensing approach.
CRIS-Team Scopus Importer:2019-12-17
Keywords: memristor; multilevel cell (MLC); read; Resistive RAM; schmitt-trigger; sense amplifier; sensor

Binary addition in resistance switching memory array by sensing majority - Reuben, John Reuben (Micromachines, 2020)
The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the 'von Neumann bottleneck' or 'memory wall'. Emerging resistance switching memories (memristors) show promising signs to overcome the 'memory wall' by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory READ operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory READ and WRITE operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T-1R array, which is faster than IMPLY, NAND, NOR and other similar logic primitives.
CRIS-Team Scopus Importer:2020-06-09
Keywords: Adder; Boolean logic; In-memory computing; Majority logic; Memristor; Non-volatile memory (NVM); Resistance switching memory; Sense Amplifier

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles - Prabahar, John Reuben; Fey, Dietmar (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 2021)
The movement of data between processing and memory units, often referred to as the 'von Neumann bottleneck' is the main reason for the degraded performance of contemporary computing systems. In an effort to overcome this bottleneck, methods to 'compute' at the location of data are being pursued in many emerging memories, including Resistive RAM (ReRAM). Although many prior works have pursued addition in memory, the latency of n-bit addition has not been judiciously optimized, resulting in O(n) or at best O(log(n)). Computing with three states can enable carry-free addition and result in a latency which is independent of operand width (O(1)). In this work, we propose a method to perform carry-free addition completely in memory (a storage array, a processing array and their peripheral circuitry). The proposed technique incurs a latency of 22 memory cycles, which outperforms other in-memory binary adders for n = 32. This speed is achieved at the cost of increased peripheral hardware.
CRIS-Team Scopus Importer:2021-09-24
Keywords: 1 Transistor-1 Resistor (1T1R); carry-free addition; in-memory computing; memristor; Non-Volatile Memory (NVM); Resistive RAM; stored-transfer representation; ternary computing; von Neumann bottleneck

Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic - Fey, Dietmar; Reuben, John Reuben; Slesazeck, Stefan (2021 28TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (IEEE ICECS 2021), 2021)
CRIS-Team WoS Importer:2022-05-06

Design of in-memory parallel-prefix adders - Reuben, John Reuben (Journal of Low Power Electronics and Applications, 2021)
Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width (O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in O(log(n)) latency in the memory array.
CRIS-Team Scopus Importer:2021-12-10
Keywords: 1Transistor-1Resistor (1T–1R); In-memory computing; Logic-in-memory; Majority logic; Memristive logic; Memristor; Non-volatile memory (NVM); Parallel-prefix adder; Processing-in-memory; Resistive RAM (ReRAM)

Direct state transfer in MLC based memristive ReRAM devices for ternary computing - Fey, Dietmar; Reuben, John Reuben (ECCTD 2020 - 24th IEEE European Conference on Circuit Theory and Design, 2020)
In this paper we present a new procedure for a direct state transfer in ReRAM based multi-level cell (MLC) memristors for future ternary data processing, i.e. the direct transitioning of one ternary MLC state to another state. According to the rules of a ternary stored-transfer-adder cell the content of two memristors storing three different resistance values are read out and processed by a sense amplifier to produce a new ternary state for two output memristors. In contrast to own older work the analogue-digital-converting of ternary MLC based memristors with subsequent digital processing is avoided what requires a comparatively high energy budget. The solution is based on an adapted version of an existing sense amplifier circuit realising an in-memory processing for a majority logic developed by our own. We present the new concept and simulation results characterising the functionality for the new memristive ternary MLC for a ReRAM technology from Innovations for High Performance Microelectronics (IHP).
CRIS-Team Scopus Importer:2020-12-04
Keywords: 1 Transistor-1 Resistor(1T1R); in-memory computing; majority logic; memristor; Non-Volatile Memory (NVM); von Neumann bottleneck

Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford-PKU Model - Reuben, John Reuben; Biglari, Mehrdad; Fey, Dietmar (IEEE Transactions on Nanotechnology, 2020)
Intrinsic variability observed in resistive-switching devices (cycle-to-cycle and device-to-device) is widely recognised as a major hurdle for widespread adoption of Resistive RAM technology. While physics-based models have been developed to accurately reproduce the resistive-switching behaviour, reproducing the observed variability behavior of a specific RRAM has not been studied. Without a properly fitted variability in the model, the simulation error introduced at the device-level propagates through circuit-level to system-level simulations in an unpredictable manner. In this work, we propose an algorithm to fit a certain amount of variability to an existing physics-based analytical model (Stanford-PKU model). The extent of variability exhibited by the device is fitted to the model in a manner agnostic to the cause of variability. Further, the model is modified to better reproduce the variations observed in a device. The model, fitted with variability can well reproduce cycle-to-cycle, as well as device-to-device variations. The significance of integrating variability into RRAM models is underscored using a sensing example.
CRIS-Team WoS Importer:2020-08-21

Inner Product Computation In-Memory Using Distributed Arithmetic - Lakshmi, Vijaya; Pudi, Vikramkumar; Reuben, John Reuben (IEEE Transactions on Circuits and Systems I-Regular Papers, 2022)
In-memory computing using emerging technologies such as Resistive Random-Access Memory (ReRAM) has been proposed as a promising substitute for future computing applications to address the ‘von Neumann bottleneck’. Multiplication is the key component for inner product computation in every digital signal processing (DSP) application and the complexity of multipliers increases greatly with bit-width. Distributed arithmetic (DA) using look-up tables and adder-shifter module has been proposed for inner product computation to achieve multiplier-less efficient DSP architectures, particularly when one of the vectors is a constant and known in advance. Due to the memory wall, DA can be made furthermore latency and energy-efficient when implemented ‘in memory’. In this work, for the first time, we propose two design techniques to compute inner product completely in memory using DA. This is accomplished by storing the precomputed look-up table contents in a ReRAM array and implementing adder-shifter module also in the same array. The adder-shifter is implemented in memory using majority gates which are in turn realized as READ operations in the memory array. Two methods of mapping: latency-optimized and area-optimized and their comparison in terms of latency and area are presented. The proposed method-1 achieves ≈ 60% energy savings compared to CMOS and the proposed method-2 achieves 10.59 times higher throughput compared to CMOS.
CRIS-Team Scopus Importer:2022-08-19
Keywords: 1Transistor-1Resistor (1T–1R); adder-shifter; Adders; Arithmetic; Complexity theory; Computer architecture; distributed arithmetic (DA); in-memory computing; Logic gates; look-up table; majority logic; Memristor; Read only memory; read-out circuit; resistive random-access memory (ReRAM); sense amplifier; Table lookup; von Neumann bottleneck

Majority Logic Based In-Memory Comparator - Lakshmi, Vijaya; Prabahar, John Reuben; Pudi, Vikramkumar (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE, 2022)
To conquer the von Neumann bottleneck, it is necessary to shift computation to the place where data resides. In this work, we present a methodology to move the comparator circuit to the memory array. A binary comparator is implemented in a transistor-accessed ReRAM (Resistive Random Access Mem-ory) array using majority logic. The majority primitive is a better logic primitive than NAND/NOR/IMPLY primitives for arithmetic intensive operations and also can be realized in memory array efficiently as a READ operation. Using Majority gates and vast gate-level parallelism in the array, comparator is implemented optimally, latency and energy-wise. Using the methodology presented for 1-bit and 8-bit, any n-bit comparator can be realized in 6 + 4log2n cycles. Moreover, a general transistor-accessed memory array can be used to implement the proposed comparator without the need for any supreme modifications to the memory peripherals and is efficient as well in terms of energy.
CRIS-Team Scopus Importer:2022-09-30
Keywords: 1Transistor-1Resistor (1T-1R); comparator; in-memory computing; majority logic; memristor; processing-in-memory; read-out circuit; resistive random-access memory (ReRAM); sense amplifier; von Neumann bottleneck

mMPU—A Real Processing-in-Memory Architecture to Combat the von Neumann Bottleneck - Talati, Nishil; Ben-Hur, Rotem; Wald, Nimrod; Haj-Ali, Ameer; Prabahar, John Reuben; Kvatinsky, Shahar (Applications of Emerging Memory Technology, 2020)
Data transfer between processing and memory units in modern comput- ing systems is their main performance and energy-efficiency bottleneck, commonly known as the von Neumann bottleneck. Prior research attempts to alleviate the prob- lem by moving the computing units closer to the memory that has had limited success since data transfer is still required. In this chapter, we present mMPU memristive memory processing unit, which relies on a memristive memory to perform computa- tion using the memory cells, and therefore directly tackles the von Neumann bottle- neck. In mMPU, the operation is controlled by a modified controller and peripheral circuit without changing the structure of the memory cells and arrays. As the basic logic element, we present Memristor-Aided loGIC (MAGIC), a technique to com- pute logical functions using memristors within the memory array. We further show how to extend basic MAGIC primitives to execute any arbitrary Boolean function and demonstrate the microarchitecture of the memory. This process is required to enable data computing using MAGIC. Finally, we show how to build the computing system using mMPU, which performs computation using MAGIC to enable a real processing-in-memory machin
Keywords: processing-in-memory; memristors

Rediscovering majority logic in the post-CMOS era: A perspective from in-memory computing - Reuben, John Reuben (Journal of Low Power Electronics and Applications, 2020)
As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50-70% when compared to IMPLY, NAND, NOR and other similar logic primitives.
CRIS-Team Scopus Importer:2020-11-06
Keywords: Adder; Boolean logic; In-memory computing; Majority logic; Memristive logic; Memristor; Non-volatile memory (NVM); Parallel-prefix adder; Resistive ram

Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems - Perez-Bosch Quesada, Emilio; Romero-Zaliz, Rocio; Perez, Eduardo; Kalishettyhalli Mahadevaiah, Mamathamba; Reuben, John Reuben; Schubert, Markus Andreas; Jimenez-Molinos, Francisco; Roldan, Juan Bautista; Wenger, Christian (Electronics, 2021)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.
CRIS-Team WoS Importer:2021-04-16