A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages - Leuschner, Stephan; Pinarello, Sandro; Hodel, Uwe; Müller, Jan-Erik; Klar, Heinrich (Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE, 2010)

Adaptive Strategies for Enhancing the Efficiency of Radio Frequency Power Amplifiers in Back-Of Operation - Pinarello, Sandro (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2017)

Analog Compensation of AM-AM and AM-PM effects for HighEfficiency Stacked-FET Power Amplifiers in 65-nm Standard CMOS - Zohny, Amr; Leuschner, Stephan; Rascher, Jochen; Pinarello, Sandro; Ußmüller, Thomas; Müller, Jan-Erik; Fischer, Georg; Weigel, Robert (European Microwave Integrated Circuits Conference (EuMIC), 2013)
Simultaneously achieving high linearity and high power-added efficiency (PAE) is essential for power amplifiers (PA) operating with modern communication signals. The challenge is exacerbated by the low breakdown voltages of standard CMOS realizations. This work presents a low-complexity programmable analog scheme to compensate the strong AM-AM and AM-PM nonlinearities of the high-ruggedness stacked-cascode topology while maintaining high PAE. The proposed solution utilizes standard NMOS devices to achieve peak PAE of 60% at the 900 MHz band from a 3V supply. The compensation scheme manages to improve the output 1-dB compression point by up to 2 dB and keep the AM-PM variation within 5 degrees. The proposed method improves the linear output power (@ ACPR= -40 dBc) for a Class-AB power amplifier by up to 1.5 dB without compromising PAE or saturated output power
elib2cris::1512001600,zohny2013a
Keywords: Power amplifier; Stacked FET; Stacked cascode; CMOS; linearization; ruggedness

An unconventional VNA-based time-domain waveform load-pull test bench - Teppati, Valeria; Pinarello, Sandro; Ferrero, Andrea; Müller, Jan-Erik (Microwave Conference Proceedings (APMC), 2010 Asia-Pacific, 2010)

Comparative Evaluation of Different Current Saving Strategies for Power Amplifiers in Back-Off Operation - Pinarello, Sandro; Müller, Jan-Erik; Weigel, Robert (European Microwave Conference (EuMC), 2013)
Three different methodologies are compared, which are suitable for saving battery current of a power amplifier operated in back-off. Dynamic Voltage Biasing (DVB), Dynamic Current Biasing (DCB), and Load Modulation (LM) have been paired in three different ways and experimentally tested for the first time on the same power transistor to achieve meaningful conclusions. Measurement results from on-wafer load-pull investigation of a SiGe power cell identify the combination of DVB and DCB as the most profitable strategy. This mode manifests a power added efficiency higher than 75% for an excellent 14dB back-off dynamic.
elib2cris::1512001600,weigel2013a
Keywords: modulation; power amplifiers; power transistors; DCB; DVB; LM; back-off operation; battery current; current saving strategies; dynamic current biasing; Digital video broadcasting; Frequency measurement

Extension of the Load-Line Theory by Investigating the Impact of the Knee-Voltage on Output-Power and Efficiency - Pinarello, Sandro; Müller, Jan-Erik; Weigel, Robert (European Microwave Integrated Circuits Conference, 2013)
The standard load-line theory for power amplifier (PA) design becomes inaccurate when the ratio of the transistor's knee-voltage to the supply voltage gets larger than one. This is often the case for sub-micron CMOS PA designs due to low breakdown voltage. Based on simple geometrical reasoning the load-line theory is generalized to include these cases. The optimum load impedance that results in maximum output power, the maximum power achieved, and the corresponding efficiency are derived in closed form. The efficiency can be improved by backing off the output power. The trade-off between output power and simultaneously achievable efficiency as a function of the knee-voltage is discussed.
elib2cris::1512001600,sandro2013

Frequency Response of Stress-Effects on CMOS Power Amplifiers - Cattaneo, Andrea; Pinarello, Sandro; Müller, Jan-Erik; Weigel, Robert (IEEE International Integrated Reliability Workshop Final Report (IIRW), 2014)
RF Power Amplifiers (PAs) undergo to high electrical stress conditions due to strong lateral field along the channel. Reliability of CMOS PAs is largely studied in literature. Generally is focused in understanding how RF stress can harm the device. Many authors proved that the generation of defects does not have a frequency dependency. In this work the problem is faced from a new point of view. The response of the defects, instead of the generation, is studied over frequency. It is demonstrated that the electrons-trapping by interface states is quenched by increasing the operation frequency. As a consequence the performance of the PA are recovered. This finding points out for the first time the possibility of relaxing the reliability constrains when operating in RF regime.
elib2cris::1512001600,cattaneo2014a

Geometrical demonstration of the VSWR-locus in different reference planes and its applications - Pinarello, Sandro; Müller, Jan-Erik; Weigel, Robert (Microwave Conference, 2009. APMC 2009. Asia Pacific, 2009)
When evaluating the RF robustness of a power amplifier test measurements are performed on a locus of load conditions with constant voltage standing wave ratio (VSWR). The reference plane is normally set at the antenna input terminal where this constant VSWR locus of points represented on a Smith chart is a circle centred on the origin: often 50 Ohm. For design and technology purposes this investigation is performed via on wafer measurement at the transistor level, before the matching network. This implies that a different locus has to be chosen. Previous literature approaches this issue in a purely algebraical way which formulates the relationship between this two loci but leaves peculiar properties of the transformation unrevealed and unused. In this paper the problem is geometrically tackled and solved by reasoning on the nature of the loci and on the properties of the functions involved. The geometrical procedure is then arithmetically formalised as a linear system of equations whose solutions are compared with those of the classical approach. This comparison lead to discover an imprecision in the formulas previously published. The geometrical reasoning reveals a set of peculiar solutions which are traced back to conditions on the S-parameters of the matching network. The outcome of this proof is suitable for a software implementation and can be applied to an automated load-pull measurement set-up.
elib2cris::1512001600,pinarello2009
Keywords: S-parameters; VSWR; antenna input terminal; matching network

Highly linear robust RF switch with low insertion loss and high power handling capability in a 65nm CMOS technology - Rascher, Jochen; Pinarello, Sandro; Müller, Jan-Erik; Fischer, Georg; Weigel, Robert (2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2012)
This work reports on the considerations for building RF switches in deeply scaled CMOS. As demonstrator single pole single throw (SPST) switches in a standard 65 nm technology are designed and measured. Goal of this design is lowest insertion loss while achieving high power handling capability, linearity, and robustness. For the novel design of switch variant Dev 1 0.8dB of insertion loss, 30dBm of power handling and an input third order intermodulation intercept point (iIP3) of 48.8 dBm has been achieved at 1.8 GHz. High robustness is achieved by stacking 4 transistors. Isolation at 1.8 GHz is better than 22dB. For high power handling capability in off state a method is implemented to rise the DC voltage level at inner nodes of the switch. Thus the threshold voltage lowering in deeply scaled CMOS can be counteracted. The small and large signal behaviour of the switch is compared to conventional designs and benefits are proven.
elib2cris::1512001600,rascher2012

Impact of DC and RF non-conducting stress on nMOS reliability - Cattaneo, Andrea; Pinarello, Sandro; Müller, Jan-Erik; Weigel, Robert (IEEE International Reliability Physics Symposium (IRPS), 2015)
The increase of leakage current in deep-submicrometer MOS transistors operated below threshold is becoming a reliability concern for scaled technology nodes. Especially high-power analog applications like high efficiency PAs and RF-switches undergo to strong lateral field when Vg <;Vth. Indeed an increased degradation for these MOS applications was already reported in the state of the art but not completely understood. In this paper a thorough study of the DC non-conducting (NC) stress is presented and a new physical model describing the worsening of the electrical parameter is proposed. This model is suitable for being extended to the high frequency regime by means of a quasi-static sum (QS). For the first time RF stress measurements are conducted in various NC configurations. No frequency dependency is detected up to 4Ghz and the QS model is able to precisely predict the performance degradation.
elib2cris::1512001600,cattaneo2015

Methods for Low Insertion Loss RF Switches with Increased Power Handling Capability in 65nm CMOS - Rascher, Jochen; Pinarello, Sandro; Müller, Jan-Erik; Fischer, Georg; Weigel, Robert (Asia-Pacific Microwave Conference 2011 (APMC 2011), 2011)
This work reports on methods and dependencies for the design of low insertion loss single pole single throw (SPST) switches in 65nm CMOS with triple well transistors. Two different switch types are investigated and implemented. The series switch has less than 1dB insertion loss at 1.8GHz and a 1dB input compression point (P1dB) of 28.8dBm. The shunt switch has less than 0.4dB insertion loss at 1.8GHz and a P1dB of 29.1dBm. Isolation of the series and shunt switches at 1.8GHz is better than 21dB and 20dB, respectively. By applying a resistive body ﬂoating technique low insertion loss and increased power handling capability are achieved. At the shunt switch negative gate bias is adopted for improved P1dB. At the series switch a method is implemented to boost the DC voltage level at source/ drain nodes of transistors for improved power handling capability in off state without additional circuitry or any DC power consumption. The combination of these methods andan additional DC voltage in on state increases power handling capability in both states of the switch.
elib2cris::1512001600,rascher2011a

MOSFET degradation under DC and RF Fowler-Nordheim stress - Cattaneo, Andrea; Pinarello, Sandro; Müller, Jan-Erik; Weigel, Robert (44th European Solid State Device Research Conference (ESSDERC), 2014)
Fowler-Nordheim (F-N) stress is reported to be one of the most severe wear-out mechanisms for high-frequency MOSFET applications like PAs and RF switches. Previous studies of this degradation process were limited to the DC-static case only and standard empirical models were proposed. In this work a novel general physical model is developed, which correctly describes the ageing of electrical parameters under DC stress. This is made possible by taking into account the hole injection into the gate oxide. Finally this study extends the understanding of F-N degradation to RF regime. In this case a quasi-static sum of the degradation rate is adopted to accurately model and predict the performance worsening; the wear-out shows no frequency dependency in the range up to 4Ghz.
elib2cris::1512001600,cattaneo2014