A Prototype of an Invasive Tightly-Coupled Processor Array - Muddasani, Shravan; Boppu, Srinivas; Hannig, Frank; Kuzmin, Boris; Lari, Vahid; Teich, Jürgen (Proc. of the 2012 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2012)
Invasive computing is a novel paradigm for the exploitation of runtime parallelism of future MPSoC architectures through resource-aware programming and dynamic reconfiguration of the underlying architectures. Based on the state and availability of resources, an invasive algorithm organizes its computation itself. A highly-parameterizable weakly programmable VLIW processor array called Tightly-Coupled Processor Array (TCPA) that is augmented with decentralized units for hardware-accelerated resource exploration is well suited for invasive computing, especially for accelerating computationally intensive loop programs. We present a prototype of an invasive TCPA, which demonstrates the benefits of invasive computing using the example of video processing. More specifically, the targeted applications in this prototype are 2D convolution filters (such as edge detection and Gaussian filtering) that are applied on a real-time input video stream. For different workload scenarios and resource competition between applications, a varying quality of the output video streams is shown. © 2012 ECSI.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.aproto

Design of low power on-chip processor arrays - Lari, Vahid; Muddasani, Shravan; Boppu, Srinivas; Hannig, Frank; Teich, Jürgen (Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), 2012)
In this paper, we present an ultra low power design for a class of massively parallel architectures, called tightly-coupled processor arrays.Here, the key idea is to exploit the benefits of a decentralized resource management as inherent to invasive computing for power saving.We propose concepts and studying different architecture trade-offs for hierarchical power management by temporarily shutting down regions of processors through power gating. Moreover, a) overall system chip energy consumption, b) hardware cost, and c) timing overheads are compared for different sizes of power domains.Experimental results show that up to 70% of system energy consumption may be saved for selected characteristical algorithms and different resource utilizations. © 2012 IEEE.

Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays - Lari, Vahid; Muddasani, Shravan; Boppu, Srinivas; Hannig, Frank; Schmid, Moritz; Teich, Jürgen (ACM Transactions on Design Automation of Electronic Systems, 2012)
We present a self-adaptive hierarchical power management technique for massively parallel processor architectures, supporting a new resource-aware parallel computing paradigm called invasive computing. Here, an application can dynamically claim, execute, and release the resources in three phases: resource acquisition (invade), program loading/configuration and execution (infect), and release (retreat). Resource invasion is governed by dedicated decentralized hardware controllers, called invasion controllers (iCtrls), which are integrated into each processing element (PE). Several invasion strategies for claiming linearly connected or rectangular regions of processing resources are implemented. The key idea is to exploit the decentralized resource management inherent to invasive computing for power savings by enabling applications themselves to control the power for processing resources and invasion controllers using a hierarchical power-gating approach. We propose analytical models for estimating various components of energy consumption for faster design space exploration and compare them with the results obtained from a cycle-accurate C++ simulator of the processor array. In order to find optimal design trade-offs, various parameters like (a) energy consumption, (b) hardware cost, and (c) timing overheads are compared for different sizes of power domains. Experimental results show significant energy savings (up to 73%) for selected characteristical algorithms and different resource utilizations. In addition, we demonstrate the accuracy of our proposed analytical model. Here, estimation errors less than 3.6% can be reported. © 2012 ACM.
UnivIS-Import:2015-03-09:Pub.2012.tech.IMMD.inform.hierar
Keywords: Adaptive power optimization; Parallel computing; Resource awareness; Runtime resource management; Timing overhead minimization