Evaluating a Simulation based PLC Processor Optimization - Kohl, Johannes; Bauer, Wolfgang; Bäsig, Jürgen; Fey, Dietmar (ISC 2017, 2017)
UnivIS-Import:2017-12-18:Pub.2017.tech.IMMD.IMMD3.evalua_54

Evaluating HSA-Compatible Heterogeneous Systems for ADAS Applications - Bauer, Wolfgang; Holzinger, Philipp; Rachuj, Sebastian; Häublein, Konrad; Reichenbach, Marc; Fey, Dietmar (Workshop Proceedings, 2019)

Evaluation of a Sensor Fusion Algorithm on a Real-Time Processor - Rachuj, Sebastian; Bauer, Wolfgang; Fey, Dietmar (AmE 2018 - Automotive meets Electronics, 2018)
UnivIS-Import:2018-02-22:Pub.2018.tech.IMMD.IMMD3.evalua

Generation of Executable Runtime Constrained Random Programs Functional Processor Verification - Bauer, Wolfgang; Kohl, Johannes; Bäsig, Jürgen; Rübesam, Stefan; Fey, Dietmar (ESM 2016, 2016)
The functional verification of multi-issue deep pipeline processor architectures exceeds the complexity level manageable with static test methods. A randomized approach including automatic test program generation leads to instruction sequences not anticipated and reaches the verification requirements. The challenge is to generate programs that on the one hand are deterministic and terminate for all possible inputs and on the other hand cover the entire instruction set. Moreover for out of order architectures the dependencies between instructions must be taken into account and therefore the instruction sequencing must be part of the coverage. In this paper we present a random program generation technique that produces executable runtime self-constraining deterministic random programs for processor verification. The core elements are a template based program flow generation, program termination certainty and runtime error protection. To avoid unpredictable or illegal situations during program execution value constraining blocks are added to program areas with uncertain behavior.
UnivIS-Import:2017-12-18:Pub.2016.tech.IMMD.IMMD3.genera
Keywords: Branch behavior verification; Functional processor verification; Instruction sequence coverage; Random program generation

Latency Measurements for an Emulation Platform on Autonomous Driving Platform NVIDIA Drive PX2 - Widerspick, Christian; Bauer, Wolfgang; Fey, Dietmar (ARCS Workshop 2018; 31th International Conference on Architecture of Computing Systems, 2018)

Processor Error Detection Capabilities of Random Programs - Kohl, Johannes; Bauer, Wolfgang; Bäsig, Jürgen; Rübesam, Stefan; Fey, Dietmar (Tagungsband TuZ 2017, 2017)
UnivIS-Import:2017-12-18:Pub.2017.tech.IMMD.IMMD3.proces

Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems - Bauer, Wolfgang; Holzinger, Philipp; Reichenbach, Marc; Vaas, Steffen; Hartke, Paul; Fey, Dietmar (Euro-Par 2018: Parallel Processing Workshops, 2019)
Modern algorithms for virtual reality, machine learning or big data find its way into more and more application fields and result in stricter power per watt requirements. This challenges traditional homogeneous computing concepts and drives the development of new, heterogeneous architectures. One idea to attain a balance of high data throughput and flexibility are GPU-like soft-core processors combined with general purpose CPUs as hosts. However, the approaches proposed in recent years are still not sufficient regarding their integration in a shared hardware environment and unified software stack. The approach of the HSA Foundation provides a complete communication definition for heterogeneous systems but lacks FPGA accelerator support. Our work presents a methodology making soft-core processors HSA compliant within MPSoC systems. This enables high level software programming and therefore eases the accessibility of soft-core FPGA accelerators. Furthermore, the integration effort is kept low by fully utilizing the HSA Foundation standards and toolchains.
CRIS-Team Scopus Importer:2019-05-02
Keywords: FPGA; Heterogeneous system architecture; HSA foundation; Nyuzi processor; Programmable accelerator; Zynq ultrascale+