Accelerating Veins Simulations by Utilizing Task Parallelism on a HPC Cluster Without Introducing Major Inaccuracies - Fritscher, Markus; Dengler, Gabriel; Bleibaum, Cord; Niebisch, Michael; German, Reinhard (13th International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP), 2022)
The evaluation of large-scale vehicular networks has proven difficult. The researcher has to either do a lot of experiments, reduce simulation accuracy or endure simulation runtimes prohibiting a reasonable investigation. We present a framework that allows preserving simulation accuracy while maintaining reasonable simulation times by cutting the to-be-investigated area into individual tiles. Instead of running on a single CPU core we are able to run the simulation on hundreds of HPC servers in parallel. This yields a speedup of several orders of magnitude, allowing the simulation of entire cities. We validate our approach by investigating different access-point distributions for the city of Ingolstadt.<br
Keywords: SUMO; OMNeT++; Veins; HPC; simulation

A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories - Knödtel, Johannes; Fritscher, Markus; Reiser, Daniel; Fey, Dietmar; Breiling, Marco; Reichenbach, Marc (9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020, Bremen, Germany, September 7-9, 2020, 2020)
With the emergence of DNN accelerators the main focus of such systems usually lies on utilizing local memories and reducing the size of the processed data, since delay and energy consumption are dominated by data transfer. Utilizig emerging memory technologies, such as ReRAMs, these goals might be attained much easier, due to advantageous non-functional and functional properties.One of the key drawbacks of such systems are reliability and variability of devices of such technologies. To certain degree, DNNs are resilient to soft and hard errors in their memory cells, so these issues might be surmountable depending on the device properties, but eludes trivial analyses known from the digital domain. Here the dynamic behavior of the devices comes into play and must be simulated in order to get a decent degree of confidence on the reliability of the hardware and therefore also yield.In order to tackle this issue we present an accelerator architecture and matching analysis pipeline that allows the user to specify and train a net topology and then test the design against some input activations with different randomized device properties. Using this approach we can estimate the inference results and other system and algorithm level properties in presence of different device level properties which might for example be extracted from real world measurements. Such a system can help the user in the design of their net or give them hints on the required device properties for a given net or aid them in evaluating existing designs.
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