A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter - Löhr, Robert; Stadelmayer, Markus; Röber, Jürgen; Ohnhäuser, Frank; Weigel, Robert (ECCTD, 2017)
High-Performance Analog-to-Digital Converter (ADC) have high requirements concerning sampling rate and linearity. Therefore a new formula is derived to determine, which pipeline stage dependent on the used capacitor sizes needs to be calibrated for the targeted linearity. Furthermore, a model of a 16 bit and 200MS/s pipeline ADC is described. A combination of a digital foreground and a digital background calibration is presented, which can compensate linear errors and achieves a DNL smaller than ±1 and a THD of -88 dB.
Keywords: Pipeline ADC; modeling; common mode jump; capacitor-flip-over architecture; digital calibration; foreground; background; high resolution.

Analysis of the Settling Behavior of an External Reference Voltage Source for a 16 Bit and 200 MS/s Pipeline Analog-to-Digital Converter - Löhr, Robert; Bender, Leon; Röber, Jürgen; Ohnhäuser, Frank; Weigel, Robert (24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017)
High-Performance Analog to Digital Converter (ADC) have high requirements concerning the reference voltage source. In a small period of time the reference voltage has to settle with a high accuracy. Otherwise the linearity of the ADC degrades. In this paper the settling of an external reference voltage source is examined. Therefore optimization techniques for the signal path of the reference voltage are presented. This includes methods for reducing the external parasitic inductanceas well as design techniques for an enhanced settling curve. Under typical conditions, the achieved reference voltage source settles with an accuracy of 15 uV in less than halve a clock cycle for a 200 MS/s and 16 bits Pipeline ADC.
Keywords: reference voltage; settling; Pipeline ADC; external parasitic inductance; attenuation

Implementation of a High-Speed Flash ADC for High Performance Pipeline ADCs in an 180nm CMOS Process - Löhr, Robert; Kempf, Markus; Ohnhäuser, Frank; Röber, Jürgen; Weigel, Robert; Bänisch, Andreas (International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2015)
Pipeline Analog to Digital Converters (ADC) use a sub-ADC in each pipeline stage. They require a much higher sampling rate and less accuracy. For that reason Flash ADCs are predestined for sub-ADCs. In this paper a differential Flash ADC is presented for a targeted pipeline ADC with 16 Bit, 200 MS/s and a 1.5 Bit resolution per stage. The overall accuracy of the Flash ADC is 30mV and a typical propagation delay of around 400 ps is achieved. This corresponds to a sampling rate of 2.5 GS/s. In addition, a new numerical method for an effective simulation of the propagation delay and offset is presented.
elib2cris::1512001600,loehr2015

Switch Bootstrapping in a 1.5 Bit Pipeline Stage - Löhr, Robert; Ohnhäuser, Frank; Röber, Jürgen; Weigel, Robert (Analog2016, 2016)
The targeted 16 bit pipeline converter has an adjustable sampling frequency from 100MHz to 200MHz. In this paper the switches for the input and the reference voltage sampling are analyzed. Therefore, a novel switch bootstrapping technique is presented, which guarantees a worst case input voltage settling accuracy of LSB 2 at settling times between 2 ns to 5 ns. The non-linearity caused by the input switches is simulated and typically amounts to -115 dB. In addition a possible solution for external reference voltage settling is introduced.
elib2cris::1512001600,loehr2016
Keywords: 1.5 bit; switch bootstrapping; MDAC; charge injection; external reference; non-linearity