System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems - Pourmohseni, Behnaz (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2021)

System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems - Pourmohseni, Behnaz; Teich, Jürgen (PhD Forum at the Design, Automation, and Test in Europe (DATE) Conference and Exhibition, 2020)

System-level Mapping of Dataflow Applications onto MPSoCs - Schwarzer, Tobias (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2020)

System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC - Streubühr, Martin; Riedel, Christian; Haubelt, Christian; Teich, Jürgen (Proceedings of 10. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", 2007)

System-Level Modeling and Simulation of Networked PROFINET IO Controllers - Zhang, Liyuan; Streubühr, Martin; Glaß, Michael; Teich, Jürgen; von Schwerin, Andreas; Liu, Kai (Proc. of the Embedded World Conference, 2012)
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.system

System-Level Optimization and Code Generation for Graphics Processors using a Domain-Specific Language - Qiao, Bo (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2021)

System Level Performance Simulation for Heterogeneous Multi-Processor Architectures - Streubühr, Martin; Haubelt, Christian; Teich, Jürgen (1st HiPEAC Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), in conjunction with the 4th HiPEAC Conference, 2009)

System-Level Power and Performance Estimation in Early SoC Design Phases - Xu, Yang (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2015)

System-Level Reliability Analysis and Optimization in the Presence of Uncertainty - Khosravi, Faramarz (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2019)

System-Level Reliability Analysis Considering Imperfect Fault Coverage - Khosravi, Faramarz; Aliee, Hananeh; Teich, Jürgen (15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), 2017)
Safety-critical systems rely on redundancy schemes such as k-out-of-n structures which enable tolerance against multiple faults. These techniques are subject to Imperfect Fault Coverage (IFC) as error detection and recovery might be prone to errors or even impossible for certain fault models. As a result, these techniques may act as single points of failure in the system where uncovered faults might be overlooked and lead to wrong system outputs. Neglecting IFC in reliability analysis may lead to fatal overestimations in case of safety-critical applications. Yet, existing techniques that do consider IFC are overly pessimistic in assuming that the occurrence of an uncovered fault always results in a system failure. But often, in particular in complex systems with nested redundant structures, a fault that is not noticed by an inner redundancy scheme might be caught by an outer redundancy scheme. This paper proposes to automatically incorporate IFC into reliability models, i. e. Binary Decision Diagrams (BDDs), to enable an accurate reliability analysis for complex system structures including nested redundancies and repeated components. It also shows that IFC does not equally affect different redundancy schemes. Experimental results presented for applications in multimedia and automotive confirm that the proposed approach can analyze system reliability more accurately at an acceptable execution time and memory overhead compared to the underlying IFC-unaware technique.
Keywords: Reliability; redundancy; imperfect fault coverage; binary decision diagrams

System Level Synthesis Flow for Self-adaptive Multi-mode Reconfigurable Systems - Wildermann, Stefan; Reimann, Felix; Ziener, Daniel; Teich, Jürgen (Proc. of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012)
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.system_8

System-Level Synthesis Using Evolutionary Algorithms - Blickle, Tobias; Teich, Jürgen; Thiele, Lothar (Design Automation For Embedded Systems, 1998)
In this paper, we consider system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the selection of the architecture (allocation) including general purpose and dedicated processors, ASICs, busses and memories, (2) the mapping of the specification onto the selected architecture in space (binding) and time (scheduling), and (3) the design space exploration with the goal to find a set of implementations that satisfy a number of constraints on cost and performance. Existing methodologies often consider a fixed architecture, perform the binding only, do not reflect the tight interdependency between binding and scheduling, do not consider communication (tasks and resources), or require long run-times preventing design space exploration, or yield only one implementation with optimal cost. Here, a model is introduced that handles all mentioned requirements and allows the task of system-synthesis to be specified as an optimization problem. The application and adaptation of an Evolutionary Algorithm to solve the tasks of optimization and design space exploration is described.
UnivIS-Import:2015-03-05:Pub.1998.tech.IMMD.inform.system
Keywords: Design space exploration; Evolutionary algorithms; Hardware/software partitioning; System-synthesis

System-level synthesis using evolutionary algorithms - Teich, Jürgen; Thiele, Lothar (1996)

SysteMoC: A Data-Flow Programming Language for Codesign - Falk, Joachim; Haubelt, Christian; Teich, Jürgen; Zebelein, Christian (Handbook of Hardware/Software Codesign, 2017)
Computations in hardware/software systems are inherently performed concurrently. Hence, modeling hardware/software systems requires notions of concurrency. Data-flow models have been and are still successfully applied in the modeling of hardware/software systems. In this chapter, we motivate and introduce the usage of data-flow models. Moreover, we discuss the expressiveness and analyzability of different data-flow Models of Computation (MoCs). Subsequently, we present SysteMoC, an approach supporting many data-flow MoCs based on the system description language SystemC. Besides specifying data-flow models, SystemMoC also permits the automatic classification of each different part of an application modeled in SysteMoC into a least expressive but most analyzable MoC. This classification is the key to further optimization in later design stages of hardware/software systems, such as exploration of design alternatives as well as automatic code generation and hardware synthesis. Such optimization and refinement steps are employed as part of the extscSystemCoDesigner design flow that uses SysteMoC as its input languag
Keywords: dataflow; SysteMoC; SystemCoDesigner

Systems of Partial Differential Equations in ExaSlang - Schmitt, Christian; Kuckuk, Sebastian; Hannig, Frank; Teich, Jürgen; Köstler, Harald; Rüde, Ulrich; Lengauer, Christian (Software for Exascale Computing - SPPEXA 2013-2015, 2016)
As HPC systems are becoming increasingly heterogeneous and diverse, writing software that attains maximum performance and scalability while remaining portable as well as easily composable is getting more and more challenging. Additionally, code that has been aggressively optimized for certain execution platforms is usually not easily portable to others without either losing a great share of performance or investing many hours by re-applying optimizations. One possible remedy is to exploit the potential given by technologies such as domain-specific languages (DSLs) that provide appropriate abstractions and allow the application of technologies like automatic code generation and auto-tuning. In the domain of geometric multigrid solvers, project ExaStencils follows this road by aiming at providing highly optimized and scalable numerical solvers, specifically tuned for a given application and target platform. Here, we introduce its DSL ExaSlang with data types for local vectors to support computations that use point-local vectors and matrices. These data types allow an intuitive modeling of many physical problems represented by systems of partial differential equations (PDEs), e.g., the simulation of flows that include vector-valued velocitie
UnivIS-Import:2017-01-09:Pub.2016.tech.IMMD.lsinfs.system

Szenarienbasierte Integration von Diagnosefunktionalität in E/E Architekturen - Reimann, Felix; Glaß, Michael; Teich, Jürgen; Abelein, Ulrich (Proc. Automotive meets Electronics, GMM Fachbericht 75, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.szenar

Task-accurate performance modeling in SystemC for real-time multi-processor architectures - Streubühr, Martin; Falk, Joachim; Teich, Jürgen; Haubelt, Christian; Dorsch, Rainer; Schlipf, Th (Proceedings of Design, Automation and Test in Europe (DATE 2006), IEEE Computer Society, 2006)
We propose a novel framework, called Virtual Processing Components (VPC), that permits the modeling and simulation of multiple processors running arbitrary scheduling strategies in SystemC. The granularity is given by task accuracy that guarantees a small simulation overhead.

Task Graph Clustering with Internal State - Falk, Joachim; Haubelt, Christian; Teich, Jürgen (2007)

Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems - Pourmohseni, Behnaz; Wildermann, Stefan; Smirnov, Fedor; Meyer, Paul; Teich, Jürgen (IEEE Access, 2022)

Task Scheduling for Heterogeneous Reconfigurable Computers - Ahmadinia, Ali; Bobda, Christophe; Koch, Dirk; Majer, Mateusz; Teich, Jürgen (Proceedings of the 17th Symposium on Integrated Circuits and Systems Design (SBCCI), 2004)
We consider the problem of executing a dynamically changing set of tasks on a reconfigurable system, made upon a processor and a reconfigurable device. Task execution on such a platform is man-aged by a scheduler that can allocate tasks either to the processor or to the reconfigurable device. The scheduler can be seen as part of an operating system running on the software or as core in the reconfigurable device. For each tasks to be executed on reconfigurable device, an equivalent implementation exists as rectangular block in a database. This block has to be placed on the device at run-time. A placer is responsible for the placement of tasks received from the scheduler on the reconfigurable device. However, the placement of tasks on the reconfigurable device will not be succesful if enough space is not available on the device to hold the task. In this case the scheduler receive an acknowledgment from the placer and decide either to preempt a running task or to run the task on software. We present in this work an implementation of a placer module as well as investigations on task preemption. The two modules are part of an operating system for reconfigurable system currently under development.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.tasksc_0
Keywords: FPGA; Hardware Preemption; Partial Reconfiguration; Placement; Reconfigurable Computing; Scheduling

TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays - Sousa, Éricles; Chakraborty, Arindam; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2017)

Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs - Ziener, Daniel (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2010)

Techniques for on-demand structural redundancy for massively parallel processor arrays - Teich, Jürgen; Lari, Vahid; Tanase, Alexandru-Petru; Witterauf, Michael; Khosravi, Faramarz; Meyer, Brett (Journal of Systems Architecture, 2015)
In this paper, we present techniques for providing on-demand structural redundancy for Coarse-Grained Reconfigurable Array (CGRAs) and a calculus for determining the gains of reliability when applying these replication techniques from the perspective of safety-critical parallel loop program applications. Here, for protecting massively parallel loop computations against errors like soft errors, well-known replication schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) must be applied to each single Processor Element (PE) rather than one based on application requirements for reliability and Soft Error Rates (SERs). Moreover, different voting options and signal replication schemes are investigated. It will be shown that hardware voting may be accomplished at negligible hardware cost, i. e. less than two percent area overhead per PE, for a class of reconfigurable processor arrays called Tightly Coupled Processor Arrays (TCPAs). As a major contribution of this paper, a formal analysis of the reliability achievable by each combination of replication and voting scheme for parallel loop executions on CGRAs in dependence of a given SER and application timing characteristics (schedule) is elaborated. Using this analysis, error detection latencies may be computed and proper decisions which replication scheme to choose at runtime to guarantee a maximal probability of failure on-demand can be derived. Finally, fault-simulation results are provided and compared with the formal analysis of reliability.
Keywords: Coarse-grained reconfigurable Architectures; Fault tolerance; Reliability analysis

Techniques to Secure HW/SW-Programmable SoC Architectures for Edge Computing - Streit, Franz-Josef (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2022)

Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs) - Glocker, E.; Boppu, Srinivas; Chen, Q.; Schlichtmann, U.; Teich, Jürgen; Schmitt-Landsiedel, D. (Advances in Radio Science, 2014)
This contribution provides an approach for emulating the behaviour of an ASIC temperature monitoring system (TMon) during run-time for a tightly-coupled processor array (TCPA) of a heterogeneous invasive multi-tile architecture to be used for FPGA prototyping. It is based on a thermal RC modeling approach. Also different usage scenarios of TCPA are analyzed and compared.

Temporal Task Clustering for Online Placement on Reconfigurable Hardware - Ahmadinia, Ali; Bobda, Christophe; Teich, Jürgen (Proceedings of the IEEE International Conference on Field-Programmable Technology, 2003)
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.tempor

Testfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen - Gladigau, Jens; Haubelt, Christian; Streubühr, Martin; Teich, Jürgen; Schneider, Axel; Knäblein, Joachim; Lindig, Michael (Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2009)

Testing Switched Ethernet Networks in Automotive Embedded Systems - Kern, Andreas; Zhang, Hongyan; Streichert, Thilo; Teich, Jürgen (Proceedings of the 6th IEEE International Symposium on Industrial Embedded Systems (SIES'11), 2011)
Ethernet is currently being discussed within the automotive community to become a general network technology for interconnecting future distributed automotive systems. If this is the case, a complete tool chain will be necessary to support developers to implement their functions. One important component is the availability of tools to monitor, generate, manipulate, and simulate traffic in distributed embedded systems. Today's established communication technologies like LIN, CAN, or FlexRay have the enormous advantage to be based on a physical shared medium which makes it relatively easy to add an additional test device to a network under test. This paper describes an approach to implement such a test device for switched Ethernet networks, presents performance measurements of our implemented Ethernet-Test-Switch, and introduces a concept to integrate simulated and existing devices with each other. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.testin
Keywords: Ethernet; IP; network simulation; packet generation; packet monitoring; switch; testing; UDP

The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL - Qiao, Bo; Özkan, Mehmet Akif; Teich, Jürgen; Hannig, Frank (Proceedings of the 57th Annual Design Automation Conference (DAC), 2020)
CUDA graph is an asynchronous task-graph programming model recently released by Nvidia. It encapsulates application workflows in a graph, with nodes being operations connected by dependencies. The new API brings two benefits: Reduced work launch overhead and whole workflow optimizations. In this paper, we improve the ability of CUDA graph to exploit workflow optimizations, e.g. concurrent kernel executions with complementary resource occupancy. Additionally, we argue that the advantages of DSLs are complementary to CUDA graph, and joining the two techniques can benefit from the best of both worlds. Here, we propose a compiler-based approach that combines CUDA graph with an image processing DSL and a source-to-source compiler called Hipacc. For ten image processing applications benchmarked on two Nvidia GPUs, our approach is able to achieve a geometric mean speedup of 1.30 over Hipacc without CUDA graph, 1.11 over CUDA graph without Hipacc, and 3.96 over another state-of-the-art DSL called Halid

The concepts of COMPAR: A compiler for massive parallel architectures - Arzt, Ulrich; Teich, Jürgen; Thiele, Lothar (Proc. International Symposium on Circuits and Systems, 1992)
UnivIS-Import:2015-04-16:Pub.1992.tech.IMMD.inform.thecon

The Connectedness of Clash-free Timetables - Mühlenthaler, Moritz; Wanka, Rolf (Proc. 10th Int. Conf. on the Practice and Theory of Automated Timetabling (PATAT), 2014)
We investigate the connectedness of clash-free timetables with respect to the Kempe-exchange operation. This investigation is related to the connectedness of the search space of timetabling problem instances, which is a desirable property, for example for twostep algorithms using the Kempe-exchange during the optimization step. The theoretical framework for our investigations is based on the study of reconfiguration graphs, which model the search space of timetabling problems. We contribute to this framework by including period availability requirements in the analysis and we derive improved conditions for the connectedness of clash-free timetables in this setting. We further show that the diameter of the reconfiguration graphs increases only linearly due to the period availability requirements. We apply the theoretical insights to establish the connectedness of clash-free timetables for a number of benchmark instances.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.infalg._theco

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer - Bobda, Christophe; Majer, Mateusz; Teich, Jürgen; Ahmadinia, Ali (Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2007)
UnivIS-Import:2015-04-14:Pub.2006.tech.IMMD.inform.theerl

The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform - Ahmadinia, Ali; Bobda, Christophe; Fekete, Sandor P.; Haller, Thomas; Linarth, Andre Guilherme; Majer, Mateusz; Teich, Jürgen; Van Der Veen, Jan C. (Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), 2005)
We present a new concept as well as the implementation of an FPGA-based reconfigurable platform, the Erlangen Slot Machine (ESM). The main advantages of this platform are: first, the possibility for each module to access its peripheries independent from its location through a programmable crossbar, and distributed SRAMs among slices. This allows an unrestricted relocation of modules on the device. Second, the intermodule structure allows an unlimited communication among running modules. © 2005 IEEE.
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.theerl

The Erlangen Slot Machine - An FPGA-Based Partially Reconfigurable Computer - Majer, Mateusz (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2011)

The Erlangen Slot Machine: A Platform for Interdisciplinary Research in Reconfigurable Computing - Angermeier, Josef; Göhringer, Diana; Majer, Mateusz; Teich, Jürgen; Fekete, Sandor P.; Van Der Veen, Jan C. (it - Information Technology, 2007)
UnivIS-Import:2015-03-09:Pub.2007.tech.IMMD.inform.theerl_8

The Gender Gap in Computer Science — A Bibliometric Analysis - Mattauch, Sandra; Lohmann, Katja; Hannig, Frank; Lohmann, Daniel; Teich, Jürgen (2018)

The Handbook of Hardware/Software Codesign - Ha, Soonhoi; Teich, Jürgen (Springer, 2017)

The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids - Alhaddad, Samer; Förstner, Jens; Groth, Stefan; Grünewald, Daniel; Grynko, Yevgen; Hannig, Frank; Kenter, Tobias; Pfreundt, Franz-Josef; Plessl, Christian; Schotte, Merlind; Steinke, Thomas; Teich, Jürgen; et al. (Concurrency and Computation-Practice & Experience, 2021)

The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure - Weichslgartner, Andreas; Teich, Jürgen (Proc. of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), 2014)
UnivIS-Import:2015-04-17:Pub.2014.tech.IMMD.inform.theinv

Theoretical Analysis of Fair Bandwidth Sharing in Priority-based Medium Access - Wildermann, Stefan; Teich, Jürgen (2008)

Theoretical Analysis of Initial Particle Swarm Behavior - Helwig, Sabine; Wanka, Rolf (Proceedings of the 10th International Conference on Parallel Problem Solving from Nature, 2008)
In this paper, particle trajectories of PSO algorithms in the first iteration are studied. We will prove that many particles leave the search space at the beginning of the optimization process when solving problems with boundary constraints in high-dimensional search spaces. Three different velocity initialization strategies will be investigated, but even initializing velocities to zero cannot prevent this particle swarm explosion. The theoretical analysis gives valuable insight into PSO in high-dimensional bounded spaces, and highlights the importance of bound handling for PSO: As many particles leave the search space in the beginning, bound handling strongly influences particle swarm behavior. Experimental investigations confirm the theoretical results. © 2008 Springer-Verlag Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.infalg._theor

Theory of particle swarm optimization: A survey of the power of the swarm’s potential - Bassimir, Bernd; Raß, Alexander; Schmitt, Manuel (it - Information Technology, 2019)
This paper presents a survey on different showcases for potential measures on particle swarm optimization (PSO). First, a potential is analyzed to prove convergence to non-optimal points. Second, one can apply a minor modification to PSO to prevent convergence to non-optimal points by using an easy potential measure. Finally, analyzing this potential measure yields a reliable stopping criterion for the modified PS
Keywords: Particle swarm optimization; potential; meta-heuristics

The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications - Hannig, Frank; Ruckdeschel, Holger; Teich, Jürgen (Proceedings of the GI/ITG/GMM-Workshop – Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2008)
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.thepau

The Randomized Sample Tree: A Data Structure for Externally Stored Virtual Environments - Meyer auf der Heide, Friedhelm; Fischer, Matthias; Krokowski, Jens; Klein, Jan; Wanka, Rolf; Wand, Michael (Presence-Teleoperators and Virtual Environments, 2004)
We present a new data structure for rendering highly complex virtual environments of arbitrary topology. The special feature of our approach is that it allows an interactive navigation in very large scenes (30 GB/400 million polygons in our benchmark scenes) that cannot be stored in main memory, but only on a local or remote hard disk. Furthermore, it allows interactive rendering of substantially more complex scenes by instantiating objects. The sampling process is done in the preprocessing. There, the polygons are randomly distributed in our hierarchical data structure, the randomized sample tree. This tree uses only space that is linear in the number of polygons. In order to produce an approximate image of the scene, the tree is traversed and polygons stored in the visited nodes are rendered. During the interactive walk-through, parts of the sample tree are loaded from a local or remote hard disk. We implement our algorithm in a prototypical walk-through system. Analysis and experiments show that the quality of our images is comparable to images computed by the conventional z-buffer algorithm regardless of the scene topology. © 2005 by the Massachusetts Institute of Technology.
UnivIS-Import:2015-03-09:Pub.2004.tech.IMMD.inform.theran

The randomized sample tree: A data structure for interactive walkthroughs in externally stored virtual environments - Klein, Jan; Krokowski, Jens; Wand, Michael; Fischer, Matthias; Wanka, Rolf; Meyer auf der Heide, Friedhelm (Proc. ACM Symp. on Virtual Reality Software and Technology (VRST), 2002)
We present a new data structure for rendering highly complex virtual environments of arbitrary topology. The special feature of our approach is that it allows an interactive navigation in very large scenes (30 GB/400 million polygons in our benchmark scenes) that cannot be stored in main memory, but only on a local or remote hard disk. Furthermore, it allows interactive rendering of substantially more complex scenes by instantiating objects. For the computation of an approximate image of the scene, a sampling technique is used. In the preprocessing, a so-called sample tree is built whose nodes contain randomly selected polygons from the scene. This tree only uses space that is linear in the number of polygons. In order to produce an image of the scene, the tree is traversed and polygons stored in the visited nodes are rendered. During the interactive walkthrough, parts of the sample tree are loaded from local or remote hard disk. We implemented our algorithm in a prototypical walkthrough system. Analysis and experiments show that the quality of our images is comparable to images computed by the conventional z-buffer algorithm regardless of the scene topology.
Keywords: Level of Detail Algorithms; Monte Carlo Techniques; Out-Of-Core Rendering; Point Sample Rendering; Rendering Systems; Spatial Data Structures

The ReProVide Query-Sequence Optimization in a Hardware-Accelerated DBMS - Beena Gopalakrishnan Nair, Lekshmi; Becher, Andreas; Meyer-Wegener, Klaus (DaMoN '20: Proceedings of the 16th International Workshop on Data Management on New Hardware, 2020)
Hardware acceleration of database query processing can be done with the help of FPGAs. In particular, they are partially reconfigurable at runtime, which allows for the adaptation to a variety of queries. Reconfiguration itself, however, takes some time. This paper presents optimizations based on query sequences, which reduce the impact of the reconfigurations. Knowledge of upcoming queries is used to avoid reconfiguration overhead. We evaluate our optimizations with a calibrated model. Improvements in execution time of up to 28% can be obtained even with sequences of only two querie

Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems - Pourmohseni, Behnaz; Smirnov, Fedor; Khdr, Heba; Wildermann, Stefan; Teich, Jürgen; Henkel, Jörg (Proceedings of the 40th IEEE Real-Time Systems Symposium (RTSS), 2019)

The role of e-dominance in Multi-Objective Particle Swarm Optimization Methods - Mostaghim, Sanaz; Teich, Jürgen (Proceedings of the Congress on Evolutionary Computation (CEC'03), 2003)
In this paper, the influence of ε-dominance on multi-objective particle swarm optimization (MOPSO) methods is studied. The most important role of ε-dominance is to bound the number of non-dominated solutions stored in the archive (archive size), which has influences on computational time, convergence and diversity of solutions. Here, ε-dominance is compared with the existing clustering technique for fixing the archive size and the solutions are compared in terms of computational time, convergence and diversity. A new diversity metric is also suggested. The results show that the ε-dominance method can find solutions much faster than the clustering technique with comparable and even in some cases better convergence and diversity. © 2003 IEEE.
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.therol

The Spectral Relation between the Cube-Connected Cycles and the Shuffle-Exchange Network - Riess, Christian; Strehl, Volker; Wanka, Rolf (Proc. 10th Workshop on Parallel Systems and Algorithms (PASA) of the 25th Int. Conf. on Architecture of Computing Systems (ARCS), 2012)

Three-dimensional localization of bats: visual and acoustical - Hochradel, Klaus; Häcker, Timm; Hohler, Tino; Becher, Andreas; Wildermann, Stefan; Sutor, Alexander (IEEE Sensors Journal, 2019)
Keywords: Acoustics; Cameras; Microphone arrays; Hardware; Sensors; Data acquisition; Microphone; Array; Stereo Camera; Infrared; automation; Ultrasound; Source localization; Bat

Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks using Multi-Reader Buffers - Letras, Martin; Falk, Joachim; Teich, Jürgen (Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023), 2023)

Throughput-optimizing compilation of dataflow applications for multi-cores using quasi-static scheduling - Schwarzer, Tobias; Falk, Joachim; Glaß, Michael; Teich, Jürgen; Zebelein, Christian; Haubelt, Christian (Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2015)
Application modeling using dynamic dataflow graphs is wellsuited for multi-core platforms. However, there is often a mismatch between the fine granularity of the application and the platform. Tailoring this granularity to the platform promises performance gains by (a) reducing dynamic scheduling overhead and (b) exploiting compiler optimizations. In this paper, we propose a throughput-optimizing compilation approach that uses Quasi-Static Schedules (QSSs) to combine actors of static dataflow subgraphs. Our proposed approach combines core allocation, QSSs, and actor binding in a Design Space Exploration (DSE), optimizing the throughput for a number of available cores. During the DSE, each implementation candidate is compiled to and evaluated on the target hardware-here an Intel i7 and an ARM Cortex-A9. Experimental results including synthetic benchmarks as well as a real-world control application show that our proposed holistic compilation approach outperforms classic DSEs that are agnostic of QSS as well as a DSE that employs QSS as a post-processing step. Amongst others, we show a case where the compilation approach obtains a speedup of 9.91 x for a 4-core implementation, while a classic DSE only obtains a speedup of 2.12 x.
Keywords: Clustering; Compilation; Dataflow; Design space exploration; Multi-core

Time-Critical Systems Design: A Survey - Mitra, Tulika; Teich, Jürgen; Thiele, Lothar (IEEE Design and Test of Computers, 2018)

Time Synchronization - Streichert, Thilo; Busse, Marcel (Algorithms for Sensor and Ad Hoc Networks, 2007)
UnivIS-Import:2015-04-20:Pub.2007.tech.IMMD.inform.timesy

Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays - Gangadharan, Deepak; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES), 2014)

Timing Analysis of Ethernet AVB-based Automotive E/E Architectures - Reimann, Felix; Graf, Sebastian; Streit, Fabian; Glaß, Michael; Teich, Jürgen (Proc. IEEE International Conference on Emerging Technology & Factory Automation, 2013)
Due to ever-increasing bandwidth requirements of modern automotive applications, Ethernet AVB is becoming a standard high-speed bus in automotive E/E architectures. Since Ethernet AVB is tailored to audio and video entertainment, existing analysis approaches neglect the specific requirements and features of heterogeneous E/E architectures and their applications. This paper presents a timing analysis technique based on Real Time Calculus to consider Ethernet AVB in complex E/E architectures, reflecting key features such as static routing and stream reservation, fixed topology, and real-time applications. A comparison with a simulation on case studies from the automotive domain gives evidence that the proposed technique delivers valuable bounds for complete sensor-to-actuator chains, enabling automatic system synthesis and design space exploration approaches. © 2013 IEEE.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.timing

Timing Analysis of Systems of Communicating Tasks with Internal State - Teich, Jürgen (2006)

Timing Verification of Realtime Automotive Networks: What can we expect from Simulation? - Navet, Nicolas; Seyler, Jan; Migge, Jörn (Proceedings of the 8th European Congress on Embedded Real Time Software and Systems (ERTS), 2016)

Toolchain-Independent Variant Management with the Leviathan Filesystem - Hofer, Wanja; Elsner, Christoph; Blendinger, Frank; Schröder-Preikschat, Wolfgang; Lohmann, Daniel (Proceedings of the 2nd Workshop on Feature-Oriented Software Development (FOSD 2010), 2010)
Preprocessor-configured software needs tool support for the developer to be able to cope with the complexity introduced by optional and alternative code blocks in the source. Current approaches, which assist the software developer by providing preprocessed views, are all bound to a special integrated development environment. This eliminates them from being used both in industry settings (where domain-specific toolchains are often mandated) and in open-source projects (where diverse sets of editors and tools are being used and freedom of tool choice is crucial for the project success). We therefore propose to tackle the problem at a lower level by implementing variant views at the filesystem level. By mounting one or more variants using our Leviathan filesystem, we enable the use of standard tools such as syntax validators, code metric analysis tools, or arbitrary editors to view or modify a variant. The major benefit (and challenge) is the support for automatically writing back to the configurable code base when editing one of the mounted variant views. © 2010 ACM.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.IMMD4.toolch
Keywords: Leviathan; Software Product Lines; Variability Implementation; Preprocessor-Based Configuration; Toolchain-Independent Variability Support; Filesystem Views; Käsebrot; VAMOS; CiAO

Topic 18: Embedded Parallel Systems - Teich, Jürgen; Kaxiras, Stefanos; Plaks, Toomas; Flautner, Krisztián (Proceedings of the 12th International Euro-Par Conference, 2006)
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.topic1

Topology-aware replica placement in fault-tolerant embedded networks - Streichert, Thilo; Glaß, Michael; Wanka, Rolf; Haubelt, Christian; Teich, Jürgen (Proc. 21st International Conference on Architecture of Computing Systems (ARCS), 2008)
Application details uncertain at design time as well as tolerance against permanent resource defects demand flexibility and redundancy. In this context, we present a strategy for placing replicas in embedded point-to-point networks where link as well as node defects may occur at runtime. The proposed strategies for replica placement are based on the partitioning of the network into biconnected components. We are able to distinguish between different replication strategies, i.e., active and passive replication. Our experimental results show that the reliability improvement due to the proposed replica placement strategies is up to 23% compared to a randomized strategy. © 2008 Springer-Verlag Berlin Heidelberg.

To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations - Plagwitz, Patrick; Hannig, Frank; Teich, Jürgen; Keszöcze, Oliver (2023)
Convolutional Neural Networks (CNNs) are widely employed to solve various problems, e.g., image classification. Due to their compute- and data-intensive nature, CNN accelerators have been developed as ASICs or on FPGAs. Increasing complexity of applications has caused resource costs and energy requirements of these accelerators to grow. Spiking Neural Networks (SNNs) are an emerging alternative to CNN implementations, promising higher resource and energy efficiency. The main research question addressed in this paper is whether SNN accelerators truly meet these expectations of reduced energy requirements compared to their CNN equivalents. For this purpose, we analyze multiple SNN hardware accelerators for FPGAs regarding performance and energy efficiency. We present a novel encoding scheme of spike event queues and a novel memory organization technique to improve SNN energy efficiency further. Both techniques have been integrated into a state-of-the-art SNN architecture and evaluated for MNIST, SVHN, and CIFAR-10 datasets and corresponding network architectures on two differently sized modern FPGA platforms. For small-scale benchmarks such as MNIST, SNN designs provide rather no or little latency and energy efficiency advantages over corresponding CNN implementations. For more complex benchmarks such as SVHN and CIFAR-10, the trend reverses

Towards a Better Understanding of the Local Attractor in Particle Swarm Optimization: Speed and Solution Quality - Lange, Vanessa; Schmitt, Manuel; Wanka, Rolf (Proc. International Conference on Adaptive and Intelligent Systems (ICAIS), 2014)
Particle Swarm Optimization (PSO) is a popular nature-inspired meta-heuristic for solving continuous optimization problems. Although this technique is widely used, the understanding of the mechanisms that make swarms so successful is still limited. We present the first substantial experimental investigation of the influence of the local attractor on the quality of exploration and exploitation. We compare in detail classical PSO with the social-only variant where local attractors are ignored. To measure the exploration capabilities, we determine how frequently both variants return results in the neighborhood of the global optimum. We measure the quality of exploitation by considering only function values from runs that reached a search point sufficiently close to the global optimum and then comparing in how many digits such values still deviate from the global minimum value. It turns out that the local attractor significantly improves the exploration, but sometimes reduces the quality of the exploitation. The effects mentioned can also be observed by measuring the potential of the swarm. © 2014 Springer International Publishing Switzerland.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.infalg._towar

Towards Actor-oriented Programming on PGAS-based Multicore Architectures - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Proc. of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), 2014)
UnivIS-Import:2015-04-17:Pub.2014.tech.IMMD.inform.toward_7

Towards a multisensor station for automated biodiversity monitoring - Wägele, J. Wolfgang; Bodesheim, Paul; Bourlat, Sarah J.; Denzler, Joachim; Diepenbroek, Michael; Fonseca, Vera; Frommolt, Karl Heinz; Geiger, Matthias F.; Gemeinholzer, Birgit; Glöckner, Frank Oliver; Haucke, Timm; Kirse, Ameli; et al. (Basic and Applied Ecology, 2022)
Rapid changes of the biosphere observed in recent years are caused by both small and large scale drivers, like shifts in temperature, transformations in land-use, or changes in the energy budget of systems. While the latter processes are easily quantifiable, documentation of the loss of biodiversity and community structure is more difficult. Changes in organismal abundance and diversity are barely documented. Censuses of species are usually fragmentary and inferred by often spatially, temporally and ecologically unsatisfactory simple species lists for individual study sites. Thus, detrimental global processes and their drivers often remain unrevealed. A major impediment to monitoring species diversity is the lack of human taxonomic expertise that is implicitly required for large-scale and fine-grained assessments. Another is the large amount of personnel and associated costs needed to cover large scales, or the inaccessibility of remote but nonetheless affected areas. To overcome these limitations we propose a network of Automated Multisensor stations for Monitoring of species Diversity (AMMODs) to pave the way for a new generation of biodiversity assessment centers. This network combines cutting-edge technologies with biodiversity informatics and expert systems that conserve expert knowledge. Each AMMOD station combines autonomous samplers for insects, pollen and spores, audio recorders for vocalizing animals, sensors for volatile organic compounds emitted by plants (pVOCs) and camera traps for mammals and small invertebrates. AMMODs are largely self-containing and have the ability to pre-process data (e.g. for noise filtering) prior to transmission to receiver stations for storage, integration and analyses. Installation on sites that are difficult to access require a sophisticated and challenging system design with optimum balance between power requirements, bandwidth for data transmission, required service, and operation under all environmental conditions for years. An important prerequisite for automated species identification are databases of DNA barcodes, animal sounds, for pVOCs, and images used as training data for automated species identification. AMMOD stations thus become a key component to advance the field of biodiversity monitoring for research and policy by delivering biodiversity data at an unprecedented spatial and temporal resolution.
CRIS-Team Scopus Importer:2022-02-11
Keywords: AMMOD; Artificial intelligence; Bioacoustic monitoring; Biodiversity monitoring; Computer science; Computer vision; Metabarcoding; Pattern recognition; Visual monitoring; Volatile organic compounds

Towards an Autonomous, Power-Efficient Base Station for Sensor Data Collection - Sixdenier, Pierre-Louis André Edouard (2nd IEEE International Conference on Autonomic Computing and Self-Organizing Systems Companion, ACSOS-C 2021, 2021)
Keywords: Autonomous-system; Data-transmission; Data-compression; Power-management; Iot

Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language - Membarth, Richard; Reiche, Oliver; Schmitt, Christian; Hannig, Frank; Teich, Jürgen; Stürmer, Markus; Köstler, Harald (Journal of Parallel and Distributed Computing, 2014)
High Performance Computing (HPC) systems are nowadays more and more heterogeneous. Different processor types can be found on a single node including accelerators such as Graphics Processing Units (GPUs). To cope with the challenge of programming such complex systems, this work presents a domain-specific approach to automatically generate code tailored to different processor types. Low-level CUDA and OpenCL code is generated from a high-level description of an algorithm specified in a Domain-Specific Language (DSL) instead of writing hand-tuned code for GPU accelerators. The DSL is part of the Heterogeneous Image Processing Acceleration (HIPAcc) framework and was extended in this work to handle grid hierarchies in order to model different cycle types. Language constructs are introduced to process and represent data at different resolutions. This allows to describe image processing algorithms that work on image pyramids as well as multigrid methods in the stencil domain. By decoupling the algorithm from its schedule, the proposed approach allows to generate efficient stencil code implementations. Our results show that similar performance compared to hand-tuned codes can be achieve
UnivIS-Import:2015-03-11:Pub.2014.tech.IMMD.inform.toward_67
Keywords: Multigrid; Multiresolution; Image pyramid; Domain-specific language; Stencil codes; Code generation; GPU; CUDA; OpenCL

Towards Clause Learning a la Carte through VarMonads - Friedemann, Arved; Keszöcze, Oliver (International Symposium on Logic-based Program Synthesis and Transformation, 2022)

Towards Domain-specific Computing for Stencil Codes in HPC - Membarth, Richard; Hannig, Frank; Teich, Jürgen; Köstler, Harald (Proceedings of the 2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), 2012)
High Performance Computing (HPC) systems are nowadays more and more heterogeneous. Different processor types can be found on a single node including accelerators such as Graphics Processing Units (GPUs). To cope with the challenge of programming such complex systems, this work presents a domain-specific approach to automatically generate code tailored to different processor types. Low-level CUDA and OpenCL is generated from a high-level description of a geometric multigrid algorithm written in a Domain-Specific Language (DSL) instead of writing hand-tuned code for GPU accelerators. By decoupling the algorithm from its schedule, the proposed approach allows to generate efficient stencil codes. Our results show that competitive performance compared to hand-tuned codes can be achieved and that more than 25 frames per second for 16.8 Megapixel images are obtained for full High Dynamic Range (HDR) compression of 2D medical data sets. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.toward
Keywords: code generation; CUDA; domain-specific language; GPU; OpenCL; stencil codes

Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor - Kouveli, Georgia; Hannig, Frank; Lupp, Jan-Hugo; Teich, Jürgen (Proceedings of the 3rd MARC Symposium, 2011)
In this paper, we apply a new programming paradigm called resource-aware programming to the Single-Chip Cloud Computer. According to this paradigm, an application may change at certain points of execution its allocation of resources. This gives application engineers the opportunity to dynamically adapt an algorithm's behavior and parallelism to the work load and state of the underlying resources (e. g., availability, clock frequency, temperature). Resource-aware programming can provide a selforganizing behavior to conventional programs for being able to not only tolerate certain types of faults and cope with feature variations, but also to provide scalability, higher resource utilization, as well as performance and power gains by managing voltage/frequency islands and adjusting the amount of allocated resources to the temporal needs of a running application. We discuss the details of resource-aware programming as well as three alternative implementation concepts that we intend to evaluate. Finally, we present the results of initial experiments, we conducted using a centralized resource management framework on the Single- Chip Cloud Computer.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.toward_0

Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded System Design and Optimization - Graf, Sebastian; Reimann, Felix; Glaß, Michael; Teich, Jürgen (Proc. of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2014)
Symbolic encoding for resource allocation, task binding, and message routing during multi-objective design space exploration (DSE) has gained significant attention in recent years. To determine the message routing, existing symbolic approaches typically rely on an explicit encoding of routing hops which results in a huge number of required variables and/or constraints. As a result, these approaches fail in case of large network diameters and/or a huge number of messages or resources and even for smaller problems, the convergence of the involved optimization process suffers. To tackle this shortcomings, this work proposes three novel symbolic routing encoding strategies that all avoid to encode hops explicitly, but are based on an encoding of individual links or complete sender-receiver paths, but still cover the same design space. The result is a more compact problem representation with less constraints and, in particular, less variables; the latter eliminates ineffective degrees of freedom from the search space and significantly enhances the optimization quality of a multi-objective optimization with even non-linear objectives. In an extensive test-suite, three major classes of wired networked embedded systems are considered: (a) hierarchical stars as in MPSoCs or automotive, (b) redundant backbone buses as common in rail systems or avionics, and (c) mesh-based architectures that often occur in NoC-based MPSoCs. For all three classes, the proposed approaches significantly outperform existing techniques in both scalability and optimization quality and, thus, considerably enlarge the field of application of a multi-objective DSE for the networked embedded system design. Copyright is held by the owner/author(s).
UnivIS-Import:2015-04-17:Pub.2014.tech.IMMD.inform.toward_5

Towards scalable system-level reliability analysis - Glaß, Michael; Lukasiewycz, Martin; Haubelt, Christian; Teich, Jürgen (47th Design Automation Conference, DAC '10, 2010)
State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: (1) The BDDs exhaust available memory during their construction and/or (2) the final size of the BDDs is, sometimes up to several orders of magnitude, larger than the available memory. The contribution of this paper is twofold: (1) A partitioning-based early quantification technique is presented that aims to keep the size of the BDDs during construction at minimum. (2) A SAT-assisted simulation approach aims to deliver approximated results when exact analysis techniques fail because the final BDDs exhaust available memory. The ability of both methods to accurately analyze larger and more complex systems than known approaches is demonstrated for various test cases. Copyright 2010 ACM.
Keywords: Early quantification; Reliability analysis; SAT-assisted simulation

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays - Boppu, Srinivas; Hannig, Frank; Teich, Jürgen; Pérez-Andrade, Roberto (Proc. of ReConFig, 2011)
Invasive computing is a novel computing paradigm, which allows us to allocate several resources at run-time. Tightly-coupled processor arrays are well suited for invasive computing. This paper proposes a methodology, to symbolically program a claimed array of computational resources. Using this methodology, a single configuration stream can be derived, which is sufficient to configure all the claimed resources (processing elements) irrespective of the number of resources claimed. The configuration stream is modified at run-time dynamically, depending on the number of processors claimed. Configuration memory requirements were estimated for our methodology. It requires constant memory size and is independent of the problem size compared to a traditional approach. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.toward
Keywords: coarse grained architectures; dynamic reconfiguration

Towards the co-evolution of industrial products and its production systems by combining models from development and hardware/software deployment in cyber-physical systems - Vogel-Heuser, Birgit; Wildermann, Stefan; Teich, Jürgen (Production Engineering, 2017)

Towards the Co-Evolution of Industrial Products and its Production Systems by Combining Models from Development and Hardware/Software Deployment in Cyber-Physical Systems - Vogel-Heuser, Birgit; Wildermann, Stefan; Teich, Jürgen (Production Engineering, 2017)

Towards Virtual Hardware Prototyping for Generated Geometric Multigrid Solvers - Kuckuk, Sebastian; Leitenmaier, Lena; Schmitt, Christian; Schönwetter, Dominik; Köstler, Harald; Fey, Dietmar (2017)
Many applications in scientific computing require solving one or more partial differential equations (PDEs). For this task, solvers from the class of multigrid methods are known to be amongst the most efficient. An optimal implementation, however, is highly dependent on the specific problem as well as the target hardware. As energy efficiency is a big topic in today's computing centers, energy-efficient platforms such as ARM-based clusters are actively researched. In this work, we present a domain-specific approach, starting with the problem formulation in a domain-specific language (DSL), down to code generation targeting a variety of systems including embedded architectures. Furthermore, we present an approach to simulate embedded architectures to achieve an optimal hardware/software co-design, i.e., an optimal composition of software and hardware modifications. In this context, we use a virtual environment (OVP) that enables the adaptation of multicore models and their simulation in an efficient way. Our approach shows that execution time prediction for ARM-based platforms is possible and feasible but has to be enhanced with more detailed cache and memory models. We substantiate our claims by providing results for the performance prediction of geometric multigrid solvers generated by the ExaStencils framewor
Keywords: ARM; code generation; domain-specific language; multigrid; open virtual platforms

TRAC: Compilation-based Design of Transformer Accelerators for FPGAs - Plagwitz, Patrick; Hannig, Frank; Teich, Jürgen (IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications, 2022)

Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter - Bednara, Marcus; Beyer, O.; Teich, Jürgen; Wanka, Rolf (Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors, pp. 299-308, Boston, MA, U.S.A. IEEE Computer Society Press, July 2000Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors, 2000)
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the low performance, while realizing multiprocessor sorting methods on parallel computers is much too expensive with respect to power consumption, physical weight, and cost. We investigate cost/performance tradeoffs for hybrid sorting algorithms that use a mixture of sequential merge sort and systolic insertion sort techniques. We propose a scalable architecture for integer sorting that consists of a uniprocessor and an FPGA-based parallel systolic co-processor. Speedups obtained analytically and experimentally and depending on hardware (cost) constraints are determined as a function of time constants of the uniprocessor and the co-processor.
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.tradeo

Tradeoff Analysis of FPGA Based Elliptic Curve Cryptography - Bednara, Marcus; Daldrup, M.; J. Shokrollahi, J.; Teich, Jürgen; von zur Gathen, J. (Proc. of IEEE International Symposium on Circuits and Systems, 2002)
FPGAs are an attractive platform for elliptic curve cryptography hardware. Since field multiplication is the most critical operation in elliptic curve cryptography, we have studied how efficient several field multipliers can be mapped to lookup table based FPGAs. Furthermore we have compared different curve coordinate representations with respect to the number of required field operations, and show how an elliptic curve coprocessor based on the Montgomery algorithm for curve multiplication can be implemented using our generic coprocessor architecture.
UnivIS-Import:2015-04-16:Pub.2002.tech.IMMD.inform.tradeo

Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures - Boppu, Srinivas; Lari, Vahid; Hannig, Frank; Teich, Jürgen (Proc. Synopsys Users Group Conference, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.transa

Trends in Data Locality Abstractions for HPC Systems - Unat, Didem; Dubey, Anshu; Hoefler, Torsten; Shalf, John; Abraham, Mark; Bianco, Mauro; Chamberlain, Bradford L.; Cledat, Romain; Edwards, H. Carter; Finkel, Hal; Fürlinger, Karl; Hannig, Frank; et al. (IEEE Transactions on Parallel and Distributed Systems, 2017)
The cost of data movement has always been an important concern in high performance computing (HPC) systems. It has now become the dominant factor in terms of both energy consumption and performance. Support for expression of data locality has been explored in the past, but those efforts have had only modest success in being adopted in HPC applications for various reasons. However, with the increasing complexity of the memory hierarchy and higher parallelism in emerging HPC systems, locality management has acquired a new urgency. Developers can no longer limit themselves to low-level solutions and ignore the potential for productivity and performance portability obtained by using locality abstractions. Fortunately, the trend emerging in recent literature on the topic alleviates many of the concerns that got in the way of their adoption by application developers. Data locality abstractions are available in the forms of libraries, data structures, languages and runtime systems; a common theme is increasing productivity without sacrificing performance. This paper examines these trends and identifies commonalities that can combine various locality concepts to develop a comprehensive approach to expressing and managing data locality on future large-scale high-performance computing system

Uncertainty-Aware Compositional System-Level Reliability Analysis - Aliee, Hananeh; Glaß, Michael; Khosravi, Faramarz; Teich, Jürgen (Dependable Embedded Systems, 2020)

Uncertainty-aware reliability analysis and optimization - Khosravi, Faramarz; Müller, Malte; Glaß, Michael; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE 2015), 2015)
Due to manufacturing tolerances and aging effects, future embedded systems have to cope with unreliable components. The intensity of such effects depends on uncertain aspects like environmental or usage conditions such that highly safety-critical systems are pessimistically designed for worst-case mission profiles. In this work, we propose to explicitly model the uncertain characteristics of system components, i. e. we model components using reliability functions with parameters distributed between a best and worst case. Since destructive effects like temperature may affect several components simultaneously (e. g. those in the same package), a correlation between uncertainties of components exists. The proposed uncertainty-aware method combines a formal analysis approach and a Monte Carlo simulation to consider uncertain characteristics and their different correlations. It delivers a holistic view on the system's reliability with best/worst/average-case behavior and also insights on variance and quantiles. But, existing optimization approaches typically assume design objectives to be single values or to follow a predefined distribution. As a remedy, we propose a dominance criterion for meta-heuristic optimization approaches like evolutionary algorithms that enables the comparison of system implementations with arbitrarily distributed characteristics. Our presented experimental results show that (a) the proposed analysis comes at low overhead while capturing existing uncertainties with sufficient accuracy, and (b) the optimization process is significantly enhanced when guiding the search process by additional aspects like variance and the 95% quantile, delivering better system implementations as found by an uncertainty-oblivious optimization approach.

Uniform design of parallel programs for DSP - Teich, Jürgen; Thiele, Lothar (In Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 1991)

Unifying Partitioning and Placement for SAT-based Exploration of Heterogeneous Reconfigurable SoCs - Wildermann, Stefan; Ziener, Daniel; Teich, Jürgen (Proc. of the International Conference on Field Programmable Logic and Applications, 2011)
Heterogeneous reconfigurable SoCs provide more flexibility, maintainability, and re-usability than hardwired SoCs. Designing such systems is a complex task, since early decisions, as design partitioning, influence the subsequent design steps, such as placement of partially reconfigurable modules In this paper, we investigate a symbolic design space exploration (DSE) approach for this kind of SoCs, where we transform the problem of finding a feasible implementation to a Boolean satisfiability problem (SAT). We present three encoding variants which unify partitioning and placement to overcome the drawbacks of their separation. In particular, we will show that the runtime of DSE can be speeded up when we perform a preprocessing mechansim that identifies those partitionings which inevitably lead to infeasibility, and then incorporate this information into the symbolic encoding for calculating feasible placements. Our experiments show the effectiveness of our SAT-based approach and compare the presented encoding variants. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.unifyi

Unreliable Data Transmissions and Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes - Graf, Sebastian; Glaß, Michael; Teich, Jürgen (Tagungsunterlagen Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012)
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.unreli

Unveiling Kernel Concurrency in Multiresolution Filters on GPUs with an Image Processing DSL - Qiao, Bo; Reiche, Oliver; Teich, Jürgen; Hannig, Frank (Proceedings of the 13th Workshop on General Purpose Processing Using GPU (GPGPU), 2020)
Multiresolution filters, analyzing information at different scales, are crucial for many applications in digital image processing. The different space and time complexity at distinct scales in the unique pyramidal structure poses a challenge as well as an opportunity to implementations on modern accelerators such as GPUs with an increasing number of compute units. In this paper, we exploit the potential of concurrent kernel execution in multiresolution filters. As a major contribution, we present a model-based approach for performance analysis of as well single- as multi-stream implementations, combining both application- and architecture-specific knowledge. As a second contribution, the involved transformations and code generators using CUDA streams on Nvidia GPUs have been integrated into a compiler-based approach using an image processing DSL called Hipacc. We then apply our approach to evaluate and compare the achieved performance for four real-world applications on three GPUs. The results show that our method can achieve a geometric mean speedup of up to 2.5 over the original Hipacc implementation without our approach, up to 2.0 over the other state-of-the-art DSL Halide, and up to 1.3 over the recently released programming model CUDA Graph from Nvidia.<br
Keywords: Multiresolution Filter; Image Pyramid; Concurrent Kernel; CUDA Streams; GPUs

Using Deep Learning to Demodulate Transmissions in Molecular Communication - Bartunik, Max; Keszöcze, Oliver; Schiller, Benjamin; Kirchner, Jens (2022 IEEE 16th International Symposium on Medical Information and Communication Technology (ISMICT), 2022)

Using Design Space Exploration for Finding Schedules with Guaranteed Reaction Times of Synchronous Programs on Multi-core Architecture - Li, Zhenmin; Park, Heejong; Malik, Avinash; Wang, Kevin I-Kai; Salcic, Zoran; Kuzmin, Boris; Glaß, Michael; Teich, Jürgen (Journal of Systems Architecture, 2017)

Using hashing and lexicographic order for Frequent Itemsets Mining on data streams - Bustio, Lazaro; Letras, Martin; Cumplido, René; Hernández-León, Raudel; Feregrino, Claudia; Bande, Jose M. (Journal of Parallel and Distributed Computing, 2019)
Frequent Itemsets Mining is a Data Mining technique that has been employed to extract useful knowledge from datasets and, more recently, also from data streams. Data streams are unbounded and infinite flows of data arriving at high rates which cannot be stored for off-line processing; therefore, proposed algorithms for Frequent Itemsets Mining approaches from datasets cannot be used straightforwardly for Frequent Itemsets Mining from data streams. Frequent Itemsets Mining is a compute intensive task, hence developing custom hardware-based architectures to speed up this process is an active research topic. This paper introduces an algorithm for a hardware-based Frequent Itemsets Mining on data streams that uses the top- frequent 1-itemsets detection as preprocessing. The received transactions are handled using hash functions, and the lexicographic order of items is used for obtaining frequent itemsets. The proposed algorithm is focused on discovering frequent itemsets in data streams composed of short transactions in large alphabets. Experimental results demonstrate that the proposed algorithm outperforms the processing time of the state-of-the-art algorithms used as the baseline.<br
Keywords: Frequent Itemsets Mining; Data streams; Reconfigurable hardware; Hashing Lexicographic order

Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems - Smirnov, Fedor; Pourmohseni, Behnaz; Teich, Jürgen (PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020), 2020)
CRIS-Team WoS Importer:2021-02-26

Using Learning Classifier Systems for the DSE of Dynamically Adaptable Embedded Systems - Smirnov, Fedor; Pourmohseni, Behnaz; Teich, Jürgen (Design, Automation and Test in Europe Conference, 2020)
Modern embedded systems are not only becoming more and more complex but are also often exposed to dynamically changing run-time conditions such as resource availability or processing power requirements. This increasing dynamism of embedded systems has led to the emergence of novel design approaches that combine a static off-line Design Space Exploration (DSE) with the consideration of the dynamic run-time behavior of the system under design. In contrast to a purely static design approach, which statically designs a single design solution which compromises between the possible run-time situations, the off-line DSE of these so-called hybrid approaches provides a set of configuration alternatives, so that at run time, it becomes possible to dynamically choose the option most suited for the current situation. However, most of these approaches still use optimizers which were primarily developed for static design. Consequently, the modeling of complex dynamic environments or run-time requirements is either not possible or comes at the cost of significant computation overheads or results of lower quality. As a remedy, this paper introduces Learning Optimizer Constrained by ALtering conditions (LOCAL), a novel optimization framework for the optimization of dynamically adaptable embedded systems. Following the structure of Learning Classifier System (LCS) optimizers, the proposed framework optimizes a strategy, i.e., a set of conditionally applicable solutions for the problem at hand, instead of a set of independent solutions. The framework enables the designer to model complex environmental behavior, making this problem-specific knowledge accessible to the optimizer. We show how the proposed framework—which can be used for the optimization of any dynamic system—is used for the optimization of dynamically reconfigurable many-core systems and provide experimental evidence that the hereby obtained strategy offers superior embeddability compared to the solutions provided by a s.o.t.a. hybrid approach which uses an evolutionary algorithm.<br
Keywords: DSE; Adaptable Systems; Learning Classifiers

Using symbolic feasibility tests during design space exploration of heterogeneous multi-processor systems - Schlichter, Thomas; Hannig, Frank; Haubelt, Christian; Teich, Jürgen (Proceedings of Application-specific Systems, Architectures and Processors (ASAP), 2005)
The task of automatic design space exploration of heterogeneous multi-processor systems is often tackled with Evolutionary Algorithms. In this paper, we propose a novel approach in combining Evolutionary Algorithms with symbolic techniques in order to improve the convergence speed. The main idea is to guide the search towards the feasible region by utilizing symbolic techniques. We will present experimental results showing the advantages of our novel approach, especially when the search space contains only few feasible solutions, what is often the case when designing heterogeneous multi-processor systems. © 2005 IEEE.

Using the Power Side Channel of FPGAs for Communication - Ziener, Daniel; Baueregger, Florian; Teich, Jürgen (Proc. 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, 2010)
In this paper, we present a novel technique for transmitting data over the power supply pins of an FPGA. Using this power side channel communication, a core inside the FPGA is able to send data to a receiver outside of the FPGA. Possible applications include monitoring, debugging, and watermarking. For the communication, we do not need any further resources, like IO pins or modifications of the board. We characterize the communication channel over the power pins and build a channel model. Furthermore, we present an encoding/decoding method which is independent of the board type and FPGA combination. With this approach, we achieve data rates up to 500 kbit/s. Finally, we provide a case study, which extends existing power watermarking techniques to the new encoding/decoding method and show experimental decoding results. © 2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.usingt

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism - Schaffer, Rainer; Merker, Renate; Hannig, Frank; Teich, Jürgen (Proceedings of the 11th Euromicro Conference on Digital System Design, 2008)
In this paper a systematic mapping method for a specific algorithm class is given which exploits all levels of parallelism of the target architecture. This target architecture is a processor array where each processing element can have several functional units. This functional units allow subword parallelism, that means multiple equal operations with low data word width can be executed in parallel in the data path of the functional units. The mapping method is illustrated on the edge detection algorithm, and achieves up to 99% of the theoretical speed-up. © 2008 IEEE.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.utiliz

Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks - Sabih, Muhammad; Hannig, Frank; Teich, Jürgen (2020)
For many applications, utilizing Deep Neural Networks (DNNs) requires their implementation on a target architecture in an optimized manner concerning energy consumption, memory requirement, throughput, etc. DNN compression is used to reduce the memory footprint and complexity of a DNN before its deployment on hardware. Recent efforts to understand and explain AI (Artificial Intelligence)methods have led to a new research area, termed as explainable AI. Explainable AI methods allow us to better understand the inner working of DNNs, such as the importance of different neurons and features. The concepts from explainable AI provide an opportunity to improve DNN compression methods such as quantization and pruning in several ways that have not been sufficiently explored so far. In this paper, we utilize explainable AI methods: mainly DeepLIFT method. We use DeepLIFT for (1) pruning of DNNs; this includes structured and unstructured pruning of Convolutional Neural Network (CNN) filters pruning as well as pruning weights of fully connected layers, (2) non-uniform quantization of DNN weights using clustering algorithm; this is also referred to as Weight Sharing, and (3)integer-based mixed-precision quantization; this is where each layer of a DNN may use a different number of integer bits. We use typical image classification datasets with common deep learning image classification models for evaluation. In all these three cases, we demonstrate significant improvements as well as new insights and opportunities from the use of explainable AI in DNN compressio

Validation and Demonstrator - Becker, Jürgen; Hannig, Frank; Wild, Thomas; Brand, Marcel; Lenke, Oliver; Lesniak, Fabian (Invasive Computing, 2022)

Variety-Aware Routing Encoding for Efficient Design Space Exploration of Automotive Communication Networks - Smirnov, Fedor; Pourmohseni, Behnaz; Glaß, Michael; Teich, Jürgen (5th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS), 2019)
The introduction of sophisticated ADAS has given rise to larger and more complex automotive communication networks whose efficient (in effort) and optimal (in quality) design necessarily depends on automated network design techniques. Typically, these techniques either (a) optimize communication routes based on topology-independent constraint systems that encode the inclusion of each network component in the route of a message or (b) depend on a time- and memory-expensive enumeration of all possible transmission routes to identify the optimal route. In this paper, we propose a novel approach which combines the advantages of these two strategies to enable an efficient exploration of the routing search space: First, the given network is preprocessed to identify so-called proxy areas in which each pair of nodes can be connected by exactly one route. Contrary to network areas with a variety of different routing possibilities, proxy areas do not offer any room for optimization. We propose two approaches—both integrable into existing constraint systems—which exploit the knowledge gathered on proxy areas to improve the exploration efficiency during the routing optimization process. Experimental results for two mainstream topologies of automotive networks give evidence that, compared to state-of-the-art routing optimization approaches, the proposed approaches (a) offer an exploration speedup of up to 185, (b) deliver network designs of equal or higher quality, and (c) enable an automated design of significantly larger automotive systems.<br
Keywords: Design Space Exploration; Network Optimization; Automotive Networks

Velocity Adaptation in Particle Swarm Optimization - Helwig, Sabine; Neumann, Frank; Wanka, Rolf (Handbook of Swarm Intelligence, 2011)
Swarm Intelligence methods have been shown to produce good results in various problem domains. A well-known method belonging to this kind of algorithms is particle swarm optimization (PSO). In this chapter, we examine how adaptation mechanisms can be used in PSO algorithms to better deal with continuous optimization problems. In case of bound-constrained optimization problems, one has to cope with the situation that particles may leave the feasible search space. To deal with such situations, different bound handling methods were proposed in the literature, and it was observed that the success of PSO algorithms highly depends on the chosen bound handling method. We consider how velocity adaptation mechanisms can be used to cope with bounded search spaces. Using this approach we show that the bound handling method becomes less important for PSO algorithms and that using velocity adaptation leads to better results for a wide range of benchmark functions.
UnivIS-Import:2015-04-20:Pub.2011.tech.IMMD.infalg._veloc

Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques (Keynote) - Teich, Jürgen; Ziener, Daniel (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2011)
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.verify

Verteilte HW/SW-Partitionierung für fehlertolerante rekonfigurierbare Netzwerke - Streichert, Thilo; Haubelt, Christian; Teich, Jürgen (Proceedings of 17. ITG/GI/GMM Workshop für Testmethoden und Zuverlässigkeit und Fehlertoleranz von Schaltungen und Systemen, 2005)

Virtual Area Management: Multitasking on Dynamically Partially Reconfigurable Devices - Angermeier, Josef; Teich, Jürgen; Kamphans, Tom; Fekete, Sandor P. (Proc. 17th Reconfigurable Architectures Workshop, 2010)
Every year the computing resources available on dynamically partially reconfigurable devices increase enormously. In the near future, we expect many applications to run on a single reconfigurable device. In this paper, we present a concept for multitasking on dynamically partially reconfigurable systems called virtual area management. We explain its advantages, show its challenges, and discuss possible solutions. Furthermore, we investigate one problem in more detail: Packing modules with time-varying resource requests. This problem from the reconfigurable computing field results in a completely new optimization problem not tackled before. ILP-based and heuristic approaches are compared in an experimental study and the drawbacks and benefits discussed. © 2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.virtua

Virtual Networks - Distributed Communication Resource Management - Heisswolf, Jan; Zaib, Aurang; Weichslgartner, Andreas; König, Ralf; Wild, Thomas; Teich, Jürgen; Herkersdorf, Andreas; Becker, Jürgen (ACM Transactions on Reconfigurable Technology and Systems, 2013)
Networks-on-Chip (NoC) enable scalability for future manycore architectures, facilitating parallel communication between multiple cores. Applications running in parallel on a NoC-based architecture can affect each other due to overlapping communication. Quality-of-Service (QoS) must be supported by the communication infrastructure to execute communication-, real-time- and safety-critical applications on such an architecture. Different strategies have been proposed to provide QoS for point-to-point connections. These strategies allow each node to set up a limited number of connections to other nodes. In this work Virtual Networks (VN) are proposed to enable QoS for regions of a NoC-based architecture. Virtual Networks overcome the limitation of point-to-point connections. A VN behaves like an exclusive physical network. Virtual Networks can be defined and configured during runtime. The size of the VN region and the assigned bandwidth can be adjusted depending on the application requirements. Virtual Networks enable the decoupling of local from global communication. Therefore, the communication of the application mapped into the region is assigned to a Virtual Network established in that specific region. This concept targets packet-switched networks with virtual channels and is realized by an intelligent hardware unit that manages the virtual channel reservation process at system runtime. Virtual Networks can be established and administrated independent of each other, enabling distributed communication resource management. The proposed concept is implemented as a cycle-accurate SystemC simulation model. The simulation results of executing communicating graphs obtained from real application highlight the usefulness of Virtual Networks by showing improved throughput and reduced delay in the respective scenarios. A hardware implementation demonstrates a low impact on area utilization and power consumption. © 2013 ACM.
UnivIS-Import:2015-03-09:Pub.2013.tech.IMMD.inform.virtua
Keywords: Hardware; Network-on-Chip; Quality-of-service; Region-based; Subnetworks; Virtual network

Virtual prototyping for efficient multi-core ECU development of driver assistance systems - Kiesel, Rainer; Streubühr, Martin; Haubelt, Christian; Terzis, Anestis; Teich, Jürgen (Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XII), 2012)
In recent years, road vehicles have experienced an enormous increase in driver assistance systems such as traffic sign recognition, lane departure warning, and pedestrian detection. Cost-efficient development of electronic control units (ECUs) for these systems is a complex challenge. The demand for shortened time to market makes the development even more challenging and thus demands efficient design flows. This paper proposes a model-based design flow that permits simulation-based performance evaluation of multi-core ECUs for driver assistance systems in a pre-development stage. The approach is based on a system-level virtual prototype of a multi-core ECU and allows the evaluation of timing effects by mapping application tasks to different platforms. The results show that performance estimation of different parallel implementation candidates is possible with high accuracy even in a pre-development stage. By adapting the best-fitting parallelization strategy to the final ECU, a reduction in the time to market period is possible. Currently, the design flow is being evaluated by Daimler AG and is being applied to a pedestrian detection system. Results from this application illustrate the benefits of the proposed approach. © 2012 IEEE.

Vision-Based Path Construction and Maintenance for Indoor Guidance of Autonomous Ground Vehicles Based on Collaborative Smart Cameras - Streit, Franz-Josef; Pantho, Md Jubaer Hossain; Bobda, Christophe; Roullet, Cindy (ACM Proceedings of the 10th International Conference on Distributed Smart Cameras, 2016)

White Paper: Programming Abstractions for Data Locality - Tate, Adrian; Kamil, Amir; Dubey, Anshu; Größlinger, Armin; Chamberlain, Brad; Goglin, Brice; Edwards, Carter H.; Newburn, Chris; Padua, David; Unat, Didem; Jeannot, Emmanuel; Hannig, Frank; et al. (Proc. of PADAL Workshop, 2014)
UnivIS-Import:2015-04-17:Pub.2014.tech.IMMD.inform.whitep

Windowed Synchronous Data Flow - Keinert, Joachim; Haubelt, Christian; Teich, Jürgen (2005)

Assertion-Based Verification of Transaction Level Models - Niemann, Bernardt; Haubelt, Christian (Proceedings of the 9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2006)

Automatic Model-Based Design Space Exploration for Embedded Systems - A System Level Approach - Haubelt, Christian (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2005)

Design Space Exploration for Distributed Hardware Reconfigurable Systems - Haubelt, Christian (Field-Programmable Logic and Applications, 2004)

Formalizing TLM with Communicating State Machines - Niemann, Bernardt; Haubelt, Christian (Proceedings Forum on Specification and Design Languages (FDL'06), 2006)

Invasive Tightly Coupled Processor Arrays - Lari, Vahid (Springer book series on Computer Architecture and Design Methodologies, 2016)

RITK: The Range Imaging Toolkit - A Framework for 3-D Range Image Stream Processing - Wasza, Jakob; Bauer, Sebastian; Haase, Sven; Schmid, M.; Reichert, S.; Hornegger, Joachim (VMV 2011: Vision, Modeling & Visualization, 2011)