Bridging Algorithm and ESL Design: Matlab/Simulink Model Transformation and Validation - Zhang, Liyuan; Glaß, Michael; Ballmann, Nils; Teich, Jürgen (Proc. Forum on Specification & Design Languages, 2013)
Matlab/Simulink is today's de-facto standard for model-based design in domains such as control engineering and signal processing. Particular strengths of Simulink are rapid design and algorithm exploration. Moreover, commercial tools are available to generate embedded C or HDL code directly from a Simulink model. On the other hand, Simulink models are purely functional models and, hence, designers cannot seamlessly consider the architecture that a Simulink model is later implemented on. In particular, it is not possible to explore the different architectural alternatives and investigate the arising interactions and side-effects directly within Simulink. To benefit from Matlab/Simulink's algorithm exploration capabilities and overcome the outlined drawbacks, this work introduces a model transformation framework that converts a Simulink model to an executable specification, written in an actor-oriented modeling language. This specification then serves as the input of well-established Electronic System Level (ESL) design flows that, e. g., enables Design Space Exploration (DSE) and automatic code generation for both hardware and software. We also present a validation technique that considers the functional correctness by comparing the original Simulink model with the generated specification in a co-simulation environment. The co-simulation can also be used to evaluate the performance of implementation candidates during DSE. As case study, we present and investigate a torque vectoring application from an electric automotive vehicle. © 2013 European Electronic Chips & Systems design Initiative - ECSI.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.bridgi
Keywords: Actor-oriented Design; Code Generation; DSE; Matlab/Simulink; System-level Validation; SystemC

Bridging Algorithm and ESL Design: MATLAB/Simulink Model Transformation and Validation - Zhang, Liyuan; Glaß, Michael; Ballmann, Nils; Teich, Jürgen (Languages, Design Methods, and Tools for Electronic System Design, 2015)

Bridging the Gap between Relocation and Available Technology: The Erlangen Slot Machine - Göhringer, Diana; Majer, Mateusz; Teich, Jürgen (Proceedings of the Dagstuhl Seminar Nº 06141 on Dynamically Reconfigurable Architectures, 2006)
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.bridgi

Buffer Memory Optimization in DSP Applications - An Evolutionary Approach - Bhattacharyya, Shuvra S.; Teich, Jürgen; Zitzler, Eckart (Parallel Problem Solving from Nature (PPSN'98), 1998)
In the context of digital signal processing, synchronous data flow (SDF) graphs [12] are widely used for specification. For these, so called single appearance schedules provide program memory-optimal uniprocessor implementations. Here, buffer memory minimized schedules are explored among these using an Evolutionary Algorithm (EA). Whereas for a restricted class of graphs, there exist optimal polynomial algorithms, these are not exact and may provide poor results when applied to arbitrary, i.e., randomly generated graphs. We show that a careful EA implementation may outperform these algorithms by sometimes orders of magnitude.
UnivIS-Import:2015-04-20:Pub.1998.tech.IMMD.inform.buffer

Buffer Memory Optimization in DSP Applications - An Evolutionary Approach - Bhattacharyya, Shuvra; Teich, Jürgen; Zitzler, Eckart (Springer Lecture Notes in Computer Science (LNCS) 1498, 1998)

Buildabong: A framework for architecture/compiler co-exploration for ASIPs - Fischer, Dirk; Teich, Jürgen; Thies, M.; Weper, R. (Journal of Circuits Systems and Computers, 2003)
With the term Architecture/Compiler Co-exploration, we denote the problem of simultaneously optimizing an application-specific instruction set processor (ASIP) architecture as well as its generated compiler. In this paper, we characterize the design space of both compiler frontend (intermediate code optimization) and backend (changes of the machine model) and present the workflow of our framework BUILDABONG. The project consists of four phases: (a) architecture entry and composition, (b) automatic simulator generation, (c) compiler generation (in particular, retargeting), and (d) automatic architecture/compiler design space exploration. We demonstrate the feasibility of our approach by a detailed case study.
Keywords: Architecture/compiler co-design; ASIP; Multiobjective design space exploration; Retargetable compilation

BUILDABONG: A Rapid Prototyping Environment for ASIPs - Fischer, Dirk; Teich, Jürgen; Trinkert, Stefan; Weper, Ralph (Proc. DSP-Deutschland 2000, 2000)
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.builda

Calibration and validation of software performance models for pedestrian detection systems - Kiesel, Rainer; Streubühr, Martin; Haubelt, Christian; Löhlein, Otto; Teich, Jürgen (Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XI), 2011)
In recent years, road vehicles have seen a tremendous increase on driver assistance systems like lane departure warning, traffic sign recognition, or pedestrian detection. The development of efficient and cost-effective electronic control units that meet the necessary real-time performance for these systems is a complex challenge. Often, Electronic System-Level design tackles the challenge by simulation-based performance evaluation, although, the quality of system-level performance simulation approaches is not yet evaluated in detail. In this paper, we present the calibration and validation of a system-level performance simulation model. For evaluation, an automotive pedestrian detection algorithm is studied. Especially the varying number of pedestrians has a significant impact to the system performance and makes the prediction of execution time difficult. As test cases we used typical sequences and corner cases recorded by an experimental car. Our evaluation results indicate that prediction of execution times with an average error of 3.1% and a maximum error of 7.9% can be achieved. Thereby, simulated and measured execution times of a software implementation are compared. © 2011 IEEE.

CAN+: A New Backward-compatible Controller Area Network (CAN) Protocol with up to 16x Higher Data Rates - Ziermann, Tobias; Wildermann, Stefan; Teich, Jürgen (Proc. Design, Automation and Test in Europe, 2009)
As the number of electronic components in automobiles steadily increases, the demand for higher communication bandwidth also rises dramatically. Instead of installing new wiring harnesses and new bus structures, it would be useful, if already available structures could be used, but driven at higher data rates. In this paper, we a) propose an extension of the well-known Controller Area Network (CAN) called CAN+ with which the target rate of 1Mbit/s can be increased up to 16 times. Moreover, b) existing CAN hardware and devices not dedicated to these boosted data rates can still be used without interferences on communication. The major idea is a change of the protocol. In particular, we exploit the fact that data could be sent in time slots, where CAN-conform nodes don't listen. Finally, c) an implementation of this type of overclocking scheme on an FPGA is provided to prove the feasibility and the impressive through-put gains. © 2009 EDAA.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.canane

Can Approximate Computing Reduce Power Consumption on FPGAs? - Echavarria Gutiérrez, Jorge Alfonso; Schütz, Katja; Becher, Andreas; Wildermann, Stefan; Teich, Jürgen (Proceedings of IEEE International Conference on Electronics Circuits and Systems, 2018)
Approximate computing allows to tackling conflicting objectives, such as power and accuracy of computations. In this paper, we first describe how knowledge of stimuli's specific features can help in quantifying and improving power savings by means of approximate computing. We investigate FPGA implementations of several approximate circuits and compare their power consumption with non-approximating versions. In particular, we study approximate arithmetics and a clock-gate based technique called memoization. Moreover, we compare the accuracy of estimation techniques for power consumption evaluation versus real measurements under controlled environments. We also experimentally quantify the relationship between switching activity and power consumption. Two important results are concluded from our investigations: (1) Approximate arithmetics do not necessarily consume less power than conventional circuits, whereas memoization techniques can, in fact, reduce power consumption. (2) Simulation-based power evaluation for approximate FPGA implementations can reach fidelity values up to about 89% in input-dependent power characteristics. Yet, to evaluate absolute savings, measurements are require
Keywords: Switching Activity; Power Consumption; Approximate Computing

CAN+: Techniques and Prototype for Achieving Increased Data Rates on the Basis of Common CAN Bus Structures - Ziermann, Tobias; Teich, Jürgen; Wildermann, Stefan (Proc. 9th Stuttgart, International Symposium, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.cantec

CAP: Communication Aware Programming - Heisswolf, Jan; Zaib, Aurang; Zwinkau, Andreas; Kobbe, Sebastian; Weichslgartner, Andreas; Teich, Jürgen; Henkel, Jörg; Snelting, Gregor; Herkersdorf, Andreas; Becker, Jürgen (Proc. of The 51st Annual Design Automation Conference (DAC), 2014)
Networks on Chip (NoC) come along with increased complexity from the implementation and management perspective. This leads to higher energy consumption and programming complexity of NoC architectures. This work introduces communication aware programming to address communication resource management and efficient programming of NoC architectures. A programming interface is introduced to express communication requirements at the language level. These requirements are evaluated by an operating system component, which configures the communication hardware accordingly. The proposed concept enables an intuitive use of NoC features like end-to-end connections and Direct Memory Access (DMA). The presented results show that communication aware programming can improve performance and energy consumption. Copyright 2014 ACM.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.capcom
Keywords: Communication; Invasive; Many-core; Network on chip; X10

Cell-based Update Algorithm for Occupancy Grid Maps and new Hybrid Map for ADAS on Embedded GPUs - Fickenscher, Jörg; Schlumberger, Jens; Hannig, Frank; Bouzouraa, Mohammed Essayed; Teich, Jürgen (Design, Automation and Test in Europe (DATE), 2018)

Chapter 6 in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation - Bhattacharyya, Shuvra S.; Deprettere, Ed; Teich, Jürgen (Marcel Dekker, 2004)
UnivIS-Import:2015-05-08:Pub.2004.tech.IMMD.inform.energy

Characterisation and Analysis of Invasive Algorithmic Patterns - Bader, Michael; Wildermann, Stefan; Glaß, Michael; Pöppl, Alexander; Pourmohseni, Behnaz; Schwarzer, Tobias; Spieck, Jan; Wille, Mario (Invasive Computing, 2022)

Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks - Trautmann, Jens; Teich, Jürgen; Wildermann, Stefan (30th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2022)
FPGAs offer fast and reliable near-data processing and are therefore suitable candidates for implementing IoT and edge computing systems. As they are usually deployed in exposed locations, they are vulnerable to physical attacks, especially Side-Channel Analysis (SCA). In this paper, we characterize side-channels and how they can be exploited for SCA on FPGA-based off-the-shelf boards, i.e. without having to make any modifications to the board, hardware, or software. The basic requirement for any kind of SCA is that the individual Cryptographic Operations (COs) in the side-channel traces can be detected. To this end, we apply a SCA for semi-automatic CO detection that can be generically applied off-the-shelf to a wide variety of boards. Additionally, we introduce a new metric called Signal of COs to Noise Ratio (SCONR), that allows to quantify the pronouncedness of COs versus noise in a side channel. We then evaluate side channels measured on three different boards containing Xilinx 7 series FPGAs. We further investigate the influence of other sources of noise and how much they affect the attackability of a system. Our results show that FPGAs have a high vulnerability to SCA in general and that even noise from an operating system will not hinder the recording and finding of COs in an automated fashion as long as there are no countermeasures in place. Finally, SCONR converges after fewer recorded traces and gives a clearer indication whether a side channel is susceptible to this type of automated attack than leakage assessment techniques such as TVL
Keywords: Side-Channel Analysis; Off-The-Shelf FPGA Boards; Hardware Security; Security Assessment

Chatbot-Based Assertion Generation from Natural Language Specifications - Keszöcze, Oliver; Harris, Ian G. (Forum on Specification & Design Languages (FDL), 2019)
We present an approach to simplify the task of ex tracting assertions from specifications given in natural language. Our goal is to accept and understand a broad range of linguistic variation, allowing the author of the natural language specifications to express herself freely. To enable this, we leverage the Dialogflow framework from Google. Dialogflow is usually used to build chatbots that understand and respond to conversational statements. We have trained a Dialogflow model to recognize a range of different natural language expressions of properties, and to identify key information inside the expression. The model responses to each statement with a generated SystemVerilog assertion whose semantic meaning is equivalent to that of the English statement.<br
Keywords: Assertion-based Verification; Natural Language Understanding; Automatic Assertion Generation; Assertion Mining

CHOICE – A Tunable PUF-Design for FPGAs - Streit, Franz-Josef; Krüger, Paul; Becher, Andreas; Schlumberger, Jens; Wildermann, Stefan; Teich, Jürgen (IEEE Proceedings of the 31th International Conference on Field Programmable Logic and Applications, 2021)
FPGA-based Physical Unclonable Functions (PUFs) have emerged as a viable alternative to permanent key storage by turning inaccuracies during the manufacturing process of a chip into a unique, FPGA-intrinsic secret. However, many fixed PUF designs may suffer from unsatisfactory statistical properties in terms of uniqueness, uniformity, and robustness. Moreover, a PUF signature may alter over time due to aging or changing operating conditions, rendering a PUF insecure in the worst case. As a remedy, we propose CHOICE, a novel class of FPGA-based PUF designs with tunable uniqueness and reliability characteristics. By the use of addressable shift registers available on an FPGA, we show that a wide configuration space for adjusting a device-specific PUF response is obtained without any sacrifice of randomness. In particular, we demonstrate the concept of address-tunable propagation delays, whereby we are able to increase or decrease the probability of obtaining ’1’s in the PUF response. Experimental evaluations on a group of six 28 nm Xilinx Artix-7 FPGAs show that CHOICE PUFs provide a large range of configurations to allow a fine-tuning to an average uniqueness between 49% and 51%, while simultaneously achieving bit error rates below 1.5%, thus outperforming state-of-the-art PUF designs. Moreover, with only a single FPGA slice per PUF bit, CHOICE is one of the smallest PUF designs currently available for FPGAs. <br
Keywords: PUF; Security; FPGA; Hardware/Software Co-Design

Classification of general data flow actors into known models of computation - Zebelein, Christian; Falk, Joachim; Haubelt, Christian; Teich, Jürgen (Proc. of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2008), 2008)
Applications in the signal processing domain are often modeled by data flow graphs which contain both dynamic and static data flow actors due to heterogeneous complexity requirements. Thus, the adopted notation to model the actors must be expressive enough to accommodate dynamicdata flow actors. On the other hand, treating static data flow actors like dynamic ones hinders design tools in applying domain-specific optimization methods to static parts of the model, e.g., static scheduling. In this paper, we present a general notation and a methodology to classify an actor expressed by means of this notation into the synchronous and cyclo-static data flow models of computation. This enables the use of a unified descriptive language to express the behavior of actors while still retaining the advantage to apply domain-specific optimization methods to parts of the system. In experiments we could improve both latency and throughput of a general data flow graph application using our proposed automatic classification in combination with a static single-processor scheduling approach by 57%. © 2008 IEEE.

Clustering-Based Scenario-Aware LTE Grant Prediction - Brand, Peter; Sabih, Muhammad; Falk, Joachim; Ah Sue, Jonathan; Teich, Jürgen (Proceedings of the 2020 IEEE Wireless Communications and Networking Conference (WCNC), 2020)

Code Generation for Embedded Heterogeneous Architectures on Android - Membarth, Richard; Reiche, Oliver; Hannig, Frank; Teich, Jürgen (Proceedings of the Conference on Design, Automation and Test in Europe (DATE), 2014)
The success of Android is based on its unified Java programming model that allows to write platform-independent programs for a variety of different target platforms. However, this comes at the cost of performance. As a consequence, Google introduced APIs that allow to write native applications and to exploit multiple cores as well as embedded GPUs for compute-intensive parts. This paper proposes code generation techniques in order to target the Renderscript and Filterscript APIs. Renderscript harnesses multi-core CPUs and unified shader GPUs, while the more restricted Filterscript also supports GPUs with earlier shader models. Our techniques focus on image processing applications and allow to target these APIs and OpenCL from a common description. We further supersede memory transfers by sharing the same memory region among different processing elements on HSA platforms. As reference, we use an embedded platform hosting a multi-core ARM CPU and an ARM Mali GPU. We show that our generated source code is faster than native implementations in OpenCV as well as the pre-implemented script intrinsics provided by Google for acceleration on the embedded GPU. © 2014 EDA
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.codege_28
Keywords: GRK-1773

Code Generation for GPU Accelerators from a Domain-Specific Language for Medical Imaging - Membarth, Richard (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2013)

Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs - Schmid, Moritz; Reiche, Oliver; Schmitt, Christian; Hannig, Frank; Teich, Jürgen (Proc. of the First International Workshop on FPGAs for Software Programmers (FSP), 2014)
Multiresolution Analysis (MRA) is a mathematical method that is based on working on a problem at different scales. One of its applications is medical imaging where processing at multiple scales—based on the concept of Gaussian and Laplacian image pyramids—is a well-known technique. It is often applied to reduce noise while preserving image detail on different levels of granularity without modifying the filter kernel. In scientific computing, multigrid methods are a popular choice, as they are asymptotically optimal solvers for elliptic Partial Differential Equations (PDEs). As such algorithms have a very high computational complexity that would overwhelm CPUs in the presence of real-time constraints, application-specific processors come into consideration for implementation. Despite of huge advancements in leveraging productivity in the respective fields, designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. Recently, the HIPAcc framework was proposed as a means for automatic code generation of image processing algorithms, based on a Domain-Specific Language (DSL). From the same code base, it is possible to generate code for efficient implementations on several accelerator technologies including different types of Graphics Processing Units (GPUs) as well as reconfigurable logic (FPGAs). In this work, we demonstrate the ability of HIPAcc to generate code for the implementation of multiresolution applications on FPGAs and embedded GPUs.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.codege_1
Keywords: GRK-1773; ExaStencils

Code Generation for Tightly Coupled Processor Arrays - Boppu, Srinivas (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2015)

Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators - Reiche, Oliver; Schmid, Moritz; Hannig, Frank; Membarth, Richard; Teich, Jürgen (Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2014)
As today's computer architectures are becoming more and more heterogeneous, a plethora of options including CPUs, GPUs, DSPs, reconfigurable logic (FPGAs), and other application-specific processors come into consideration for close-to-sensor processing. Especially, in the domain of image processing on mobile devices, among numerous design challenges, a very stringent energy budget is of utmost importance, making embedded GPUs and FPGAs ideal targets for implementation. Recently, the HIPAcc framework was proposed as a means for automatic code generation of image processing algorithms for embedded GPUs, based on a Domain-Specific Language (DSL). Despite of huge advancements in High-Level Synthesis (HLS) for FPGAs, designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. As a remedy, in this work, we propose code generation techniques for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, numerous high-level transformations, and automatic test bench generation. We evaluate our approach by comparing the resulting hardware accelerators to existing frameworks in terms of performance and resource requirements. Moreover, we assess the achieved energy efficiency in contrast to software implementations, generated by HIPAcc from the same code base, executed on GPUs. Copyright 2014 AC
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.codege
Keywords: Code generation; Domain-specific language; Image processing; High-level synthesis; Hardware accelerator; FPGA; GPU

CodeSign: An Embedded System Design Environment - Esser, Rob; Teich, Jürgen; Thiele, Lothar (IEE Proceedings E: Computers and Digital Techniques, 1998)

Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs - Angermeier, Josef; Hanke, Stefan; Majer, Mateusz; Teich, Jürgen; Wildermann, Stefan (Proc. 19th IEEE/IFIP International Symposium on Rapid System Prototyping, 2008)
Current graphic cards include advanced graphic processing units to accelerate the rendering of 3D objects with millions of polygons. As object models grow in complexity, the rendering approach based on points as primitives is regarded superior in terms of scalability and efficiency. Next generation graphic cards could contain reconfigurable fabrics, similar to those implemented in current FPGAs, to offer two advantages: a) fast rendering units and b) new mechanisms for custom, run-time exchangeable accelerators. In this paper, we propose a hardware point-rendering architecture tailored specifically for reconfigurable systems. The presented implementation on a real FPGA-based platform demonstrates on the one hand the effectiveness of the approach and on the other hand it provides valuable insights into possible future improvements for this problem scenario. © 2008 IEEE. DOI 10.1109/RSP.2008.23.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.codesi

Co-Design of Massively Parallel Embedded Processor Architectures - Dutta, Hritam; Hannig, Frank; Kupriyanov, Olexiy; Teich, Jürgen; Schaffer, Rainer; Siegel, Sebastian; Merker, Renate; Keryell, Ronan; Pottier, Bernard; Chillet, Daniel; Ménard, Daniel; Sentieys, Olivier (Proceedings of the first ReCoSoC Workshop, 2005)
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.codesi

CODES+ISSS 2007 guest editors' introduction - Dutt, Nikil; Teich, Jürgen (Design Automation For Embedded Systems, 2009)

Combined system synthesis and communication architecture exploration for MPSoCs - Lukasiewycz, Martin; Streubühr, Martin; Glaß, Michael; Haubelt, Christian; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE 2009), 2009)
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of a system. Given an application model written in SystemC TLM 2.0, the proposed approach performs a fully automatic optimization by a simultaneous resource allocation, task binding, data mapping, and transaction routing for MPSoC platforms. To cope with the huge complexity of the design space, a transformation of the transaction level model to a graph-based model and symbolic representation that allows multi-objective optimization is presented. Results from optimizing a Motion-JPEG decoder illustrate the effectiveness of the proposed approach. © 2009 EDAA.

Combining Formal Model-Based System-Level Design with SystemC Transaction Level Modeling - Gladigau, Jens (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2013)

Combining Multiple Models of Computation for Scheduling and Allocation - Ernst, Rolf; Richter, Kay; Teich, Jürgen; Thiele, Lothar; Ziegenbein, Dirk (Proc. of Codes/CASHE\'98, the 6th Int. Workshop on Hardware/Software Codesign, 1998)

Communication Aware Optimization of the Task Binding in Hardware/Software Reconfigurable Networks - Streichert, Thilo; Strengert, Christian; Koch, Dirk; Teich, Jürgen; Haubelt, Christian (Journal of Integrated Circuits and Systems, 2007)
In this paper, a new methodology for tolerating link as well as node defects in self-adaptive reconfigurable networks will be presented. Currently, networked embedded systems need a certain level of redundancy for each node and link in order to tolerate defects and failures in a network. Due to monetary constraints as well as space and power limitations, the replication of each node and link is not an option in most embedded systems. Therefore, we will present a hardware/software partitioning algorithm for reconfigurable networks that optimizes the task binding onto resources at runtime such that node/link defects can be handled and data traffic on links between computational nodes will be minimized. This paper presents a new hardware/software partitioning algorithm, an experimental evaluation and for demonstrating the applicability, an implementation on a network of FPGA-based boards.
UnivIS-Import:2015-04-14:Pub.2007.tech.IMMD.inform.commun
Keywords: Dynamic hardware/software partitioning; Reconfigurable network; Task placement

Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays - Hannig, Frank; Merker, Renate; Siegel, Sebastian; Teich, Jürgen (Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems, 2006)
Methods for an efficient mapping of algorithms to parallel architectures are of utmost importance because many state-of-the-art embedded digital systems deploy parallelism to increase their computational power. This paper deals with the mapping of loop programs onto processor arrays implemented in an FPGA or available as (reconfigurable) coarsegrained processor architectures. Most existing work is closely related to approaches from the DSP domain and is not able to exploit the full parallelism of a given algorithm and the computational potential of a typical 2-dimensional array. In contrast, we present a mapping methodology which incorporates many important parameters of the target architecture in one approach. These are: number of processing elements, resources of the data path and memory within a processing element, and interconnection within the processor array. Based on these parameters, we formulate an optimization problem whose solution specifies an efficient mapping of an algorithm to the target architecture. We can optimize for speed of the algorithm and/or hardware cost caused by the communication and computation resources of the architecture.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.commun
Keywords: Data path; Hardware mapping; Integer linear programming; Interconnection; Processor array

Communication-driven Automatic Virtual Prototyping for Networked Embedded Systems - Zhang, Liyuan; Falk, Joachim; Schwarzer, Tobias; Glaß, Michael; Teich, Jürgen (Proc. of Euromicro Conference on Digital System Design (DSD), 2014)
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.commun

Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures - Wolinski, Christophe; Kuchcinski, Krzysztof; Teich, Jürgen; Hannig, Frank (Proceedings of the 11th Euromicro Conference on Digital System Design, 2008)
In this paper, we introduce a constraint programming-based approach for optimization of routing and reconfiguration overhead for a class of reconfigurable processor array architectures called weakly programmable. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for optimal routing of data between processors as well as for minimization of the routing area and the reconfiguration overhead when switching between the execution of these algorithms. In fact, applying the switching can be accomplished in just a few clock cycles. Our experiments confirm that our method can minimize routing overhead and reduce reconfiguration time significantly. © 2008 IEEE.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.commun
Keywords: Communication network; Optimization; Programmable processor array architectures; Reconfiguration overhead

Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays - Teich, Jürgen; Boppu, Srinivas; Hannig, Frank; Lari, Vahid (Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung, 2015)

Compact Code Generation for Tightly-Coupled Processor Arrays - Boppu, Srinivas; Hannig, Frank; Teich, Jürgen (Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2014)
In this paper, we consider programmable tightly-coupled processor arrays consisting of interconnected small light-weight VLIW cores, which can exploit both loop-level parallelism and instruction-level parallelism. These arrays are well suited for compute-intensive nested loop applications often providing a higher power and area efficiency compared with commercial off-the-shelf processors. They are ideal candidates for accelerating the computation of nested loop programs in future heterogeneous systems, where energy efficiency is one of the most important design goals for overall system-on-chip design. In this context, we present a novel design methodology for the mapping of nested loop programs onto such processor arrays. Key features of our approach are: (1) Design entry in form of a functional programming language and loop parallelization in the polyhedron model, (2) support of zero-overhead looping not only for innermost loops but also for arbitrarily nested loops. Processors of such arrays are often limited in instruction memory size to reduce the area and power consumption. Hence, (3) we present methods for code compaction and code generation, and integrated these methods into a design tool. Finally, (4) we evaluated selected benchmarks by comparing our code generator with the Trimaran and VEX compiler frameworks. As the results show, our approach can reduce the size of the generated processor codes up to 64 % (Trimaran) and 55 % (VEX) while at the same time achieving a significant higher throughput.
UnivIS-Import:2015-04-20:Pub.2014.tech.IMMD.inform.compac
Keywords: Accelerators; Coarse-grained reconfigurable architectures; Code generation; Compilers; Massively parallel processor arrays

Comparison and evaluation of acceleration based step length estimators for handheld devices - Patino-Studencki, Lucila; Batzer, Ulrich; Gutiérrez Boronat, Javier; Jahn, Jasper; Seitz, Jochen (2010 International Conference on Indoor Positioning and Indoor Navigation, 2010)
A comparison between different step length estimation algorithms for pedestrian dead reckoning is presented. This work covers theoretic evaluation of the estimators' performance and presents a comparison based on measurement data. Measurement data were taken from a group of five adults walking at three different velocities. For reference, the sensors were placed according to the recommendation given for each algorithm. In respect to everyday usability the performance of the estimators is furthermore evaluated for arbitrary placement of the sensors, as it is the case when using a mobile measurement platform like a smartphone.
Keywords: Global Positioning System; inertial navigation; length measurement; mobile handsets; mobile radio; notebook computers; sensor placement; acceleration; handheld devices; mobile measurement; pedestrian dead reckoning; sensor placement; smartphone; step length estimators; Acceleration; Accelerometers; Calibration; Estimation; Legged locomotion; Sensors; Systematics; Accelerometer; Pedestrian Dead Reckoning; Pedestrian Navigation; Step Length Estimation

Comparison of data structures for storing Pareto-sets in MOEAs - Mostaghim, Sanaz; Teich, Jürgen; Tyagi, Ambrish (2002 Congress on Evolutionary Computation, CEC 2002, 2002)
In MOEAs with elitism, the data structures and algorithms for storing and updating archives may have a great impact on the CPU time, especially when optimizing continuous problems with larger population sizes. In this paper, we introduce quadtrees as an efficient data structure for storing Pareto-points. Apart from conventional linear lists, we have implemented three kinds of quadtrees for the archives. These data structures were examined for different examples. The results presented show that linear lists perform better in terms of CPU time for small population sizes whereas tree structures perform better for large population sizes. © 2002 IEEE.

Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures - Membarth, Richard; Hannig, Frank; Teich, Jürgen; Körner, Mario; Eckert, Wieland (Proc. Embedded World Conference, 2010)
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.compar

Comparison of Techniques for the Automatic Verification of ADeVA Specifications - Dinkel, Thomas; Haubelt, Christian; Heinkel, Ulrich; Schlichter, Thomas; Knäblein, Joachim; Schock, Thomas; Teich, Jürgen (Proc. Dresdener Arbeitstagung Schaltungs- und Systementwurf (DASS 2005), 2005)

Compilation and Code Generation for Invasive Programs - Snelting, Gregor; Teich, Jürgen; Fried, Andreas; Hannig, Frank; Witterauf, Michael (Invasive Computing, 2022)

Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization - Schwarzer, Tobias; Falk, Joachim; Müller, Simone; Letras, Martin; Heidorn, Christian; Wildermann, Stefan; Teich, Jürgen (ACM Transactions on Design Automation of Electronic Systems, 2019)
State-of-the-art system synthesis techniques employ meta-heuristic optimization techniques for Design Space Exploration (DSE) to tailor application execution, e.g., defined by a dataflow graph, for a given target platform. Unfortunately, the performance evaluation of each implementation candidate is computationally very expensive, in particular on recent multi-core platforms, as this involves compilation to and extensive evaluation on the target hardware. Applying heuristics for performance evaluation, on the one hand, allows for a reduction of the exploration time but on the other hand, may deteriorate the convergence of the optimization technique toward performance-optimal solutions with respect to the target platform. To address this problem, we propose DSE strategies that are able to dynamically trade off between (i) approximating heuristics to guide the exploration and (ii) accurate performance evaluation, i.e., compilation of the application and subsequent performance measurement on the target platform. Technically, this is achieved by introducing a set of additional, but easily computable guiding objective functions, and varying the set of objective functions that are evaluated during the DSE adaptively. One major advantage of these guiding objectives is that they are generically applicable for dataflow models without having to apply any configuration techniques to tailor their parameters to the specific use case. We show this for synthetic benchmarks as well as a real-world control application. Moreover, the experimental results demonstrate that our proposed adaptive DSE strategies clearly outperform a state-of-the-art DSE approach known from literature in terms of the quality of the gained implementations as well as exploration times. Amongst others, we show a case for a two-core implementation where after about 3 hours of exploration time one of our proposed adaptive DSE strategies already obtains a 60% higher performance value than obtained by the state-of-the-art approach. Even when the state-of-the-art approach is given a total exploration time of more than 2 weeks to optimize this value, the proposed adaptive DSE strategy features a 20% higher performance value after a total exploration time of about 4 days.<br

Compilation Techniques for CGRAs: Exploring All Parallelization Approaches - Vander Aa, Tom; Raghavan, Praveen; Mahlke, Scott; De Sutter, Björn; Shrivastava, Aviral; Hannig, Frank (Proc. 8th International Conference on Hardware-Software Codesign and System Synthesis, 2010)
On behalf of the CODES+ISSS 2010 Program Committee, we would like to welcome you to the 8th IEEE/ACM International Conference on Hardware/Software- Co-Design and System Synthesis. CODES+ISSS is the premier conference for system-level design, with a focus on the design of embedded systems hardware, software, and tools. This year we continue the tradition of maintaining a high-quality forum for active discussion on current and innovative topics on embedded systems that bring together the latest in academic and industrial research and development. We selected the best submitted papers through a rigorous review process, and have assembled an exciting program with a mix of keynotes, tutorials, special sessions, and regular papers. This year we received 98 full paper submissions and selected 33 papers for publication, with an acceptance rate of 34%. The Program Committee carefully reviewed all papers, with an average of 4 reviews per paper. The Committee then met face to face for detailed discussions on the papers. Final paper selections were based on overall quality and novelty. Active interaction between presenters and audience has been traditionally extremely important in this conference. To encourage this we have organized poster sessions during the last 30 minutes of every session. This will give you the opportunity to discuss with all presenters independently of which of the two parallel tracks you attended. We trust you will find this year's program to be exciting and stimulating. It truly contains important advances in theory and practice of systemlevel design and related areas. We also continue the tradition of complementing the CODES+ISSS program with tutorials and special sessions. This year's tutorials and special sessions cover timely and emerging topics such as the future of interconnect; best practices and new directions for system level design; challenges and opportunities in high performance computing; an introduction to the new standard for SystemC synthesis; and compilation techniques for coarse-grain programmable arrays. CODES+ISSS is part of the growing Embedded Systems Week (ESWEEK) event that is becoming the premier international event in embedded systems research and development. CODES+ISSS is complemented by two other flagship sister conferences: EMSOFT, and CASES. Registrants to ESWEEK may attend sessions in any of the three conferences. The technical programs of the three conferences, including keynotes, special sessions, panels, tutorials and workshops, have been carefully planned to avoid major overlaps and complement each other.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.compil

Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs - Plagwitz, Patrick; Streit, Franz-Josef; Becher, Andreas; Wildermann, Stefan; Teich, Jürgen (IEEE Proceedings of the 14th International Conference on ReConFigurable Computing and FPGAs, 2019)
In order to meet tight performance and/or energy constraints of embedded systems, the implementation of applications in hardware is often a must. However, mapping of algorithms to platforms, as for example Field-Programmable Gate Arrays (FPGAs), still requires comprehensive hardware knowledge and sometimes long design cycles. Modern High-Level Synthesis (HLS) offers a means to ease the generation of hardware implementations from a software specification of an application. Although these tools have improved greatly in recent years, they often do not provide full coverage of important programming constructs and are therefore of limited use when used with existing or automatically generated code. Soft-core processors implemented with FPGA-logic can circumvent this limitation. However, these come with drawbacks in terms of performance and resource requirements as a general-purpose architecture is used to implement the application in software rather than as a highly specialized circuit. As a remedy, our work presents a novel compiler-based synthesis methodology that generates networks of Application-Specific Instruction Set Processors (ASIPs) from unmodified C/C++ algorithms. We thereby bridge the gap between traditional soft-core processors and HLS. To show the practicability of our approach, we present a case study of a JPEG decoder application while investigating design objectives like resource costs and performance. Apart from the generality of the compiler-based approach, our approach also shows better results in terms of required hardware resources and execution times compared to Instruction Set Architecture (ISA)-fixed commercial Xilinx MicroBlaze soft-core
Keywords: FPGA; HLS; ASIP; SoC; Hardware/Software Co-Design

Compiler-based Processor Network Generation for Neural Networks on FPGAs - Plagwitz, Patrick; Hannig, Frank; Teich, Jürgen; Keszöcze, Oliver (Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), 2024)
The fast-moving field of Neural Network (NN) research has brought breakthroughs in application domains like image or natural language processing. However, since new techniques are constantly emerging, fast prototyping of Neural Networks on edge devices like Field-Programmable Gate Arrays (FPGAs) is particularly appealing due to their reconfigurability. Existing compiler-based toolchains generating specialized hardware are rare and restricted in their scope and coverage. In this paper, we propose a novel NN model-to-hardware flow that exploits the capabilities of Application-Specific Instruction Set Processors (ASIPs) and networks that can be built to implement NNs in a scalable and mixed hardware/software-reconfigurable way. Starting with an NN specification in PyTorch, an ASIP network generation toolchain is presented in which each instantiated core is assigned a portion of neurons to execute a given NN in a parallel and pipelined way while tailoring the instruction set of each core to the computations of the neurons. In addition, we propose multiple ML-specific instruction set extensions realized in hardware, including bit width-restricted ALU operations and activation functions with the circuits automatically generated from a given C/C++ implementation. Experimental results include a design space exploration of alternative implementations for the design objectives of FPGA resource usage, latency, and throughput. Our approach is shown to achieve higher speed-ups than similar processor-based approaches while consuming lower amounts of resources.<br

Compile-Time Optimization of Dynamic Hardware Reconfigurations - Fekete, Sandor P.; Schepers, Jörg; Teich, Jürgen (Proc. Int. Conf. on Parallel and Distributed Processing Techniques and Applications, 1999)
UnivIS-Import:2015-04-16:Pub.1999.tech.IMMD.inform.compil

Composition of Efficient Nested BSP Algorithms: Minimum Spanning Tree Computation as an Instructive Example - Bonorden, Olaf; Meyer auf der Heide, Friedhelm; Wanka, Rolf (Proceedings of the Int. Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA), 2002)

Computational Complexity of Error Metrics in Approximate Computing - Keszöcze, Oliver; Soeken, Mathias; Drechsler, Rolf (Further Improvements in the Boolean Domain, 2018)
The amount of digital systems supporting our daily life is increasing continuously. Improved technical facilities for their production have led to growing challenges for engineers and scientists working in the Boolean domain. A Boolean variable can only carry two different Boolean values: FALSE or TRUE (0 or 1), and has the best interference resistance in technical systems. However, a Boolean function exponentially depends on the number of its variables. This exponential complexity is the reason for major problems in the process of design and realization of circuits. According to Moore’s Law, the complexity of digital systems approximately doubles every 18 months. This requires comprehensive knowledge and techniques to solve very complex Boolean problems. This volume represents the third book in a series that provides further insights into the Boolean domain. Part 1 explores powerful models, methods and techniques which improve the efficiency in solving Boolean problems of extreme complexity. The universality of Boolean equations as a model to solve Non-deterministic Polynomial-time (NP) hard problems, as well as special properties of index generation functions, spectral techniques, or relational approaches, is discussed here. Both hardware devices, such as Field Programmable Gate Arrays (FPGAs) or Graphics Processing Units (GPUs), and optimized algorithms realized in software contribute to the acceleration of Boolean calculations. Part 2 contributes to the synthesis and visualization of digital circuits, and provides interesting new solutions for several types of circuits. A comprehensive collection of benchmarks supports the evolution of both existing and new synthesis approaches. The continuous reduction of the size of the transistors increases the challenges with regard to the reliability of the circuits. Part 3 describes several new approaches for the synthesis of reversible circuits. These approaches, as well as a classification of reversible functions, extend the basis of future quantum computer

Concepts and Algorithms to Increase the Efficiency and Reliability of Reconfigurable Computer - Angermeier, Josef (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2013)

Concepts for Autonomic Integrated Systems - Stechele, Walter; Bringmann, Oliver; Ernst, Rolf; Herkersdorf, Andreas; Hojenski, Katharina; Janacik, Peter; Rammig, Franz; Teich, Jürgen; Wehn, Norbert; Zeppenfeld, Johannes; Ziener, Daniel (Proceedings of edaWorkshop07, 2007)
UnivIS-Import:2015-04-16:Pub.2007.tech.IMMD.inform.concep

Concepts for Autonomous Control Flow Checking for Embedded CPUs - Ziener, Daniel; Teich, Jürgen (Proceedings of the 5th International Conference on Autonomic and Trusted Computing (ATC-08), 2008)
In this paper, we introduce new concepts and methods for checking the correctness of control flow instructions during the execution of programs in embedded CPUs. Detecting and avoiding the execution of faulty control flow instructions is a problem of growing importance w.r.t. reliability and security. On the other hand, hardware cost overheads and an easy integration into the design flow are of utmost important for cost sensitive embedded systems. Our proposed methodology is able to monitor all direct jumps and branches as well as calls and returns form subroutines autonomously during program execution. Furthermore, we propose and evaluate an implementation of an autonomous checker unit which is closely coupled to the processor and can detect and even avoid the execution of a faulty control flow instruction. Upon detection of a faulty instruction, we propose a method to refetch and reexecute the incorrect jump or branch instruction. Other benefits of this novel approach are that the application code must not be changed or augmented by signatures or additional instructions, and that there is no measurable performance impact in terms of execution latency. From the user point of view, our approach is completely transparent to a program developer. © 2008 Springer-Verlag Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.concep_4

Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs - Ziener, Daniel; Teich, Jürgen (International Journal of Autonomous and Adaptive Communications Systems, 2009)
In this paper, we introduce new concepts and methods for checking the correctness of control flow instructions (CFI) issued during the execution of programs for embedded RISC CPUs. Our proposed methodology is able to detect at run-time any error of illegal or faulty direct jump and branch instruction as well as call and return form subroutine for a given program code. Furthermore, two different hardware concepts and implementations of generic control flow (CF) checker units which may be tightly attached to a given CPU are proposed. These implementations can detect and even avoid the execution of faulty CFI at very low area and usually no latency penalty. Other benefits of this novel approach are that the application code must not be changed or augmented by signatures or additional instructions at all. The presented approach is, thus, completely transparent to the program developer. Copyright © 2009 Inderscience Enterprises Ltd.
UnivIS-Import:2015-03-09:Pub.2009.tech.IMMD.inform.concep
Keywords: Autonomous elements; CF method; CFI method; Control flow checker; Control flow instruction method; Control flow method; Embedded CPUs; Error-resilient control flow checking; Leon core; Monitoring

Concepts for self-adaptive and self-healing networked embedded systems - Streichert, Thilo; Koch, Dirk; Haubelt, Christian; Teich, Jürgen (Organic Computing, 2008)
Networked embedded systems which operate in unattended areas with rare maintenance often make use of redundant resources for guaranteeing reliable service. In this paper, we will present novel concepts for dynamically partitioning and assigning functionality to software as well as hardware reconfigurable resources in a network. As a result, self-adaptive and self-healing systems emerge with a good tradeoff between redundancy and reliability. The proposed concepts are embedded in a three step approach, which 1.) reestablishes the functionality after a resource defect, 2.) optimizes the binding of the running tasks and 3.) creates new replicas of the tasks in the network. In this contribution, we will give an overview over all three parts, but focus on the second step. For this second step, called dynamic hardware/ software partitioning, we will present algorithms, theoretical optimality bounds for workload distributions as well as experimental results. © 2009 Springer-Verlag Berlin Heidelberg.
Keywords: Embedded systems; Fault tolerance; Networks; Reliability; Self-adaptive; Self-healing

Concurrent topology and routing optimization in automotive network integration - Lukasiewycz, Martin; Glaß, Michael; Haubelt, Christian; Teich, Jürgen; Regler, Richard; Lang, Bardo (Proceedings of the 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), 2008)
In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based on a specialized binary Integer Linear Program (ILP) in combination with a Multi-Objective Evolutionary Algorithm (MOEA). The ILP is formulated such that each solution represents a topology and routing that fulfills all requirements and demands of the network. Thus, in an iterative process, this ILP is solved to obtain feasible networks whereas the MOEA is used for the optimization of multiple even non-linear objectives and ensures a fast convergence towards the optimal solutions. Additionally, a domain specific preprocessing algorithm for the ILP is presented that decreases the problem complexity and, thus, allows to optimize large and complex networks efficiently. The experimental results validate the performance of this methodology on two state-of-the-art prototype automotive networks. Copyright 2008 ACM.
Keywords: Automotive; Network integration; Optimization

Conference Reports: Recap of DATE 2019 in Florence, Italy - Teich, Jürgen; Fummi, Franco (IEEE Design & Test, 2019)

Configuration Tempering of BRAM-based AES Implementations on FPGAs - Ziener, Daniel; Pirkl, Jutta; Teich, Jürgen (Proceedings of 2018 International Conference on Reconfigurable Computing and FPGAs, 2018)

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - Schlichtmann, Ulf; Kleeberger, Veit B.; Abraham, Jacob A.; Evans, Adrian; Gimmler-Dumon, Christina; Glaß, Michael; Herkersdorf, Andreas; Nassif, Sani R.; Wehn, Norbert (Proc. of Design, Automation and Test in Europe (DATE), 2014)
The rapid shrinking of device geometries in the nanometer regime requires new technology-aware design methodologies. These must be able to evaluate the resilience of the circuit throughout all System on Chip (SoC) abstraction levels. To successfully guide design decisions at the system level, reliability models, which abstract technology information, are required to identify those parts of the system where additional protection in the form of hardware or software coun-termeasures is most effective. Interfaces such as the presented Resilience Articulation Point (RAP) or the Reliability Interchange Information Format (RIIF) are required to enable EDA-assisted analysis and propagation of reliability information. The models are discussed from different perspectives, such as design and test. © 2014 EDAA.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.connec

Considering Diagnosis Functionality during Automatic System-Level Design of Automotive Networks - Eberl, Michael; Glaß, Michael; Teich, Jürgen; Abelein, Ulrich (Proc. of The 49th Annual Design Automation Conference 2012 (DAC), 2012)
Today, design automation approaches for automotive E/E-architectures focus solely on application functionality, neglecting firmware-related functionalities like diagnostic tests that are of utmost importance for quality features such as dependability or maintenance. However, the latter are typically considered dispensable since they do not provide direct service to the user. This paper proposes a novel approach for integrating optional diagnosis functionality into a holistic design space exploration of automotive E/E-architectures at system-level. Opposed to application functionality, hardware-diagnostics dig deep into the hardware-structures and, hence, require specific tailoring for the employed resources. A case study with Software-Based Self-Tests representing advanced diagnosis functionality gives evidence of the viability and efficiency of the proposed approach, highlighting the importance of a holistic consideration of application as well as firmware-related functionality. © 2012 ACM.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.consid_6
Keywords: automotive; design space exploration; diagnosis

Considering MOST150 during Virtual Prototyping of Automotive E/E Architectures - Graf, Sebastian; Russ, Thomas; Glaß, Michael; Teich, Jürgen (Proc. of Automotive meets Electronics (AmE), GMM Fachbericht 72, 2012)
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.consid

Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates - Witterauf, Michael; Hannig, Frank; Teich, Jürgen (Proceedings of the Symposium on Rapid System Prototyping, 2017)
Keywords: templates; c++; simulator

Control generation in the design of processor array - Teich, Jürgen; Thiele, Lothar (Parallel Processing on VLSI Arrays, 1992)
UnivIS-Import:2015-04-20:Pub.1992.tech.IMMD.inform.contro

Control generation in the design of processor arrays - Teich, Jürgen; Thiele, Lothar (Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 1991)

Controller Synthesis for Mapping Partitioned Programs on Array Architectures - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 19th International Conference on Architecture of Computing Systems, 2006)
Processor arrays can be used as accelerators for a plenty of dataflow-dominant applications. Innately these applications have almost no control flow, but the application of sophisticated partitioning and scheduling techniques in order to handle large scale problems and to balance local memory requirements with I/O-bandwidth has the disadvantage of a more complex control flow. Thus, efficient control path synthesis is one of the greatest challenges when compiling algorithms onto processor arrays. This paper presents an efficient methodology for the automated control path synthesis for the mapping of partitioned algorithms onto processor arrays. The major advantages observed in the presented methodology are seen in, (a) control generation for different partitioning techniques and arbitrary parallelepiped tiles, (b) combined use of a global and a local control strategy in order to reduce the control overhead, (c) up to 90 percent reduction in control path area and resources compared to existing approaches. © Springer-Verlag Berlin Heidelberg 2006.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.contro

Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (2005)

Convergence Analysis for Particle Swarm Optimization - Schmitt, Manuel (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2015)

Convoy Tracking for ADAS on Embedded GPUs - Fickenscher, Jörg; Reinhart, Sebastian; Bouzouraa, Mohammed Essayed; Hannig, Frank; Teich, Jürgen (Intelligent Vehicles Symposium (IV 2017), 2017)

CoreMap: A Rapid Prototyping Environment for Distributed Reconfigurable Systems - Bobda, Christophe (International Journal of Embedded Systems, 2004)
UnivIS-Import:2015-03-09:Pub.2004.tech.IMMD.inform.corema

CORSICA: A Framework for Conducting Real-World Side-Channel Analysis - Schlumberger, Jens; Wildermann, Stefan; Teich, Jürgen (11th IFIP International Conference on New Technologies, Mobility and Security (NTMS), 2021)
With the abundance of computing devices in our everyday life such as IoT devices, improving their security has become a number one priority. While the major focus lies on software security, hardware vulnerabilities are often not considered. Here, particularly side-channel attacks pose a realistic threat to such systems. However, conducting Side-Channel Analysis (SCA) to evaluate those threats currently requires deep expert knowledge, a lab environment, and numerous manual steps. Therefore, it is often ignored in security considerations. In this paper, we analyze the challenges when conducting SCA on consumer-grade devices using template-matching based triggering techniques. By introducing a three-staged framework called CORSICA, we elaborate the obstacles and deficiencies of current state-of-the-art techniques and provide potential solutions for them. Moreover, we validate our claims by introducing a method for semi-automatic extraction of a waveform template of an AES 128 encryption that can be used in combination with a template-matching triggering system. This extraction is based on generic meta information and is demonstrated on a consumer-grade ARM processor board.
Keywords: Side-Channel Analysis; Off-The-Shelves Devices; template-matching trigger

Covering Pareto-optimal fronts by subswarms in multi-objective particle swarm optimization - Mostaghim, Sanaz; Teich, Jürgen (Proceedings of the Congress on Evolutionary Computation (CEC '04), 2004)
Covering the whole set of Pareto-optimal solutions is a desired task of multi-objective optimization methods. Because in general it is not possible to determine this set, a restricted amount of solutions are typically delivered in the output to decision makers. In this paper, we propose a new method using multi-objective particle swarm optimization to cover the Pareto-optimal front. The method works in two phases. In phase 1 the goal is to obtain a good approximation of the Pareto-front. In a second run subswarms are generated to cover the Pareto-front. The method is evaluated using different test functions and compared with an existing covering method using a real world example in antenna design.

Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques - Dellnitz, Michael; Mostaghim, Sanaz; Schütze, Oliver; Teich, Jürgen (Proceedings of the Second International Conference on Evolutionary Multi-Criterion Optimization (EMO), 2003)
We present new hierarchical set oriented methods for the numerical solution of multi-objective optimization problems. These methods are based on a generation of collections of subdomains (boxes) in parameter space which cover the entire set of Pareto points. In the course of the subdivision procedure these coverings get tighter until a desired granularity of the covering is reached. For the evaluation of these boxes we make use of evolutionary algorithms. We propose two particular strategies and discuss combinations of those which lead to a better algorithmic performance. Finally we illustrate the efficiency of our methods by several examples. © Springer-Verlag Berlin Heidelberg 2003.
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.coveri

CPU-aware, process-level redundancy to tolerate faults in multi-core - Aliee, Hananeh; Zarandi, Hamid R.; Tajary, Alireza (2011 International Conference on High Performance Computing and Simulation, HPCS 2011, 2011)
This paper proposes: 1) A dynamically scheduled Process-Level Redundancy (PLR) for enhancing reliability of multi-core systems, 2) A comparison between PLR and Thread-Level Redundancy (TLR), and 3) A fault study on the thread selector unit of a modern processor. The proposed technique employs underutilized CPU resources to improve fault tolerance ability of a system. The evaluation on PLR reliability proves that it performs better than Thread-Level Redundancy (TLR) when the reliability of sub modules in a system is higher than almost 0.8. In this technique, a set of redundant processes are created per application process. The number of replicas is then modified dynamically to achieve better performance. The experimental results on some standard benchmarks show that on average, the CPU is utilized less than 20% during the execution time of applications which can be used to provide 100% fault detection and recovery with almost 10% performance overhead using the proposed technique. Also, the fault study proves that among 7000 faults injected into the thread selector module using OpenSPARC simulator, 83.5% of faults are benign faults, and 16.5% of faults lead to system failure which affect either hardware (13.7%), or program outputs (2.8%). These faults can be all detected using this technique. © 2011 IEEE.
Keywords: fault tolerance; Multi-Core processors; process-level redundancy; reliability; thread-level redundancy

Cross-Layer Dependability Modeling and Abstraction in System on Chip - Herkersdorf, Andreas; Engel, Michael; Glaß, Michael; Henkel, Jörg; Kleeberger, Veit B.; Kochte, Michael A.; Kühn, Johannes M.; Nassif, Sani R.; Rauchfuss, Holm; Rosenstiel, Wolfgang; Schlichtmann, Ulf; Shafique, Muhammad; et al. (Proc. 9th Workshop on Silicon Errors in Logic - System Effects, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.crossl

Cross-Level Compositional Reliability Analysis for Embedded Systems - Glaß, Michael; Yu, Heng; Reimann, Felix; Teich, Jürgen (Proc. of the 31st International Conference on Computer Safety, Reliability, and Security (SAFECOMP), 2012)
Ever shrinking device structures are one of the main reasons for a growing inherent unreliability of embedded system components. As a remedy, various means to increase the reliability of complex embedded systems at several levels of abstraction are available. In fact, their efficient application is a key factor for the successful design of reliable embedded systems. While analysis approaches that evaluate these techniques and their advantages and disadvantages at particular levels exist, an overall system analysis that has to work cross-level is still lacking. This paper introduces a framework for cross-level reliability analysis that enables a seamless and flexible combination of various reliability analysis techniques across different levels of abstraction. For this purpose, a proposed framework provides mechanisms for (a) the composition and decomposition of the system during analysis and (b) the connection of different levels of abstraction by adapters that convert and abstract analysis results. As a case-study, the framework extends and combines three analysis approaches from the MPSoC domain: (I) a BDD-based reliability analysis considers redundancies in the system structure, (II) an analytical behavioral model to consider computational activity, and (III) a temperature simulator for processor cores. This enables to capture thermal reliability threats at transistor level in an overall system analysis. The approach is seamlessly integrated in an automatic Electronic System Level (ESL) tool flow. © 2012 Springer-Verlag.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.crossl

DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems - Weichslgartner, Andreas; Gangadharan, Deepak; Wildermann, Stefan; Glaß, Michael; Teich, Jürgen (Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), 2014)
Future many-core systems are envisaged to support the concurrent execution of varying mixes of different applications. Because of the vast number of binding options for such mixes on heterogeneous resources, enabling predictable application execution is far from trivial. Hybrid application mapping is an efficient way of achieving run-time predictability by combining design-time analysis of application mappings with run-time management. Existing hybrid mapping strategies focus on computation resources and either ignore communication details or make significantly simplifying assumptions like unlimited bandwidth or exclusive usage. But, actual many-core systems consist of constrained and shared computation and communication resources where the run-time decision of whether a feasible application binding on a set of preoccupied resources exists or not is an NP-complete problem. As a remedy, we present a novel hybrid application mapping approach that considers constrained shared communication and computation resources. Here, (a) a design space exploration coupled with a formal performance analysis delivers several resource reservation configurations with verified real-time guarantees for each individual application. The configurations are then transformed to (b) a novel efficient intermediate representation that is passed to the run-time management where we (c) formulate run-time resource reservation and application binding as a constraint satisfaction problem and present an adequate solving mechanism. Our experimental evaluation shows that existing approaches may produce infeasible outcomes and are thus not applicable for predictable application execution, while the proposed approach enables predictable and efficient run-time management of dynamic application mixes. Copyright is held by the owner/author(s).
Keywords: Dse; Hybrid mapping; Many-core; Networks-on-chip; Predictability

Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach - Henkel, Jörg; Chen, Qingqing; Schmitt-Landsiedel, Doris; Glocker, Elisabeth; Sousa, Éricles; Schlichtmann, Ulf; Herkersdorf, Andreas; Hannig, Frank; Wenzel, Volker; Wagner, Philipp; Sagi, Mark; Wild, Thomas; et al. (it - Information Technology, 2016)

Data acquisition and control at the edge: a hardware/software-reconfigurable approach - Streit, Franz-Josef; Wituschek, Simon; Pschyklenk, Michael; Becher, Andreas; Lechner, Michael; Wildermann, Stefan; Pitz, Indra; Merklein, Marion; Teich, Jürgen (Production Engineering, 2020)
Today’s manufacturing facilities and processes offer the potential to collect data on an unprecedented scale. However, conventional Programmable Logic Controllers are often proprietary systems with closed-source hardware and software and not designed to also take over the seamless acquisition and processing of enormous amounts of data. Furthermore, their major focus on simple control tasks and a rigid number of static built-in I/O connectors make them not well suited for the big data challenge and an industrial environment that is changing at a high pace. This paper, advocates emerging hardware- and I/O reconfigurable Programmable System-on-Chip (PSoC) solutions based on Field-Programmable Gate Arrays to provide flexible and adaptable capabilities for both data acquisition and control right at the edge. Still, the design and implementation of applications on such heterogeneous PSoC platforms demands a comprehensive expertise in hardware/software co-design. To bridge this gap, a model-based design automation approach is presented to generate automatically optimized HW/SW configurations for a given PSoC. As a case study, a metal forming process is considered and the design automation of an industrial closed-loop control algorithm with the design objectives performance and resource costs is investigated to show the benefits of the approac
Keywords: FPGA; PSoC; Hardware/software co-design; Model-based engineering; Industrial automation; Manufacturing technology; Forming process; Motor control

Data-Driven Scenario-based Application Mapping for Heterogeneous Many-Core Systems - Spieck, Jan; Wildermann, Stefan; Schwarzer, Tobias; Teich, Jürgen; Glaß, Michael (Multicore/Many-core Systems-on-Chip (MCSoC 2019), 2019)

Data Flow Based System Level Design and Analysis of Concurrent Image Processing Applications - Keinert, Joachim; Haubelt, Christian; Teich, Jürgen (Proceedings of DATE'09 Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, 2009)

Data Flow Based System Level Modeling, Analysis, and Synthesis of High-Performance Streaming Image Processing Applications - Keinert, Joachim (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2009)

Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays - Lari, Vahid; Narovlyanskyy, Andriy; Hannig, Frank; Teich, Jürgen (Proc. of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, 2011)
This paper presents a hardware-supported resource management methodology for massively parallel processor arrays. It enables processing elements to autonomously explore resource availability in their neighborhood. To support resource exploration, we introduce specialized controllers, which can be attached to each of the processing elements. We propose different types of architectures for the exploration controller: fast FSM-based designs as well as flexible programmable controllers. These controllers allow to implement different distributed resource exploration strategies in order to enable parallel programs the exploration and reservation of available resources according to different application requirements. Hardware cost evaluations show that the cost of the simplest implementation of our programmable controller is comparable to our FSM-based implementations, while offering the flexibility for implementing different exploration strategies. We show that the proposed distributed approach can achieve a significant speedup in comparison with centralized resource exploration methods. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.decent

Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications - Letras, Martin; Falk, Joachim; Teich, Jürgen (24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2021)
This paper presents a new approach to estimate the throughput of real-world dataflow applications mapped to multi-core systems based on decision trees. Design Space Exploration (DSE) is employed to explore the mapping alternatives of a given application to a multi-core architecture to find the highest throughput solutions. Here, a fast evaluation of the throughput of a single implementation is required. However, simulation-based as well as measurement-based evaluation approaches impose often unaffordably high evaluation times. During a DSE, this evaluation time is particularly critical, as typically thousands of solutions need to be evaluated. Obviously, there exists a trade-off between evaluation accuracy and time for evaluating the throughput of an implementation. This paper presents a solution exploiting this trade-off by proposing a decision tree-based approach consisting of a trained decision tree model used as a throughput evaluator by the DSE. We show that a well-trained evaluator is able to estimate the throughput of an implementation about 20× faster than using a measurement-based evaluation. Moreover, in order to deliver a sufficient accuracy, our DSE approach uses decision tree-based valuations 90 % of the time and measurement-based evaluations for the remaining 10 %. On average, the resulting DSE approach is able to find Pareto-fronts about 8× faster than a reference DSE using measurements only with equal qualit
Keywords: Decision Tree; Design Space Exploration; MSoCs; Dataflow

Declarative Programming Techniques for Hardware Synthesis of Image Processing Applications - Özkan, Mehmet Akif (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2023)

Decomposing Run-time Resource Management in Heterogeneous Reconfigurable Systems - Wildermann, Stefan; Teich, Jürgen (Proc. Workshop on Self-Awareness in Reconfigurable Computing Systems, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.decomp

Deep Learning to Demodulate Transmissions in Molecular Communication - Bartunik, Max; Keszöcze, Oliver; Schiller, Benjamin; Kirchner, Jens (Proceedings of the 6th Workshop on Molecular Communications, 2022)

Defragmenting the Module Layout of a Partially Reconfigurable Device - Ahmadinia, Ali; Bobda, Christophe; Fekete, Sandor P.; Hannig, Frank; Majer, Mateusz; Teich, Jürgen; Van Der Veen, Jan C. (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005)
Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, making defragmentation an important issue. We address this problem by propose an online and an offline component for the defragmentation of the available space. We consider defragmenting the module layout on a reconfigurable device. This corresponds to solving a two-dimensional strip packing problem. Problems of this type are NP-hard in the strong sense, and previous algorithmic results are rather limited. Based on a graph-theoretic characterization of feasible packings, we develop a method that can solve two-dimensional defragmentation instances of practical size to optimality. Our approach is validated for a set of benchmark instances.
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.defrag
Keywords: Defragmentation; two-dimensional packing; Exact algorithms; NP-hard problems; Partial reconfiguration; Reconfigurable computing

Degree-constrained Subgraph Reconfiguration is in P - Mühlenthaler, Moritz (Proceedings of the 40th International Symposium on Mathematical Foundations of Computer Science (MFCS), 2015)

Dependability-Aware System-Level Design for Embedded Systems - Glaß, Michael (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2011)

Description and Simulation of Microprocessor Instruction Sets Using ASMs - Kutter, Philipp; Teich, Jürgen; Weper, Ralph (Lecture Notes in Computer Science (LNCS) 1912, 2000)
In this paper, we describe how cycle-accurate processor behavior may be efficiently described using Abstract State Machines (ASMs). Given a register transfer description of the target processor, an extraction mechanism is described following the approach in [26] that extracts so called guarded register transfer patterns from the processor description. It will be shown that these may be directly transformed into a set of ASM rules which in turn provide an executable model of the processor for simulation purposes. Here, we use the ASM description language XASM from which the Gem-Mex tool [2] automatically generates a graphical simulator of a given architecture. The feasibility of this approach is demonstrated for an ARM microprocessor. © Springer-Verlag Berlin Heidelberg 2000.
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.descri

Design and Architectures for Dependable Embedded Systems - Henkel, Jörg; Bauer, Lars; Becker, Joachim; Bringmann, Oliver; Brinkschulte, Uwe; Chakraborty, Samarjit; Engel, Michael; Ernst, Rolf; Härtig, Hermann; Hedrich, Lars; Herkersdorf, Andreas; Kapitza, Rüdiger; et al. (Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '11), 2011)
The paper presents an overview of a major research project on dependable embedded systems that has started in Fall 2010 and is running for a projected duration of six years. Aim is a 'dependability co-design' that spans various levels of abstraction in the design process of embedded systems starting from gate level through operating system, applications software to system architecture. In addition, we present a new classification on faults, errors, and failures. Copyright 2011 ACM.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.IMMD4.design_4
Keywords: embedded systems; dependable systems; danceos

Design and Error Analysis of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Keszöcze, Oliver; Khosravi, Faramarz; Becher, Andreas; Teich, Jürgen (it - Information Technology, 2022)
We present the design and a closed-form error analysis of accuracy-configurable multipliers via segmented carry chains. To address this problem, we model the approximate partial-product accumulations as a sequential process. According to a given splitting point of the carry chains, the technique herein discussed allows varying the quality of the accumulations and, consequently, the overall product. Due to these shorter critical paths, such kinds of approximate multipliers can trade-off accuracy for an increased performance whilst exploiting the inherent area savings of sequential over combinatorial approaches. We implemented multiple architectures targeting FPGAs and ASICs with different bit-widths and accuracy configurations to 1) estimate resources, power consumption, and delay, as well as to 2) evaluate those error metrics that belong to the so-called #P-complete class.<br
Keywords: Approximate computing; Sequential Multiplier; Error Analysis

Design and Evaluation of a Tunable PUF Architecture for FPGAs - Streit, Franz-Josef; Krüger, Paul; Becher, Andreas; Wildermann, Stefan; Teich, Jürgen (ACM Transactions on Reconfigurable Technology and Systems, 2021)
FPGA-based Physical Unclonable Functions (PUFs) have emerged as a viable alternative to permanent key storage by turning effects of inaccuracies during the manufacturing process of a chip into a unique, FPGA-intrinsic secret. However, many fixed PUF designs may suffer from unsatisfactory statistical properties in terms of uniqueness, uniformity, and robustness. Moreover, a PUF signature may alter over time due to aging or changing operating conditions, rendering a PUF insecure in the worst case. As a remedy, we propose CHOICE, a novel class of FPGA-based PUF designs with tunable uniqueness and reliability characteristics. By the use of addressable shift registers available on an FPGA, we show that a wide configuration space for adjusting a device-specific PUF response is obtained without any sacrifice of randomness. In particular, we demonstrate the concept of address-tunable propagation delays, whereby we are able to increase or decrease the probability of obtaining ’1’s in the PUF response. Experimental evaluations on a group of six 28 nm Xilinx Artix-7 FPGAs show that CHOICE PUFs provide a large range of configurations to allow a fine-tuning to an average uniqueness between 49% and 51%, while simultaneously achieving bit error rates below 1.5%, thus outperforming state-of-the-art PUF designs. Moreover, with only a single FPGA slice per PUF bit, CHOICE is one of the smallest PUF designs currently available for FPGAs. It is well-known that signal propagation delays are affected by temperature, as the operating temperature impacts the internal currents of transistors that ultimately make up the circuit. We therefore comprehensively investigate how temperature variations affect the PUF response and demonstrate how the tunability of CHOICE enables us to determine configurations that show a high robustness to such variations. As a case study, we present a cryptographic key generation scheme based on CHOICE PUF responses as device-intrinsic secret and investigate the design objectives resource costs, performance, and temperature robustness to show the practicability of our approach.<br

Design and Evaluation of a Tunable PUF Architecture for FPGAs - Streit, Franz-Josef; Krüger, Paul; Becher, Andreas; Wildermann, Stefan; Teich, Jürgen (IEEE Proceedings of the 20th International Conference on Field-Programmable Technology, 2021)
FPGA-based Physical Unclonable Functions (PUFs) have emerged as a viable alternative to permanent key storage by turning effects of inaccuracies during the manufacturing process of a chip into a unique, FPGA-intrinsic secret. However, many fixed PUF designs may suffer from unsatisfactory statistical properties in terms of uniqueness, uniformity, and robustness. Moreover, a PUF signature may alter over time due to aging or changing operating conditions, rendering a PUF insecure in the worst case. As a remedy, we propose CHOICE, a novel class of FPGA-based PUF designs with tunable uniqueness and reliability characteristics. By the use of addressable shift registers available on an FPGA, we show that a wide configuration space for adjusting a device-specific PUF response is obtained without any sacrifice of randomness. In particular, we demonstrate the concept of address-tunable propagation delays, whereby we are able to increase or decrease the probability of obtaining ’1’s in the PUF response. Experimental evaluations on a group of six 28 nm Xilinx Artix-7 FPGAs show that CHOICE PUFs provide a large range of configurations to allow a fine-tuning to an average uniqueness between 49% and 51%, while simultaneously achieving bit error rates below 1.5%, thus outperforming state-of-the-art PUF designs. Moreover, with only a single FPGA slice per PUF bit, CHOICE is one of the smallest PUF designs currently available for FPGAs. It is well-known that signal propagation delays are affected by temperature, as the operating temperature impacts the internal currents of transistors that ultimately make up the circuit. We therefore comprehensively investigate how temperature variations affect the PUF response and demonstrate how the tunability of CHOICE enables us to determine configurations that show a high robustness to such variations. As a case study, we present a cryptographic key generation scheme based on CHOICE PUF responses as device-intrinsic secret and investigate the design objectives resource costs, performance, and temperature robustness to show the practicability of our approac

Design and Evaluation of Ethernet-based E/E-Architectures for Latency- and Safety-critical Applications - Smirnov, Fedor (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2019)

Design and Evaluation of Future Ethernet AVB-based ECU Networks - Glaß, Michael; Graf, Sebastian; Reimann, Felix; Teich, Jürgen (Embedded Systems Development, From Functional Models to Implementations 2014, 2014)
UnivIS-Import:2015-04-20:Pub.2013.tech.IMMD.inform.design

Design and Experimental Evaluation of Multiple Adaptation Layers in Self-optimizing Particle Swarm Optimization - Ritscher, Thomas; Helwig, Sabine; Wanka, Rolf (Proceedings of the IEEE Congress on Evolutionary Computation (CEC 2010), 2010)
Particle swarm optimization (PSO) is a nature-inspired technique for solving continuous optimization problems. For a fixed optimization problem, the quality of the found solution depends significantly on the choice of the algorithmic PSO parameters such as the inertia weight and the acceleration coefficients. It is a challenging task to choose appropriate values for these parameters by hand or mathematically. In this paper, a novel self-optimizing particle swarm optimizer with multiple adaptation layers is introduced. In the new algorithm, adaptation takes place on both particle and subswarm level. The new idea of using virtual parameter swarms which hold modifiable parameter configurations each is introduced. The algorithmic PSO parameters can be mutated by using, for instance, well-known techniques from the field of evolutionary algorithms, in order to allow fine-granular parameter adaptation to the problem at hand. The new algorithm is experimentally evaluated, and compared to a standard PSO and the Tribes algorithm. The experimental study shows that our new algorithm is highly competitive to previously suggested approaches. © 2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.infalg._desig

Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware - Bednara, Marcus; Danne, Klaus; Deppe, Markus; Oberschelp, Oliver; Slomka, Frank; Teich, Jürgen (EURASIP J APPL SIG P, 2003)
The implementation of large linear control systems requires a high amount of digital signal processing. Here, we show that reconfigurable hardware allows the design of fast yet flexible control systems. After discussing the basic concepts for the design and implementation of digital controllers for mechatronic systems, a new general and automated design flow starting from a system of differential equations to application-specific hardware implementation is presented. The advances of reconfigurable hardware as a target technology for linear controllers is discussed. In a case study, we compare the new hardware approach for implementing linear controllers with a software implementation.
UnivIS-Import:2015-03-09:Pub.2003.tech.IMMD.inform.design
Keywords: Digital linear control; Mechatronic systems; Reconfigurable hardware

Design and Implementation of Reconfigurable Multiple Bus on Chip (RMBoC) - Ahmadinia, Ali; Bobda, Christophe; Ding, Ji; Teich, Jürgen (2004)

Design and Optimization of Multi-Variant Automotive E/E Architecture Component Platforms - Graf, Sebastian (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2015)

Design Automation for Massively Parallel Processor Arrays: Transforming Regular Algorithms to Reconfigurable Hardware - Bednara, Marcus (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2004)

Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019 - Teich, Jürgen; Fummi, Franco (2019)

Design, Calibration, and Evaluation of Real-Time Waveform Matching on an FPGA-based Digitizer at 10 GS/s - Trautmann, Jens; Krüger, Paul; Becher, Andreas; Wildermann, Stefan; Teich, Jürgen (ACM Transactions on Reconfigurable Technology and Systems, 2023)
Digitizing side-channel signals at high sampling rates produces huge amounts of data, while side-channel analysis techniques only need those specific trace segments containing Cryptographic Operations (COs). For detecting these segments, waveform-matching techniques have been established comparing the signal with a template of the CO's characteristic pattern. Real-time waveform matching requires highly parallel implementations as achieved by hardware design but also reconfigurability as provided by FPGAs to adapt the matching hardware to a specific CO pattern. However, currently proposed designs process the samples from analog-to-digital converters sequentially and can only process low sampling rates due to the limited clock speed of FPGAs. In this paper, we present a parallel waveform-matching architecture capable of performing high-speed waveform matching on a high-end FPGA-based digitizer. We also present a workflow for calibrating the waveform-matching system to the specific pattern of the CO in the presence of hardware restrictions provided by the FPGA hardware. Our implementation enables waveform matching at 10 GS/s, offering a speedup of 50x compared to the fastest state-of-the-art implementation known to us. We demonstrate how to apply the technique for attacking the widespread XTS-AES algorithm using waveform matching to recover the encrypted tweak even in the presence of so-called systemic noise. <br
Keywords: side-channel analysis; waveform matching; interval matching; feature selection

Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach - Milbredt, Paul; Glaß, Michael; Lukasiewycz, Martin; Steininger, Andreas; Teich, Jürgen (Proc. of Design, Automation and Test in Europe (DATE), 2012)
FlexRay is likely to become the de-facto standard for upcoming in-vehicle communication. Efficient scheduling of the static and dynamic segment of the communication cycle in combination with the determination of more than 60 parameters that are part of the FlexRay protocol is a challenging task. This paper provides a formal analysis for interdependencies between the parameters as well as a scheduling approach for the static and dynamic segment. Experimental results give evidence of a significant interdependency between the subtasks such that a holistic scheduling approach becomes mandatory to provide high-quality FlexRay schedules. As a solution, this work introduces a complete functional FlexRay scheduling approach that takes parameter selection, allocation of messages to the static and dynamic segment, and concurrent scheduling into account. A real-world case study from the automotive domain gives evidence of efficiency and applicability of the proposed approach. © 2012 EDAA.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.design

Designing Heterogeneous ECU Networks via Compact Architecture Encoding and Hybrid Timing Analysis - Glaß, Michael; Lukasiewycz, Martin; Teich, Jürgen; Bordoloi, Unmesh; Chakraborty, Samarjit (Proc. 2009 ACM/EDAC/IEEE Design Automation Conference, 2009)
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies a number of design steps, i.e., resource allocation, process binding, message routing, scheduling, and parameter estimation for the processor and bus schedulers, and (ii) a hybrid scheme that allows different timing analysis techniques to be applied to different bus protocols (viz., CAN and FlexRay) within the same architecture in order to derive global performance estimates such as end-to-end delays of messages. The use of the compact encoding technique substantially reduces the underlying search space, and the hybrid timing analysis scheme allows the combination of known timing analysis techniques from the real-time systems domain. The proposed techniques were combined into a tool-chain and a real-life case study to illustrate their advantages. Copyright 2009 ACM.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.design
Keywords: Automotive; Design space exploration; Timing analysis

Designing Low Power Hardware / Software Systems - Glaß, Michael (Proceedings of the 1st Chinese-German Summer School, 2006)
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.design

Designing Partial and Dynamically Reconfigurable Applications on Xilinx Virtex-II FPGAs using HandelC - Ahmadinia, Ali; Bobda, Christophe; Blodget, Brandon; Hübner, Michael; Majer, Mateusz; Niyonkuru, Adronis (2004)

Design Methodology and Run-Time Management for Predictable Many-Core Systems - Wildermann, Stefan; Weichslgartner, Andreas; Teich, Jürgen (Proceedings of the 6th IEEE Workshop on Self-Organizing Real-Time Systems (SORT 2015), 2015)
Many-core systems provide a feasible means to build high-performance multi-application systems. They are increasingly exposed to dynamic changes due to varying and online modified application mixes, as well as unavailability of hardware resources due to thermal and power management or faults. Particularly, when applications with real-time requirements are executed, these constraints may become a problem. Here, self-adaptive mechanisms are a means to optimally and feasibly manage such a system at run-time. This paper gives an overview of a design flow for hybrid application mapping for predictable many-core systems. The idea behind this concept is to perform a complex timing analysis and verification of an application during design time and then exploit this information for RM of the system. We propose a novel optimization algorithm to perform RM, which statically calculates a set of application mappings that are guaranteed to fulfill real-time requirements while heuristically optimizing the system objectives. Here, minimization of the energy consumption is exemplary chosen. The algorithm achieves significantly better results than a state-of-the-art approach, especially for systems with a high resource congestion.
Keywords: design space exploration; Many-core systems; run-time management; timing predictability

Design of configurable processor arrays - Huber, M; Teich, Jürgen; Thiele, Lothar (Proc. IEEE Int. Symp. Circuits and Systems, 1990)

Design of Image Processing Embedded Systems Using Multidimensional Data Flow - Keinert, Joachim; Teich, Jürgen (Springer-Verlag, 2011)
UnivIS-Import:2015-04-15:Pub.2011.tech.IMMD.inform.design

Design of low power on-chip processor arrays - Lari, Vahid; Muddasani, Shravan; Boppu, Srinivas; Hannig, Frank; Teich, Jürgen (Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), 2012)
In this paper, we present an ultra low power design for a class of massively parallel architectures, called tightly-coupled processor arrays.Here, the key idea is to exploit the benefits of a decentralized resource management as inherent to invasive computing for power saving.We propose concepts and studying different architecture trade-offs for hierarchical power management by temporarily shutting down regions of processors through power gating. Moreover, a) overall system chip energy consumption, b) hardware cost, and c) timing overheads are compared for different sizes of power domains.Experimental results show that up to 70% of system energy consumption may be saved for selected characteristical algorithms and different resource utilizations. © 2012 IEEE.

Design Space Characterization for Architecture/Compiler Co-Exploration - Fischer, Dirk; Kastens, Uwe; Teich, Jürgen; Thies, Michael; Weper, Ralph (ACM SIG Proceedings International Conference on Compilers, Architectures and Synthesis for Embedded Systems, 2001)
UnivIS-Import:2015-04-16:Pub.2001.tech.IMMD.inform.design

Design Space Exploration for Automotive E/E Architecture Component Platforms - Graf, Sebastian; Glaß, Michael; Teich, Jürgen; Lauer, Christoph (Proc. of Euromicro Conference on Digital System Design (DSD), 2014)
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.design

Design Space Exploration for Layer-parallel Execution of Convolutional Neural Networks on CGRAs - Heidorn, Christian; Hannig, Frank; Teich, Jürgen (Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2020)
In this work, we systematically explore the design space of throughput, energy, and hardware costs for layer-parallel mappings of Convolutional Neural Networks (CNNs) onto coarse-grained reconfigurable arrays (CGRAs). We derive an analytical model that computes the required resources (processing elements) and buffer memory and thus hardware cost C to sustain a given throughput T as well as the resulting overall energy consumption E for inference. Further, we propose an efficient design space exploration (DSE) to determine the fronts of Pareto-optimal (T,E,C) solutions. This exploration helps to determine the limits of scalability of the presented tiled CGRA accelerator architectures in terms of throughput, the number of parallel layers that can be simultaneously processed, and memory requirements. Finally, we provide an evaluation of energy savings achievable on our architecture in comparison to implementations that execute sequentially a CNN layer-by-layer. In experiments, it is shown that layer-parallel processing is able to reduce energy consumption E by 3.6×, hardware cost C by 1.2×, and increase the achievable throughput T by 6.2× for MobileNet. <br

Design Space Exploration for Massively Parallel Processor Arrays - Hannig, Frank; Teich, Jürgen (Proc. of the Sixth International Conference on Parallel Computing Technologies (PaCT-2001), 2001)

Design Space Exploration of an Approximation-Based Fully Reliable TMR Alternative - Traiola, Marcello; Echavarria Gutiérrez, Jorge Alfonso; Bosio, Alberto; Teich, Jürgen; O'Connor, Ian (8th Prague Embedded Systems Workshop, 2020)

Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits - Traiola, Marcello; Echavarria Gutiérrez, Jorge Alfonso; Bosio, Alberto; Teich, Jürgen; O'Connor, Ian (Proceedings of the International Conference on Computer-Aided Design, ICCAD, 2021)

Design Space Exploration of Multi-output Logic Function Approximations - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Teich, Jürgen (Proceedings of the International Conference On Computer Aided Design, 2018)
Approximate Computing has emerged as a design paradigm that allows decreasing hardware costs by reducing the accuracy of the computation for applications that are robust against such errors. In Boolean logic approximation, the number of terms and literals of a logic function can be reduced by allowing to produce erroneous outputs for some input combinations. This paper proposes a novel methodology for the approximation of multi-output logic functions. Related work on multi-output logic approximation minimizes each output function separately. In this paper, we show that thereby a huge optimization potential is lost. As a remedy, our methodology considers the effect on all output functions when introducing errors thus exploiting the cross-function minimization potential. Moreover, our approach is integrated into a design space exploration technique to obtain not only a single solution but a Pareto-set of designs with different trade-offs between hardware costs (terms and literals) and error (number of minterms that have been falsified). Experimental results show our technique is very efficient in exploring Pareto-optimal fronts. For some benchmarks, the number of terms could be reduced from an accurate function implementation by up to 15% and literals by up to 19% with degrees of inaccuracy around 0.1% w.r.t. accurate designs. Moreover, we show that the Pareto-fronts obtained by our methodology dominate the results obtained when applying related work.<br
Keywords: Approximate Computing; Logic Simplification; Design Space Exploration

Design space exploration of reliable networked embedded systems - Streichert, Thilo; Glaß, Michael; Haubelt, Christian; Teich, Jürgen (Journal of Systems Architecture, 2007)
In this paper, a new methodology is presented for topology optimization of networked embedded systems as they occur in automotive and avionic systems as well as wireless sensor networks. By introducing a model which is (1) suitable for heterogeneous networks with different communication bandwidths, (2) modeling of routing restrictions, and (3) flexible binding of tasks onto processors, current design issues of networked embedded systems can be investigated. On the basis of this model, the presented methodology firstly allocates the required resources which can be communication links as well as computational nodes and secondly binds the functionality onto the nodes and the data dependencies onto the links such that no routing restrictions will be violated or capacities on communication links will be exceeded. Due to the often error-prone communication in networks, we allow for routing each data dependency over multiple routes in the networks. With this strategy, our methodology is able to increase the reliability of the entire system. This reliability analysis is based on Binary Decision Diagrams (BDDs) and is integrated in our multi-objective design space exploration. By applying Evolutionary Algorithms, we are able to consider multiple objectives simultaneously during the optimization process and allow for a subsequent unbiased decision making. An experimental evaluation as well as a demonstration of a case study from the field of automotive electronics will show the applicability of the presented approach. © 2007 Elsevier B.V. All rights reserved.
UnivIS-Import:2015-04-14:Pub.2007.tech.IMMD.inform.design
Keywords: Design space exploration; Network design; Reliability; Topology optimization

Design Space Exploration of Time, Energy, and Error Rate Trade-oﬀs for CNNs using Accuracy-Programmable Instruction Set Processors - Schuster, Armin; Heidorn, Christian; Brand, Marcel; Keszöcze, Oliver; Teich, Jürgen (Joint European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML PKDD 2021), 2021)
We proclaim the use of application-speciﬁc instruction set processors with programmable accuracy called Anytime Instruction Processors (AIPs) for Convolutional Neural Network (CNN) inference. For a ﬂoating-point operation, the number of correctly computed mantissa result bits can be freely adjusted, allowing for a ﬁne-grained trade-oﬀ analysis between accuracy, execution time and energy. We propose a Design Space Exploration (DSE) technique in which the accuracy of CNN computations is determined layer-by-layer. As one result, we show that reductions of up to 62% in energy consumption are achievable for a representative ResNet-18 benchmark in comparison to a solution where each layer is computed at full accuracy according to the IEEE 754 single precision ﬂoating-point format.<br

Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs - Weichslgartner, Andreas; Wildermann, Stefan; Götzfried, Johannes; Freiling, Felix; Glaß, Michael; Teich, Jürgen (In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2016)

Detection of Unseen Low-Contrast Signals Using Classic and Novel Model Observers - Xu, Yang; Schebesch, Frank; Ravikumar, Nishant; Maier, Andreas (Informatik aktuell, 2019)
Automatic task-based image quality assessment has been of importance in various clinical and research applications. In this paper, we propose a neural network model observer, a novel concept which has recently been investigated. It is trained and tested on simulated images with different contrast levels, with the aim of trying to distinguish images based on their quality/contrast. Our model shows promising properties that its output is sensitive to image contrast, and generalizes well to unseen low-contrast signals. We also compare the results of the proposed approach with those of a channelized hotelling observer (CHO), on the same simulated dataset.
CRIS-Team Scopus Importer:2019-05-14

Detector Defect Correction of Medical Images on Graphics Processors - Membarth, Richard; Hannig, Frank; Teich, Jürgen; Litz, Gerhard; Hornegger, Heinz (Proceedings of the SPIE: Medical Imaging 2011: Image Processing, 2011)
The ever increasing complexity and power dissipation of computer architectures in the last decade blazed the trail for more power efficient parallel architectures. Hence, such architectures like field-programmable gate arrays (FPGAs) and particular graphics cards attained great interest and are consequently adopted for parallel execution of many number crunching loop programs from fields like image processing or linear algebra. However, there is little effort to deploy barely computational, but memory intensive applications to graphics hardware. This paper considers a memory intensive detector defect correction pipeline for medical imaging with strict latency requirements. The image pipeline compensates for different effects caused by the detector during exposure of X-ray images and calculates parameters to control the subsequent dosage. So far, dedicated hardware setups with special processors like DSPs were used for such critical processing. We show that this is today feasible with commodity graphics hardware. Using CUDA as programming model, it is demonstrated that the detector defect correction pipeline consisting of more than ten algorithms is significantly accelerated and that a speedup of 20x can be achieved on NVIDIA's Quadro FX 5800 compared to our reference implementation. For deployment in a streaming application with steadily new incoming data, it is shown that the memory transfer overhead of successive images to the graphics card memory is reduced by 83% using double buffering. © 2011 Copyright Society of Photo-Optical Instrumentation Engineers (SPIE).
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.detect

Development of a multisensor array for localizing bats in space - Hochradel, Klaus; Hohler, Tino; Becher, Andreas; Wildermann, Stefan; Sutor, Alexander (Journal of Physics: Conference Series, 2018)
We present a novel multisensor array to track flight paths of bats in space. Our array is designed to be portable and, thus, field applicable. Eight microphones are employed to localize each echolocation call, whereas two cameras provide continuous information on the flight path between the calls. To reduce costs and, thus, make it available for low-budget research the array was developed from scratch including a novel acoustic signal recording and processing hardware. Our developed acoustic hardware is the first system to sample eight microphone channels synchronously at 1 MS/s/CH with 16 Bit resolution without the necessity of computers or laptops. All eight signals from the ultrasonic microphones are not only recorded but also processed in real time in the frequency as well as time domain to determine the existence of echolocation calls. Only relevant acoustic signal are recorded which enables long term deployments of the array. During the acoustic signal acquisition, the system records images of two infrared cameras at 12 Hz and, in addition, several environmental factors such as temperature, humidity and illumination. Recorded datasets can be associated with a global position and time-stamp through a GPS module and matched to the GPS coordinate system with a three-axis accelerometer. The overall system (microphones, cameras and sensors) was designed to be affordable, easy to use in the field on battery power and without the necessity of an additional laptop. Without cost optimization and only small quantity we reached a prize below 1000 EUR for a complete system.

Digitale Hardware/Software-Systeme: Spezifikation und Verifikation - Haubelt, Christian; Teich, Jürgen (Springer-Verlag, 2010)

Digitale Hardware/Software-Systeme: Synthese und Optimierung - Teich, Jürgen (Springer, 1997)

Digitale Hardware/Software-Systeme: Synthese und Optimierung - Teich, Jürgen; Haubelt, Christian (Springer, 2007)
UnivIS-Import:2015-04-15:Pub.2007.tech.IMMD.inform.digita

Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect - Schmid, Moritz; Hannig, Frank; Teich, Jürgen; Diefenbach, Ralf; Pettendorf, Ralf; Hornegger, Heinz (Proceedings of the Embedded World Conference, 2010)

Discrete Particle Swarm Optimization for TSP: Theoretical Results and Experimental Evaluations - Hoffmann, Matthias; Mühlenthaler, Moritz; Helwig, Sabine; Wanka, Rolf (Proc. International Conference on Adaptive and Intelligent Systems (ICAIS), 2011)
Particle swarm optimization (PSO) is a nature-inspired technique originally designed for solving continuous optimization problems. There already exist several approaches that use PSO also as basis for solving discrete optimization problems, in particular the Traveling Salesperson Problem (TSP). In this paper, (i) we present the first theoretical analysis of a discrete PSO algorithm for TSP which also provides insight into the convergence behavior of the swarm. In particular, we prove that the popular choice of using ``sequences of transpositions'' as the difference between tours tends to decrease the convergence rate. (ii) In the light of this observation, we present a new notion of difference between tours based on ``edge exchanges'' and a new method to combine differences by computing their ``centroid.'' This leads to a more PSO-like behavior of the algorithm and avoids the observed slow down effect. (iii) Then, we investigate implementations of our methods and compare them with previous implementations showing the competitiveness of our new approaches.
Keywords: Particle Swarm Optimisation; PSO; Discrete PSO; TSP

Distributed HW/SW-partitioning for embedded reconfigurable networks - Streichert, Thilo; Haubelt, Christian; Teich, Jürgen (Proceedings of DATE 2005, Munich, 2005)
In this paper, we propose a distributed online HW/SW-partitioning strategy for increasing fault tolerance in HW/SW-reconfigurable networked systems.

Distributed Resource Reservation in Massively Parallel Processor Arrays - Lari, Vahid; Hannig, Frank; Teich, Jürgen (Proc. of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011)
This paper proposes a methodology for applications to automatically claim linear arrays of processing elements within massively parallel processor arrays at run-time depending on the available degree of parallelism or dynamic computing requirements. Using this methodology, parallel programs running on individual processing elements gain the capability of autonomously managing the available processing resources in their neighborhood. We present different protocols and architectural support for gathering and transporting the result of a resource exploration for informing a configuration loader about the number and location of the claimed resources. Timing and data overhead cost of four different approaches are mathematically evaluated. In order to verify and compare these decentralized algorithms, a simulation platform has been developed to compare the data overhead and scalability of each approach for different sizes of processor arrays. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.distri

Distributed self-organizing bandwidth allocation for priority-based bus communication - Ziermann, Tobias; Wildermann, Stefan; Mühleis, Nina; Teich, Jürgen (Concurrency and Computation-Practice & Experience, 2012)
The raising complexity in distributed embedded systems makes it necessary that the communication of such systems organizes itself automatically. In this paper, we tackle the problem of sharing bandwidth on priority-based buses. Based on a game theoretic model, reinforcement learning algorithms are proposed that use simple local rules to establish bandwidth sharing. The algorithms require little computational effort and no additional communication. Extensive experiments show that the proposed algorithms establish the desired properties without global knowledge ortextita priori information. It is proven that communication nodes using these algorithms can co-exist with nodes using other scheduling techniques. Finally, we propose a procedure that helps to set the learning parameters according to the desired behavior. Copyright © 2011 John Wiley & Sons, Ltd.
Keywords: can; organic computing; reinforcement learning

Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs - Spieck, Jan; Wildermann, Stefan; Teich, Jürgen (3rd ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2021)

Domain-specific and Resource-aware Computing - Hannig, Frank (2017)

Domain-Specific Augmentations for High-Level Synthesis - Schmid, Moritz; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen; Bhadouria, Vivek Singh; Ghoshal, Dibyendu (Proc. of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2014)
High-Level Synthesis (HLS) has become a very popular instrument to facilitate rapid development of production-ready implementations for FPGAs. Ever increasing flexibility of the frameworks, however, demands a very high level of domain-specific knowledge from the designer. Examples for such knowledge in window-based image processing are median computation and border handling. Depending on the size of the considered window, writing the code to perform such operations may become overwhelming even at very high abstraction levels. To increase productivity and to make the underlying architecture accessible to non-experts, we propose to combine HLS with domain-specific augmentations. Specifically, we propose a new language extension in form of a reduction for sorting and median computation. Furthermore, we introduce a new high-level transformation to perform multiple kinds of border treatment automatically. Both augmentations may reduce the required amount of code lines considerably. The increase in productivity is analyzed by comparing the lines of code necessary to specify a median filter for HLS in PAULA for synthesis using PARO and in C++ for synthesis using a commercial HLS tool. © 2014 IEEE.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.domain

Domain-Specific Interface Generation From Dataflow Specifications - Eisenring, Michael; Teich, Jürgen (Proc. of Codes/CASHE'98, the 6th Int. Workshop on Hardware/Software Co-design, 1998)
In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are automatically inserted into the specification to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are refined according to given communication constraints (bus protocols, memory mapping, interrupts, DMA, etc.). An object-oriented approach is presented that enables an easy migration (retargeting) of typical communication primitives to other target architectures.
UnivIS-Import:2015-04-16:Pub.1998.tech.IMMD.inform.domain

Domain-Specific Processors: Systems, Architectures, Modeling and Simulation - Bhattacharyya, Shuvra S.; Deprettere, Ed; Teich, Jürgen (Marcel Dekker, 2003)
UnivIS-Import:2015-04-02:Pub.2003.tech.IMMD.inform.domain

Domain-Specific Reconfigurable MPSoC-Systems - Challenges and Trends - Dutta, Hritam; Hannig, Frank; Kissler, Dmitrij; Teich, Jürgen; et al. (Friday Workshop Reconfigurable Hardware, Design, Automation and Test in Europe, 2008)
UnivIS-Import:2017-12-18:Pub.2008.tech.IMMD.inform.domain

DPSK modulated wakeup mechanism for point-to-point networks with partial network support - Seyler, Jan; Rahimov, Shurat; Streichert, Thilo; Glaß, Michael; Teich, Jürgen (Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES), 2014)
The automotive community introduced Ethernet as a packet-switched point-to-point network. Possible fields of application are telematics, advanced driving assistance and a backbone. Currently, CAN, FlexRay and MOST are used to interconnect these applications. With Ethernet the bandwidth is rising but the networking requirements are still the same as for existing field buses. Consumer Ethernet does not provide a wakeup mechanism that is sufficient for automotive systems. As a solution, this paper introduces a novel DPSK based physical-layer mechanism which uses digital signals to identify partial networks and has an overall wakeup latency of less than 5 ms which is a reduction of 75 % for a five-hop network to the current state-of-the-art technology for automotive point-to-point networks. © 2014 IEEE.

DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs - Fickenscher, Jörg; Hannig, Frank; Teich, Jürgen (Proceedings of the 32nd International Conference on Architecture of Computing Systems (ARCS), 2019)

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks - Sommer, Jan; Özkan, Mehmet Akif; Keszöcze, Oliver; Teich, Jürgen (IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications, 2022)
The number of Digital Signal Processor (DSP) resources available in Field Programmable Gate Arrays (FPGAs) is often quite limited. Therefore, full utilization of available DSP resources for the computationally intensive parts of an algorithm is paramount for optimizing the non-functional properties of an implementation (i.e., performance, power, and area). The DSPs available in Xilinx devices implement large bit width operators (i.e. a 48-bit accumulator or a 18 x 27 multiplier). However, using such a DSP for low-precision quantized data (as is common in image processing or machine learning applications) leaves the DSP resources underutilized. As a remedy, a method has been proposed to pack and compute four 4-bit multiplications on a single DSP in a single clock cycle. This paper presents a generalization of this scheme to arbitrary bit widths and number of multiplications. We also demonstrate that the previously proposed approach leads to errors (Mean Absolute Error (MAE) = 0.37). Furthermore, we explain where these errors come from and how they can be corrected. On top, we introduce a novel approximate method called "Overpacking" which allows to squeeze even more multiplications into a single DSP at the cost of small errors (MAE = 0.47). Overpacking allows to squeeze six 4-bit multiplications into a single DSP compared to just four in the literature. Finally, we introduce an alternative method for packing multiple small-bit width additions into a single 48-bit accumulator for use in applications such as Spiking Neural Networks. <br
Keywords: dsp; fpga; approximation; approximate computing

DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks - Sabih, Muhammad; Hannig, Frank; Teich, Jürgen (Proceedings of the 2nd European Workshop on Machine Learning and Systems (EuroMLSys), 2022)
Filter pruning is one of the most effective ways to accelerate Convolutional Neural Networks (CNNs). Most of the existing works are focused on the static pruning of CNN filters. In dynamic pruning of CNN filters, existing works are based on the idea of switching between different branches of a CNN or exiting early based on the hardness of a sample. These approaches can reduce the average latency of inference, but they cannot reduce the longest-path latency of inference. In contrast, we present a novel approach of dynamic filter pruning that utilizes explainable AI along with early coarse prediction in the intermediate layers of a CNN. This coarse prediction is performed using a simple branch that is trained to perform top-k classification. The branch either predicts the output class with high confidence, in which case the rest of the computations are left out. Alternatively, the branch predicts the output class to be within a subset of possible output classes. After this coarse prediction, only those filters that are important for this subset of classes are then evaluated. The importances of filters for each output class are obtained using explainable AI. Using this concept of dynamic pruning, we are able not only to reduce the average latency of inference, but also the longest-path latency of inference. Our proposed architecture for dynamic pruning can be deployed on different hardware platform
Keywords: Explainable AI; Filter Pruning; CNN; Dynamic Pruning

Dynamically Reconfigurable Architectures - Becker, Jürgen; Teich, Jürgen; Athanas, Peter; Brebner, Gordon (2006)

Dynamically Reconfigurable Architectures - Bergmann, Neil; Platzner, Marco; Teich, Jürgen (EURASIP Journal on Embedded Systems, 2007)
UnivIS-Import:2015-03-09:Pub.2007.tech.IMMD.inform.dynami

Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications - Platzner, Marco; Teich, Jürgen; Wehn, Norbert (Springer, 2010)
Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems. Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems. © Springer Science+Business Media B.V. 2010.
UnivIS-Import:2015-04-02:Pub.2010.tech.IMMD.inform.dynami

Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures - Weichslgartner, Andreas; Wildermann, Stefan; Teich, Jürgen (Proc. Fifth ACM/IEEE International Symposium on Networks-on-Chip, 2011)
This paper presents a novel application-driven and resource-aware mapping methodology for tree-structured streaming applications onto NoCs. This includes strategies for mapping the source of streaming applications (seed point selection), as well as embedding strategies so that each process autonomously embeds its own succeeding tasks. The proposed embedding strategies only consider the local view of neighboring cells on the NoC which allows to significantly reduce computation and monitoring overhead. Our vision is that this approach facilitates self-organizing embedded systems that provide the flexibility and fault-tolerance required in future silicon technologies. The results provided in this paper show that our local and decentralized algorithms can compete with previously presented global and centralized algorithms. © 2011 ACM.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.dynami
Keywords: decentralized mapping; graph embedding; Networks-on-Chip

Dynamic Defragmentation of Reconfigurable Devices - Fekete, Sandor P.; Kamphans, Tom; Schweer, Nils; Tessars, Christopher; Van Der Veen, Jan C.; Angermeier, Josef; Koch, Dirk; Teich, Jürgen (ACM Transactions on Reconfigurable Technology and Systems, 2012)
We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs. Our method is based on dynamic relocation of module positions during runtime, with only very little reconfiguration overhead; the objective is to maximize the length of contiguous free space that is available for new modules. We describe a number of algorithmic aspects of good defragmentation, and present an optimization method based on tabu search. Experimental results indicate that we can improve the quality of module layout by roughly 50% over the static layout. Among other benefits, this improvement avoids unnecessary rejections of modules. © 2012 ACM.
UnivIS-Import:2015-03-09:Pub.2012.tech.IMMD.inform.dynami_1
Keywords: Complexity; Defragmentation; Dynamic reconfiguration; Hardware/software codesign; Local search; Physical sorting; Reconfigurable devices

Dynamic Piecewise Linear/Regular Algorithms - Hannig, Frank; Teich, Jürgen (Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004)
In this paper we present an extension of the class of piece-wise linear algorithms (PLAs) in order to model one type of dynamic data dependencies. This extension significantly increases the range of applications which can be parallelized and mapped to massively parallel processor arrays. For instance, a lot of computational intensive applications for video and image processing consist of nested loop programs with only few and simple run-time dependent conditionals. Furthermore, we outline in which case these extensions can directly used - with slight changes - within traditional mapping methodologies based on loop parallelization in the polytope model. Additionally, we outline future research directions in the case existing methods will be inefficient.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.dynami_5

Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-off Analysis - Bobda, Christophe; Danne, Klaus (Proc. Reconfigurable Architecture Workshop 2004, 2004)
This work explores various solutions to implement an application using runtime reconfigurable field programmable gate arrays (FPGA). The example is a mechatronic control system which has to adapt its behavior from time to time. Our model is a task-graph where every task is associated with an hardware module characterized by its required FPGA resource and its execution time. We propose various mappings of the tasks onto the FPGA. For the implementation of the tasks themselves the computation technique known as distributed arithmetic is used. We achieve numerous alternatives with different resource consumptions and execution times for every task. We estimate these characteristics and compare them to synthesis results. The received values are used to get the characteristics of the over-all system. The results show that the optimal mapping depends on the application timing constrains, on the complexity of the tasks as well as on the reconfiguration speed of the used FPGA1.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.dynami

Dynamic reconfiguration of FlexRay schedules for response time reduction in asynchronous fault-tolerant networks - Brendle, Robert; Streichert, Thilo; Koch, Dirk; Haubelt, Christian; Teich, Jürgen (Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), 2008)
In this paper, we present fault-tolerance strategies for implementing passive replication techniques in networked embedded systems based on TDMA-communication such as FlexRay busses. In particular, we assume that processes are replicated at different nodes for tolerating node failures. Hence, if one node fails another node can execute the process and requires the bandwidth for transmitting those messages created by the process over the bus medium. Two concepts are introduced to solve this problem: 1.) to replicate not only the processes but also the messages and to reserve the required bandwidth a priori at design time or 2.) to reconfigure the TDMA-schedule and assign the bandwidth dynamically to the nodes. Obviously, reserving bandwidth for each failure case might lead to a huge overhead and to long response times. Therefore, we provide different reconfiguration strategies for the recently developed FlexRay bus. Moreover, the timing behavior as well as the implementation overhead are evaluated with the help of an experimental setup consisting of five FlexRay nodes. © 2008 Springer-Verlag Berlin Heidelberg.

Dynamic Resource Management for Heterogeneous Many-Cores - Henkel, Jörg; Teich, Jürgen; Wildermann, Stefan; Amrouch, Hussam (Proceedings of International Conference On Computer Aided Design 2018, 2018)

Dynamic task binding for hardware/software reconfigurable networks - Streichert, Thilo; Strengert, Christian; Haubelt, Christian; Teich, Jürgen (In Proceedings of SBCCI 2006, 2006)
In this paper, a new methodology for tolerating link as well as node defects in self-adaptive reconfigurable networks will be presented. Currently, networked embedded systems need a certain level of redundancy for each node and link in order to tolerate defects and failures in a network. Due to monetary constraints as well as space and power limitations, the replication of each node and link is not an option in most embedded systems. Therefore, we will present a hardware/software partitioning algorithm for reconfigurable networks that optimizes the task binding onto resources at runtime such that node/link defects can be handled and data traffic on links between computational nodes will be minimized. This paper presents a new hardware/software partitioning algorithm, an experimental evaluation and for demonstrating the readability, an implementation on a network of FPGA-based boards. Copyright 2006 ACM.
Keywords: Fault-tolerance; Online hardware/software partitioning; Reconfigurable system

Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging - Membarth, Richard; Lupp, Jan-Hugo; Hannig, Frank; Teich, Jürgen; Körner, Mario; Eckert, Wieland (Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS), 2012)
For medical imaging applications, a timely execution of tasks is essential. Hence, running multiple applications on the same system, scheduling with the capability of task preemption and prioritization becomes mandatory. Using GPUs as accelerators in this domain, imposes new challenges since GPU's common FIFO scheduling does not support task prioritization and preemption. As a remedy, this paper investigates the employment of resource management and scheduling techniques for applications from the medical domain for GPU accelerators. A scheduler supporting both, priority-based and LDF scheduling is added to the system such that high-priority tasks can interrupt tasks already enqueued for execution. The scheduler is capable of utilizing multiple GPUs in a system to minimize the average response time of applications. Moreover, it supports simultaneous execution of multiple tasks to hide data transfers latencies. We show that the scheduler interrupts scheduled and already enqueued applications to fulfill the timing requirements of high-priority dynamic tasks. © 2012 Springer-Verlag.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.dynami
Keywords: CUDA; Dynamic task-scheduling; GPU; Medical imaging; Resource management

DynOAA - Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems - Ziermann, Tobias; Salcic, Zoran; Teich, Jürgen (Proc. of DATE, 2011)
CAN bus systems are used in many industrial control applications, particularly automotive. Due to growing system and functional requirements, the low capacity of the CAN bus and usually strict conditions under which it is used in realtime applications, applicability of CAN bus is severely limited. The paper presents an approach for achieving high utilization and breathes new life to CAN bus based systems by proposing a dynamic offset adaptation algorithm for scheduling messages and improving message response times without any changes to a standard CAN bus. This simple algorithm, which runs on all nodes of the system, results in excellent average response times at all loads and makes the approach particularly attractive for soft real-time systems. We demonstrate the performance improvement of the proposed approach by comparisons to other approaches and introduce a new performance measure in the form of a rating function. © 2011 EDAA.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.dynoaa
Keywords: CAN; Controller Area Network; distributed embedded systems; response time; WCRT

DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices - Ahmadinia, Ali; Bobda, Christophe; Fekete, Sandor P.; Majer, Mateusz; Teich, Jürgen; Van Der Veen, Jan C. (Proceedings of the International Conference on Field-Programmable Logic and Applications, 2005)
A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at run-time is presented. Based on the network on chip (NoC) infrastructure, we developed a dynamic communication infrastructure as well as routing methodologies capable to handle routing in a NoC with obstacles created by dynamically placed components. We prove the unrestricted reachability of components and pins, the deadlock-freeness and we finally show the feasibility of our approach by means on real life example applications. © 2005 IEEE.
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.dynoca

Echtzeitanalyse Ethernet-basierter E/E-Architekturen im Automobil - Reimann, Felix; Kern, Andreas; Haubelt, Christian; Streichert, Thilo; Teich, Jürgen (GMM-Fachbericht - Automotive meets Electronics, 2010)
UnivIS-Import:2019-08-15:Pub.2010.tech.IMMD.inform.echtze

Efficiency in ILP Processing by Using Orthogonality - Brand, Marcel; Hannig, Frank; Tanase, Alexandru-Petru; Teich, Jürgen (2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2017)
For the next generations of Processor-Arrays-on-Chip(e. g., coarse-grained reconfigurable or programmable arrays)— including more than 100s to 1000s of processing elements—it is very important to keep the on-chip configuration/instruction memories as small as possible. Hence, compilers must take into account the scarceness of available instruction memory and create the code as compact as possible [1]. However, Very Long Instruction Word (VLIW) processors have thewell-known problem that compilers typically produce lengthycodes. A lot of unnecessary code is produced due to unused Functional Units (FUs) or repeating operations for single FUs in instruction sequences. Techniques like software pipeliningcan be used to improve the utilization of the FUs, yet with therisk of code explosion [2] due to the overlapped scheduling of multiple loop iterations or other control flow statements. This is, where our proposed Orthogonal Instruction Processing (OIP) architecture (see Fig. 1) shows benefits in reducing the code size of compute-intensive loop programs. The idea is, contrary to lightweight VLIW processors used in arrays like Tightly Coupled Processor Arrays (TCPAs) [4], to equip each FU with its own instruction memory, branch unit, andprogram counter, but still let the FUs share the register files as well as input and output signals. This enables a processorto orthogonally execute a loop program. Each FU can execute its own sub-program while exchanging data over the register files. The branch unit and its instruction format have to beslightly changed by introducing a counter to each instructionthat determines how often the instruction is repeated until the specified branch is executed. This enables repeating instructions without repeating them in the code. Those kind of processors have to be carefully programmed, e. g., to not run into data dependency problems while optimizing throughput. For solving this resource-constrained modulo scheduling problem, we use techniques based on mixed integer linear programming [5], [3]. Obviously, the modifications of the processor produce architectural overhead in form of additional branch units and an increase of instruction memory compared to the lightweight VLIW processors. Thus, we created an analytical model of both the lightweight VLIW processor and our proposed architecture to analyze the overhead. The model gives an upper bound of the hardware costs and the memory consumption according to [7]. We examined the HW costs of a lightweight VLIW processor with different instruction memory lengths mVLIW and compared them to our OIP processor with varying instruction ratios IR and thus instruction memory lengths mOIP of each FU’s instruction memory. In the examination, we covered processors containingten FUs and averaged the HW costs over the instruction ratio. Figure 2 shows that the overhead is negligible as soon as we are able to reduce program sizes to 50 % (i. e., IR = 2), whichis usually achieved by our compile

Efficient Application of Tensor Core Units for Convolving Images - Groth, Stefan; Teich, Jürgen; Hannig, Frank (Proceedings of the 24th International Workshop on Software and Compilers for Embedded Systems, 2021)
Keywords: Tensor core unit; Convolution; Image processing; Parallel algorithm

Efficient approximately-timed performance modeling for architectural exploration of MPSoCs - Streubühr, Martin; Gladigau, Jens; Haubelt, Christian; Teich, Jürgen (Forum on specification and Design Languages 2009, 2009)
In this paper, we propose an efficient modeling approach that permits simulation-based performance evaluation of MPSoCs at Electronic System Level (ESL). The approach is based on a SystemC simulation framework and allows for evaluating timing effects from resource contention when mapping applications to MPSoC platforms. The abstraction level used for modeling timing corresponds to approximately-timed transaction level models. This allows for an accurate performance modeling, including temporal effects from preemptive processor scheduling and bus arbitration. However, in contrast to standard SystemC TLM, application mapping and platform models are configurable and, thus, enable design space exploration at ESL. We use a Motion-JPEG decoder application to illustrate and assess the benefits of the proposed approach.

Efficient approximately-timed performance modeling for architectural exploration of MPSoCs - Streubühr, Martin; Gladigau, Jens; Haubelt, Christian; Teich, Jürgen (2010)
In this chapter, we propose an efficient modeling approach that permits simulation-based performance evaluation of MPSoCs at Electronic System Level (ESL). The approach is based on a SystemC simulation framework and allows for evaluating timing effects from resource contention when mapping applications to MPSoC platforms. The abstraction level used for modeling timing corresponds to approximately-timed communication in transaction level models. This allows for an accurate performance modeling, including temporal effects from preemptive processor scheduling and bus arbitration. However, in contrast to standard OSCI TLM, application mapping and platform models are configurable and, thus, enable design space exploration at ESL. A Motion-JPEG decoder application is used to illustrate and assess the benefits of our approach. © 2010 Springer Science+Business Media B.V.
Keywords: Electronic system level; Performance modeling; Simulation; SystemC

Efficient Architecture/Compiler Co-Exploration for ASIPs - Fischer, Dirk; Teich, Jürgen; Thies, M.; Weper, R. (ACM SIG Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, 2002)
In this paper, we present an efficient exploration algorithm for architecture/compiler co-designs of application-specific instruction-set processors. The huge design space is spanned by processor architecture parameters as well as different compiler optimization strategies. The objective space is multi-dimensional including conflicting objectives such as hardware cost, execution time and code size. The goal of the presented exploration algorithm is to determine the set of Pareto-optimal designs and compiler settings for a given benchmark program. In a case study, while exploring Pareto-optimal designs for a given DSP benchmark program, we show that for a realistic architecture family, the huge search space may be reduced dramatically using proper techniques to prune search spaces that may not contain Pareto-optimal solutions. Finally, we analyse and present solutions on what is the best architecture for a mixture of benchmark programs, i.e., what are the best architecture/compiler co-designs to execute the DSPstone benchmark. Copyright 2002 ACM.
UnivIS-Import:2015-04-16:Pub.2002.tech.IMMD.inform.effici
Keywords: Architecture/compiler codesign; ASIP; Multiobjective design space exploration; Retargetable compilation

Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Potwigin, Eduard; Teich, Jürgen (IEEE Embedded Systems Letters, 2017)
In this paper, we present a novel methodology to calculate the Arithmetic Error Rate (AER) for deterministic approximate adder architectures where the calculation of each output bit is restricted to a subset of the input bits, denoted as visibilities. Such architectures have been widely proposed in the literature and are, e.g., obtained when splitting the carry chain in a carry-propagate adder into partitions each computed by a separate parallel adder, or when removing carry-lookahead operators in a parallel prefix adder. Our contribution is a unified calculus for determining the arithmetic error rate for (a) such deterministic approximate adder architectures making use of visibilities and (b) the general case of arbitrarily (also non-uniformly) distributed input bit
Keywords: Approximate Adders; Arithmetic Error Rate; Approximate Computing

Efficient Computation of Probabilistic Dominance in Multi-objective Optimization - Khosravi, Faramarz; Raß, Alexander; Teich, Jürgen (ACM Transactions on Evolutionary Learning and Optimization, 2021)

Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays - Dutta, Hritam; Hannig, Frank; Ruckdeschel, Holger; Teich, Jürgen (Journal of Systems Architecture, 2007)
Processor array architectures are optimal platforms for computationally intensive applications. Such architectures are characterized by hierarchies of parallelism and memory structures, i.e. processor arrays apart from different levels of cache have a large number of processing elements (PE) where each PE can further contain sub-word parallelism. In order to handle large scale problems, balance local memory requirements with I/O-bandwidth, and use different hierarchies of parallelism and memory, one needs a sophisticated transformation called hierarchical partitioning. Innately the applications are data flow dominant and have almost no control flow, but the application of hierarchical partitioning techniques has the disadvantage of a more complex control flow. In a previous paper, the authors presented first time a methodology for the automated control path synthesis for the mapping of partitioned algorithms onto processor arrays. However, the control path contained complex multiplication and division operators. In this paper, we propose a significant extension to the methodology which reduces the hardware cost of the global controller and memory address generators by avoiding these costly operations. © 2006 Elsevier B.V. All rights reserved.
UnivIS-Import:2015-03-09:Pub.2007.tech.IMMD.inform.effici

Efficient Deep Neural Network Acceleration through FPGA-based Batch Processing - Posewsky, Thorbjörn; Ziener, Daniel (Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2016)
Deep neural networks are an extremely successful and widely used technique for various pattern recognition and machine learning tasks. Due to power and resource constraints, these computationally intensive networks are difficult to implement in embedded systems. Yet, the number of applications that can benefit from the mentioned possibilities is rapidly rising. In this paper, we propose a novel architecture for processing previously learned and arbitrary deep neural networks on FPGA-based SoCs that is able to overcome these limitations. A key contribution of our approach, which we refer to as batch processing, achieves a mitigation of required weight matrix transfers from external memory by reusing weights across multiple input samples. This technique combined with a sophisticated pipelining and the usage of high performance interfaces accelerates the data processing compared to existing approaches on the same FPGA device by one order of magnitude. Furthermore, we achieve a comparable data throughput as a fully featured x86-based system at only a fraction of its energy consumption.

Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers - Heidorn, Christian; Hannig, Frank; Riedelbauch, Dominik; Strohmeyer, Christoph; Teich, Jürgen (10th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS), 2024)
This paper proposes an approach for efficiently deploying neural network (NN) models on highly resource-constrained microcontroller architectures, particularly AURIX TC3xx microcontrollers. Here, compression and optimization techniques of the NN model are required to reduce execution time while maintaining accuracy on the target microcontroller. Furthermore, especially on AURIX TriCores that are frequently used in the automotive domain, there is a lack of support for automatic conversion and deployment of pretrained NN models. In this work, we present an approach that fills this gap, enabling the conversion and deployment of so-called thermal neural networks on AURIX TC3xx microcontrollers for the first time. Experimental results on three different NN types show that, when pruning of convolutional neural networks is applied, we can achieve a speedup of 2.7× compared to state-of-the-art thermal neural networks.<br
Keywords: AURIX TriCore; Neural Networks; Thermal Monitoring

Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays - Kissler, Dmitrij; Hannig, Frank; Teich, Jürgen (Journal of Low Power Electronics, 2011)
The presented evaluation framework allows extremely fast but still accurate power, area, and latency characterization of different design alternatives in a multidimensional design space of highly parameterized coarse-grained reconfigurable processor arrays. For the first time, we propose to use a relational database system, managing table-based, probabilistic macro-models, constructed with the help of a new non-uniform parameter sampling technique for the average power estimation of corresponding processor arrays on the architectural level. This leads to power estimation speeds in the milliseconds range within 10% estimation error compared to a state-of-the-art commercial gate-level post-layout power estimator. Furthermore, our approach fully accounts for such important power reduction techniques, like clock gating and operand isolation, which are commonly ignored otherwise. The feasibility and accuracy were tested in several case study implementations in a commercial 90 nm standard cell library. Experimental results show a superior scalability of the proposed technique: heterogeneous 100-core coarse-grained processor array with ≈0.5 *0 10 6 logic gates circuit complexity, implementing a signal processing algorithm, can be analyzed for power and area within less than a minute on a standard consumer PC. Since currently there exists no published architecture-level power/area estimation framework for coarse-grained, software-programmable architectures, our work tries to address this shortcoming. Copyright © 2011 American Scientific Publishers All rights reserved.
UnivIS-Import:2015-04-14:Pub.2011.tech.IMMD.inform.effici_2
Keywords: Architectural-level power analysis; Coarse-grained reconfigurable architectures (CGRA); Design space exploration

Efficient event-driven simulation of parallel processor architectures - Kupriyanov, Olexiy; Kissler, Dmitrij; Hannig, Frank; Teich, Jürgen (Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2007)
In this paper we present a new approach for generating high-speed optimized event-driven instruction set level simulators for adaptive massively parallel processor architectures. The simulator generator is part of a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The generation of high-speed cycle-accurate simulators is of utmost importance here, because they are directly used both for parallel processor architecture debugging and evaluation purposes, as well as during time-consuming architecture/compiler co-exploration. We developed a modeling environment which automatically generates a C++ simulation model either from a graphical input or directly from an XML-based architecture description. Here, we focus on the underlying event-driven simulation model and present our modeling environment, in particular the features of the graphical parallel processor architecture editor and the automatic instruction set level simulator generator. Finally, in a case-study, we demonstrate the pertinence of our approach by simulating different processor arrays. The superior performance of the generated simulators compared to existing simulators and simulator generation approaches is shown.
Keywords: Embedded tools; Modeling; Processor arrays; Simulation

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks - Sommer, Jan; Özkan, Mehmet Akif; Keszöcze, Oliver; Teich, Jürgen (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022)
Spiking neural networks (SNNs) compute in an event-based manner to achieve a more efficient computation than standard neural networks. In SNNs, neuronal outputs are not encoded as real-valued activations but as sequences of binary spikes. The motivation of using SNNs over conventional neural networks is rooted in the special computational aspects of spike-based processing, especially the high degree of sparsity of spikes. Well-established implementations of convolutional neural networks (CNNs) feature large spatial arrays of processing elements (PEs) that remain highly underutilized in the face of activation sparsity. We propose a novel architecture optimized for the processing of convolutional SNNs (CSNNs) featuring a high degree of sparsity. The proposed architecture consists of an array of PEs of the size of the kernel of a convolution and an intelligent spike queue that provides a high PE utilization. A constant flow of spikes is ensured by compressing the feature maps into queues that can then be processed spike-by-spike. This compression is performed at run-time, leading to a self-timed schedule. This allows the processing time to scale with the number of spikes. Also, a novel memory organization scheme is introduced to efficiently store and retrieve the membrane potentials of the individual neurons using multiple small parallel on-chip RAMs. Each RAM is hardwired to its PE, reducing switching circuitry. We implemented the proposed architecture on an FPGA and achieved a significant speedup compared to previously proposed SNN implementations ( 10 times) while needing less hardware resources and maintaining a higher energy efficiency ( 15 times
Keywords: Event-based processing; field-programmable gate array (FPGA); hardware acceleration; spiking convolutional neural networks (SNNs)

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks - Sommer, Jan; Özkan, Mehmet Akif; Keszöcze, Oliver; Teich, Jürgen (International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2022)
Spiking neural networks (SNNs) compute in an event-based manner to achieve a more efficient computation than standard neural networks. In SNNs, neuronal outputs are not encoded as real-valued activations but as sequences of binary spikes. The motivation of using SNNs over conventional neural networks is rooted in the special computational aspects of spike-based processing, especially the high degree of sparsity of spikes. Well-established implementations of convolutional neural networks (CNNs) feature large spatial arrays of processing elements (PEs) that remain highly underutilized in the face of activation sparsity. We propose a novel architecture optimized for the processing of convolutional SNNs (CSNNs) featuring a high degree of sparsity. The proposed architecture consists of an array of PEs of the size of the kernel of a convolution and an intelligent spike queue that provides a high PE utilization. A constant flow of spikes is ensured by compressing the feature maps into queues that can then be processed spike-by-spike. This compression is performed at run-time, leading to a self-timed schedule. This allows the processing time to scale with the number of spikes. Also, a novel memory organization scheme is introduced to efficiently store and retrieve the membrane potentials of the individual neurons using multiple small parallel on-chip RAMs. Each RAM is hardwired to its PE, reducing switching circuitry. We implemented the proposed architecture on an FPGA and achieved a significant speedup compared to previously proposed SNN implementations ( 10 times) while needing less hardware resources and maintaining a higher energy efficiency ( 15 times
Keywords: Event-based processing; field-programmable gate array (FPGA); hardware acceleration; spiking convolutional neural networks (SNNs)

Efficient hardware checkpointing: Concepts, overhead analysis, and implementation - Koch, Dirk; Haubelt, Christian; Teich, Jürgen (Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2007), 2007)
Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is an effective methodology to cope with faults. In this paper, we systematically extend the concept of checkpointing known from software systems to hardware tasks running on reconfigurable devices. We will classify different mechanisms for hardware checkpointing and present formulas for estimating the hardware overhead. Moreover, we will reveal a tool that takes over the burden of modifying hardware modules for checkpointing. Post-synthesis results of applying our methodology to different hardware accelerators will be presented and the results will be compared with the theoretical estimations. Copyright 2007 ACM.
Keywords: Checkpointing; State access

Efficient high-level modeling in the networking domain - Zebelein, Christian; Falk, Joachim; Haubelt, Christian; Teich, Jürgen; Dorsch, Rainer (Proceedings of Design, Automation and Test in Europe (DATE 2010), 2010)
Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs for complex systems is still a challenging task. In the context of network controller design, modeling complexity has two major sources: (1) the functionality to handle a single connection, and (2) the number of connections to be handled in parallel. In this paper, we will propose an efficient actor-oriented modeling approach for complex systems by (1) integrating hierarchical FSMs into dynamic dataflow models, and (2) providing new channel types to allow concurrent processing of multiple connections. We will show the applicability of our proposed modeling approach to real-world system designs by presenting results from modeling and simulating a network controller for the Parallel Sysplex architecture used in IBM System z mainframes. © 2010 EDAA.

Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System - Bobda, Christophe; Linarth, Andre Guilherme; et al. (Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2003), 2003)
We present a new implementation of the singular value decomposition (SVD) on a reconfigurable system made upon a Pentium processor and a FPGA-board plugged on a PCI slot of the PC. A maximum performance of the SVO is obtained by an efficient distribution of the data and the computation across the FPGA resource. Using the reconfiguration capability of the FPGA help us implement many operators on the same device. © Springer-Verlag Berlin Heidelberg 2003.
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.effici

Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays - Heidorn, Christian; Witterauf, Michael; Hannig, Frank; Teich, Jürgen (Journal of Computers, 2019)

Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors - Membarth, Richard; Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of the 9th International Workshop on Systems, Architectures,Modeling, and Simulation (SAMOS), 2009)
In the last decade, there has been a dramatic growth in research and development of massively parallel commodity graphics hardware both in academia and industry. Graphics card architectures provide an optimal platform for parallel execution of many number crunching loop programs from fields like image processing, linear algebra, etc. However, it is hard to efficiently map such algorithms to the graphics hardware even with detailed insight into the architecture. This paper presents a multiresolution image processing algorithm and shows the efficient mapping of this type of algorithms to the graphics hardware. Furthermore, the impact of execution configuration is illustrated and a method is proposed to determine the best configuration offline in order to use it at run-time. Using CUDA as programming model, it is demonstrated that the image processing algorithm is significantly accelerated and that a speedup of up to 33x can be achieved on NVIDIA's Tesla C870 compared to a parallelized implementation on a Xeon Quad Core. © 2009 Springer Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.effici_0

Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards - Membarth, Richard; Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Transactions on High-Performance Embedded Architectures and Compilers V, 2019)
UnivIS-Import:2015-04-20:Pub.2011.tech.IMMD.inform.effici

Efficient Oblivious Parallel Sorting on the MasPar MP-1 - Brockmann, Klaus; Wanka, Rolf (Proc of 30th Hawaii International Conference on System Sciences (HICSS), 1997)

Efficient One-Pass Synthesis for Digital Microfluidic Biochips - Mohammadzadeh, Naser; Wille, Robert; Keszöcze, Oliver (ACM Transactions on Design Automation of Electronic Systems, 2021)

Efficient Parallel Reduction on GPUs with Hipacc - Qiao, Bo; Reiche, Oliver; Özkan, Mehmet Akif; Teich, Jürgen; Hannig, Frank (Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2020)
Hipacc is a domain-specific language for ease of programming image processing applications on hardware accelerators such as GPUs. It relieves the burden of manually porting algorithms to hardware for developers with the help of domain- and architecture-specific knowledge. One fundamental operation in image processing is reduction. Global reduction operators are the building blocks of many widely used algorithms, including image normalization, similarity estimation, etc. This paper presents an efficient approach to perform parallel reductions on GPUs with Hipacc. Our proposed approach benefits from the continuous effort of performance and programmability improvement by hardware vendors, for example, by utilizing the latest low-level primitives from Nvidia. Results show our approach achieves a speedup of up to 3.43 over an existing Hipacc implementation with traditional optimization methods, and a speedup of up to 9.02 over an implementation using the Thrust library from Nvidia.
Keywords: Domain-Specific Languages; Parallel Reduction; GPUs

Efficient reconfigurable on-chip buses for fpgas - Haubelt, Christian; Koch, Dirk; Teich, Jürgen (Proceedings 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), 2008)
This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads. A test system will demonstrate a transfer rate of 800 MB/s while providing an extreme high placement flexibility. © 2008 IEEE.

Efficient Representation and Simulation of Model-Based Designs in SystemC - Falk, Joachim; Haubelt, Christian; Teich, Jürgen (Proceedings FDL'06, Forum on Design Languages 2006, 2006)

Efficient symbolic multi-objective design space exploration - Lukasiewycz, Martin; Glaß, Michael; Haubelt, Christian; Teich, Jürgen (2008 Asia and South Pacific Design Automation Conference, ASP-DAC, 2008)
Nowadays many design space exploration tools are based on Multi-Objective Evolutionary Algorithms (MOEAs). Beside the advantages of MOEAs, there is one important drawback as MOEAs might fail in design spaces containing only a few feasible solutions or as they are often afflicted with premature convergence, i.e., the same design points are revisited again and again. Exact methods, especially Pseudo Boolean solvers (PB solvers) seem to be a solution. However, as typical design spaces are multi-objective, there is a need for multi-objective PB solvers. In this paper, we will formalize the problem of design space exploration as multi-objective 0-1 ILP. We will propose (1) a heuristic approach based on PB solvers and (2) a complete multi-objective PB solver based on a backtracking algorithm that incorporates the non-dominance relation from multi-objective optimization and is restricted to linear objective functions. First results from applying our novel multi-objective PB solver to synthetic problems will show its effectiveness in small sized design spaces as well as in large design spaces only containing a few feasible solutions. For non-linear and large problems, the proposed heuristic approach is outperforming common MOEA approaches. Finally, a real world example from the automotive area will emphasize the efficiency of the proposed algorithms. ©2008 IEEE.

Efficient Symbolic Routing Encoding for In-vehicle Network Optimization - Smirnov, Fedor; Pourmohseni, Behnaz; Glaß, Michael; Teich, Jürgen (Smart Cities, Green Technologies and Intelligent Transport Systems, 2021)

Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation - Pradhan, Chetana; Letras, Martin; Teich, Jürgen (ACM Transactions on Embedded Computing Systems, 2023)
This paper proposes a novel approach for the generation of memory-efficient table-based function approxima- tion circuits for edge devices in general, and FPGAs in particular. Given a function f(x) to be approximated in a given interval [X0,X0+a) and a maximum approximation error Ea, the goal is to determine a function table implementation with a minimized memory footprint, i.e., number of entries that need to be stored. Rather than state-of-the-art work performing an equidistant sampling of the given interval by so-called breakpoints and using linear interpolation between two adjacent breakpoints to determine f(x) at the maximum error bound, we propose and compare three algorithms for splitting the given interval into sub-intervals to reduce the required memory footprint drastically based on the observation that in sub-intervals of low gradient, a coarser sampling grid may be assumed while guaranteeing the maximum interpolation error bound Ea. Experiments on elementary mathematical functions show that a large fraction in memory footprint may be saved. Second, a hardware architecture implementing the sub-interval selection, breakpoint lookup and interpolation at a latency of just 9 clock cycles is introduced. Third, for each generated circuit design, BRAMs are automatically instantiated rather than synthesizing the reduced footprint function table using LUT primitives providing an additional degree of resource efficiency. The approach presented here for FPGAs can equally be applied to other circuit technologies for fast and, at the same time, memory-optimized function approximation at the edge.<br
Keywords: FPGA; Approximate Computing; Function Approximation; BRAM

Efficient Task Spawning for Shared Memory and Message Passing in Many-core Architectures - Zaib, Aurang; Heisswolf, Jan; Weichslgartner, Andreas; Wild, Thomas; Teich, Jürgen; Becker, Jürgen; Herkersdorf, Andreas (Journal of Systems Architecture, 2017)

Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures - Aliee, Hananeh; Khosravi, Faramarz; Teich, Jürgen (The 49th IEEE/IFIP International Conference on Dependable Systems and Networks, 2019)

Eine Aktor-Orientierte Methodik zur Power-Modellierung auf Systemebene - Rosales, Rafael; Klie, Torsten; Glock, Stefan; Xu, Yang; Wang, Bo; Hasholzner, Ralph; Teich, Jürgen; Weigel, Robert (Design & Elektronik, 2012)

Electromagnetic Compatibility (EMC) of CAN+ - Ziermann, Tobias; Teich, Jürgen (GMM-Fachbericht - Automotive meets Electronics, 2010)
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.electr

Electronic System-Level Synthesis Methodologies - Gerstlauer, Andreas; Haubelt, Christian; Pimentel, Andy; Stefanov, Todor; Gajski, Daniel; Teich, Jürgen (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009)
With ever-increasing system complexities, all major semiconductor roadmaps have identified the need for moving to higher levels of abstraction in order to increase productivity in electronic system design. Most recently, many approaches and tools that claim to realize and support a design process at the so-called electronic system level (ESL) have emerged. However, faced with the vast complexity challenges, in most cases at best, only partial solutions are available. In this paper, we develop and propose a novel classification for ESL synthesis tools, and we will present six different academic approaches in this context. Based on these observations, we can identify such common principles and needs as they are leading toward and are ultimately required for a true ESL synthesis solution, covering the whole design process from specification to implementation for complete systems across hardware and software boundaries. © 2006 IEEE.
UnivIS-Import:2015-04-14:Pub.2009.tech.IMMD.inform.electr
Keywords: Electronic system level (ESL); Methodology; Synthesis.

Embedded GPUs in Future Automated Cars - Fickenscher, Jörg; Hannig, Frank; Bouzouraa, Mohammed Essayed; Teich, Jürgen (Design, Automation and Test in Europe (DATE), 2018)

Embedded Processor Design Challenges - Deprettere, Ed; Teich, Jürgen; Vassiliadis, S. (Embedded Processor Design Challenges, 2002)
UnivIS-Import:2015-04-20:Pub.2002.tech.IMMD.inform.1

Embedded System Design using the SPI Workbench - Cieslok, Frank; Ernst, Rolf; Jersak, Marek; Richter, Kai; Strehl, Karsten; Teich, Jürgen; Thiele, Lothar; Wolf, Fabian; Ziegenbein, Dirk (Proc. FDL'00, 2000)
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.embedd

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability* - Bosio, Alberto; O'Connor, Ian; Traiola, Marcello; Echavarria Gutiérrez, Jorge Alfonso; Teich, Jürgen; Abdullah Hanif, Muhammad; Shafique, Muhammad; Hamdioui, Said; Deveautour, Bastien; Girard, Patrick; Virazel, Arnaud; Bertels, Koen (Proceedings of the 26th IEEE European Test Symposium (ETS), 2021)

End-to-End Power Estimation for Heterogeneous Cellular LTE SoCs in Early Design Phases - Wang, Bo; Xu, Yang; Rosales, Rafael; Hasholzner, Ralph; Glaß, Michael; Teich, Jürgen (Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014)

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration - Becher, Andreas; Bauer, Florian; Ziener, Daniel; Teich, Jürgen (Proceedings of the Conference on Field-Programmable Logic and Applications (FPL 2014), 2014)
In this paper, we propose an approach for energy-aware FPGA-based query acceleration for databases on embedded devices. After the analysis of an incoming query, a query-specific hardware accelerator is generated on-the-fly and loaded on the FPGA for subsequent query execution using partial dynamic reconfiguration. For each SQL query operation, a pre-synthesized partial bitstream implementation exists in a module library. This library includes modules for all major SQL operations like restrictions, aggregations, as well as more complex operations such as join and sort. The implementation of this flexible FPGA-based query accelerator approach on the embedded low-energy system-on-chip (SoC) platform Xilinx Zynq shows SQL query processing speeds comparable to high-end database servers, however, at a much lower energy consumption. Indeed, provided experimental results give evidence that the proposed architecture may reduce the amount of consumed energy to just 5% of the energy needed of an in-memory database system running on an x86-based server at equal throughput for respective benchmarks.

Energy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression - Deutel, Mark; Woller, Philipp; Mutschler, Christopher; Teich, Jürgen (MBMV 2023; 26th Workshop, 2023)
Large Deep Neural Networks (DNNs) are the backbone of today's artificial intelligence due to their ability to make accurate predictions when trained on large data sets. With advancing technologies such as the Internet of Things, interpreting large amounts of data generated by sensors is becoming an increasingly important task. However, in many applications, not only the predictive performance but also the energy consumption of deep learning models is of great interest. This paper investigates the efficient deployment of deep learning models on resource-constrained microcontroller architectures via network compression. We present a methodology for systematically exploring different DNN pruning, quantization, and deployment strategies for different microcontroller architectures, with a focus on low-power ARM Cortex-M-based systems. The exploration allows to analyze trade-offs between key metrics such as accuracy, memory consumption, execution time, and power consumption. We discuss experimental results on three different DNN architectures and show that we can compress them to less than 10% of their original parameter count before their prediction quality degrades. This also allows us to deploy and evaluate them on Cortex-M based microcontrollers.<br
Keywords: Deep Neural Networks; Deep Compression; Neural Pruning; Quantization; Microcontrollers

Energy Estimation and Optimization for Piecewise Regular Processor Arrays - Hannig, Frank; Teich, Jürgen (Chapter 6 in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, 2004)
UnivIS-Import:2015-04-20:Pub.2004.tech.IMMD.inform.energy

Energy Estimation for Piecewise Regular Processor Arrays - Hannig, Frank; Teich, Jürgen (Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation, 2002)
UnivIS-Import:2015-04-16:Pub.2002.tech.IMMD.inform.energy_1

Energy Estimation of Nested Loop Programs - Hannig, Frank; Teich, Jürgen (Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures, 2002)
An energy estimation methodology when mapping nested loop programs onto fine grained VLSI architectures is proposed. Regular loop algorithms with uniform data dependencies have some power consumption-friendly properties. E.g., using linear allocation and scheduling functions (loop transformations) results in distributed computations and communication between nearest neighbor processors. So, data can be stored locally in each processor which is essential for low power VLSI designs. We show that the chosen mapping has a significant influence on the consumed energy. Our estimation approach identifies statements with decreased operand switching activity. For these statements with reduced activity, a lower power consumption value can be directly obtained from a generated table based model to refine the estimation. Experimental results fortify the significant influence of the mapping (loop transformation).
UnivIS-Import:2015-04-16:Pub.2002.tech.IMMD.inform.energy

Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice - Simon, Bertrand; Falk, Joachim; Megow, Nicole; Teich, Jürgen (Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES), 2020)
Static (offline) techniques for mapping applications given by task graphs to MPSoC systems often deliver overly pessimistic and thus suboptimal results w.r.t. exploiting time slack in order to minimize the energy consumption. This holds true in particular in case computation times of tasks may be workload-dependent and becoming known only at runtime or in case of conditionally executed tasks or scenarios. This paper studies and quantitatively evaluates different classes of algorithms for scheduling periodic applications given by task graphs (i.e., DAGs) with precedence constraints and a global deadline on homogeneous MPSoCs purely at runtime on a per-instance base. We present and analyze algorithms providing provably optimal results as well as approximation algorithms with proven guarantees on the achieved energy savings. For problem instances taken from realistic embedded system benchmarks as well as synthetic scalable problems, we provide results on the computation time and quality of each algorithm to perform a) scheduling and b) voltage/speed assignments for each task at runtime. In our portfolio, we distinguish as well continuous and discrete speed (e.g., DVFS-related) assignment problems. In summary, the presented ties between theory (algorithmic complexity and optimality) and execution time analysis deliver important insights on the practical usability of the presented algorithms for runtime optimization of task scheduling and speed assignment on MPSoCs.<br
Keywords: energy minimization; speed scaling; precedence graphs; scheduling; critical path; MPSoC