Probability-based DSE of Approximated LUT-based FPGA Designs - Echavarria Gutiérrez, Jorge Alfonso; Keszöcze, Oliver; Teich, Jürgen (15th IEEE Dallas Circuits and Systems Conference, 2022)

Proc. 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors - Charot, François; Hannig, Frank; Teich, Jürgen; Wolinski, Christophe (IEEE Press, 2010)
UnivIS-Import:2015-07-08:Pub.2010.tech.IMMD.inform.proc21

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL: Preface - Teich, Jürgen; Platzner, Marco (2008 International Conference on Field Programmable Logic and Applications, FPL, 2008)

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016 - Fanucci, Luca; Teich, Jürgen (Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, 2016)

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) - Cavallaro, Joseph R.; Ercegovac, Milos D.; Hannig, Frank; Ienne, Paolo; Swartzlander Jr., Earl E.; Tenca, Alexandre F. (Institute of Electrical and Electronics Engineers, 2011)
The proceedings contain 36 papers. The topics discussed include: CusComNet: a customisable network for reconfigurable heterogeneous clusters; address generation scheme for a coarse grain reconfigurable architecture; accelerating vision and navigation applications on a customizable platform; a high-performance, low power linear algebra core; a decimal floating point fused multiply-add unit with a novel decimal leading zero anticipator; longest prefix match and updates in range tries; lowcost hardware profiling of run-time and energy in FPGA embedded processors; TimeTrial: a low-impact performance profiler for streaming data applications; system-level design space exploration for dedicated heterogeneous multiprocessor systems; and decentralized dynamic resource management support for massively parallel processor array
UnivIS-Import:2015-07-08:Pub.2011.tech.IMMD.inform.procee

Proceedings of the 29th International Conference on Architecture of Computing Systems (ARCS) - Hannig, Frank; Cardoso, João M. P.; Pionteck, Thilo; Fey, Dietmar; Schröder-Preikschat, Wolfgang; Teich, Jürgen (Springer-Verlag, 2016)
UnivIS-Import:2018-09-06:Pub.2016.tech.IMMD.inform.procee

Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) - Hannig, Frank; Navaridas, Javier; Koch, Dirk; Abdelhadi, Ameer (IEEE Computer Society, 2020)

Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) - Hannig, Frank; Fey, Dietmar; Lokhmotov, Anton (2015)

Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021) - Hannig, Frank; Meloni, Paolo; Spallanzani, Matteo; Ziegler, Matthias (2021)
This volume contains the papers accepted at the first DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021), held virtually on February 5, 2021. SLOHA 2021 was co-located with the Conference on Design, Automation and Test in Europe (DATE

Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014) - Hannig, Frank; Koch, Dirk; Ziener, Daniel (2014)

Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014) - Hannig, Frank; Teich, Jürgen (2014)

Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015) - Hannig, Frank; Koch, Dirk; Ziener, Daniel (2015)

Processing Time Optimization for Robot Applications - Muradi, Murad; Wanka, Rolf (Proc. 6th International Conference on Control, Automation and Robotics (ICCAR), 2020)
This research work includes the use of heuristic algorithms to automatically generate processing time optimized robot programs for manufacturing processes in the automotive industry. For this, we've implemented a genetic algorithm with multi-parent recombination and adjacency-based crossover. A reallocation mutation is also introduced to optimize the load balancing by classifying tasks into common and fixed tasks depending on their location relative to the robots' workspace. The heuristic is compared to an exact solver by applying it to a test problem. Lastly, the methodology is also applied to a real business problem in the area of vehicle sealin
Keywords: robotics; processing time optimization; sequencing; scheduling; load balancing; genetic algorithm; held-karp algorithm; branch-and-bound algorithm

Proc. IEEE Int. Conference on Application Specific Systems, Architectures, and Processors (ASAP´97) - Fortes, J; Noll, T; Taylor, V; Teich, Jürgen; Thiele, Lothar; Vissers, K (IEEE Computer Society Press, 1997)

Providing Fault Tolerance Through Invasive Computing - Lari, Vahid; Weichslgartner, Andreas; Tanase, Alexandru-Petru; Witterauf, Michael; Khosravi, Faramarz; Teich, Jürgen; Heißwolf, Jan; Friederich, Stephanie; Becker, Jürgen (it - Information Technology, 2016)

Providing security on demand using invasive computing - Drescher, Gabor; Erhardt, Christoph; Freiling, Felix; Götzfried, Johannes; Lohmann, Daniel; Maene, Pieter; Müller, Tilo; Verbauwhede, Ingrid; Weichslgartner, Andreas; Wildermann, Stefan (it - Information Technology, 2016)

Providing Tamper-Secure SoC Updates through Reconfigurable Hardware - Streit, Franz-Josef; Wildermann, Stefan; Pschyklenk, Michael; Teich, Jürgen (Springer Proceedings of the 17th International Symposium on Applied Reconfigurable Computing, 2021)
Remote firmware updates have become the de facto standard to guarantee a secure deployment of often decentrally operated IoT devices. However, the transfer and the provision of updates are considered as highly security-critical. Immunity requirements, such as the authenticity of the update provider and the integrity and confidentiality of the content typically loaded from an external cloud server over an untrusted network are therefore mandatory. This is especially true for FPGA-based programmable System-on-Chip (PSoC) architectures, as they are ideal implementation candidates for products with a long lifetime due to their adaptivity of both software and hardware configurations. In this paper, we propose a methodology for securely updating PSoC architectures by exploiting the reconfigurable logic of the FPGA. In the proposed approach, the FPGA serves as a secure anchor point by performing the required authenticity and integrity checks before granting the system update to be installed. In particular, a hardware design called Trusted Update Unit (TUU) is defined that is loaded from memory for the duration of an update session to first verify the identity of an external update provider and then, based on this verification, to establish a secure channel for protected data transfers. The proposed approach is also able to secure the confidentiality of cryptographic keys even if the software of the PSoC is compromised by applying them only as device-intrinsic secrets. Finally, an implementation of the approach on a Xilinx Zynq PSoC is described and evaluated for the design objectives performance and resource costs.<br
Keywords: Security· SoC· FPGA· Secure Update· Partial Reconfiguration· Hardware/Software Co-Design

Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA - Trautmann, Jens; Patsiatzis, Nikolaos; Becher, Andreas; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 2022)
Side-Channel Analysis (SCA) requires the detection of the specific time frame Cryptographic Operations (COs) take place in the side-channel signal. Under laboratory conditions with full control over the Device under Test (DuT), dedicated trigger signals can be implemented to indicate the start and end of COs. For real-world scenarios, waveform-matching techniques have been established which compare the side-channel signal with a template of the CO’s pattern in real time to detect the CO in the side channel. State-of-the-Art approaches describe implementations based on Field-Programmable Gate Arrays (FPGAs). However, the maximal length of the template is restricted by the resources available on an FPGAs. Particularly, for high sampling rates the recording of an entire CO may need more samples than the maximum template length supported by a waveform-matching system. Consequently, the template has to be reduced such that it fits the resources while still containing all relevant features for detecting the COs via waveform matching. In this paper, we introduce a generic interval-matching technique which provides several degrees of freedom for fine-tuning it to the statistical deviations of waveform measurements of COs. Moreover, we introduce a novel calibration method that finds the best parameters automatically based on statistical analysis of training data. Furthermore, we investigate a technique to reduce the number of features used for the interval matching by utilizing machine-learning-based feature extraction to find the most important samples in a template. Finally, we evaluate the state-of-the-art interval matching and our expansions during calibration and during the application on a test set. The results show, that a reliable reduction to 10% of the original template size is possible with a reduction method from literature for our example. However, the combination of our proposed methods can reliably work with only 1.5% of the original size and is less volatile than the state-of-the-art approach for reducing the number of feature
Keywords: Signal Processing; Interval Matching; Waveform Matching; Side-Channel Analysis

Quad-trees: A Data structure for storing Pareto-sets in Multi-objective Evolutionary Algorithms with Elitism - Mostaghim, Sanaz; Teich, Jürgen (Evolutionary Multiobjective Optimization, 2005)
UnivIS-Import:2015-04-20:Pub.2003.tech.IMMD.inform.quadtr

Quality-aware video decoding on thermally-constrained MPSoC platforms - Gangadharan, Deepak; Teich, Jürgen; Chakraborty, Samarjit (Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2014)
Current mobile devices extensively run video players that are power hungry. Further, higher power densities as a result of technology scaling results in higher on-chip temperatures. Unlike general purpose computer systems, mobile devices that run on batteries cannot afford to have expensive cooling mechanisms. Therefore, in order to satisfy thermal constraints while running power hungry applications, dynamic thermal management (DTM) techniques have been employed. For multimedia applications, the techniques primarily relied on dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM) while taking care that maximum video quality is achieved. However, no prior work has exploited frame drops to lower the inserted idle times under predetermined quality constraints. In this work, we propose a DPM framework that utilizes frame drops to dynamically insert low idle times in order to satisfy a peak temperature constraint under a given quality constraint. This also reduces the end-to-end latency. The latencies are further reduced by maintaining lightweight workload histories. For the videos used in our experiments, it was observed that a small reduction in quality of 2 dB (reduction from 32 dB to 30 dB) due to frame drops in motion videos results in a maximum latency reduction of 1.7 sec. © 2014 IEEE.

Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices - Dutta, Hritam; Hannig, Frank; Ruckdeschel, Holger; Teich, Jürgen (Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing, 2008)
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.quanti_0

Quasi-static scheduling of data flow graphs in the presence of limited channel capacities - Falk, Joachim; Schwarzer, Tobias; Glaß, Michael; Teich, Jürgen; Zebelein, Christian; Haubelt, Christian (13th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2015, 2015)
Signal processing algorithms as can be found in multimedia applications are often modeled by dynamic Data Flow Graphs (DFGs), especially when targeting heterogeneous multicore platforms. However, there is often a mismatch between the fine granularity of the application and the coarse granularity of the platform. Tailoring the granularity of the DFG to a given platform by employing Quasi-Static Schedules (QSSs) promises performance gains by reducing dynamic scheduling overhead and enabling optimizations targeting groups of actors instead of individual actors in isolation. Unfortunately, all approaches known from literature to compute QSSs implicitly assume DFGs with unbounded First In First Out (FIFO) channels. In contrast, mappings of DFGs to multi-core platforms must adhere to FIFO channels with limited capacities. In this paper, we present a novel FIFO channel capacity adjustment algorithm that enables QSSs to DFGs with limited channel capacities, thus, extending the scope of QSS refinements to general multi-core targets.
Keywords: Channel capacity; Dynamic scheduling; Flow graphs; Hardware; Multimedia communication; Ports (Computers); System recovery

Rapid Design of Real-Time Image Fusion on FPGA Using HLS and Other Techniques - Aydin, Furkan; Ugurdag, H. Fatih; Leyent, Vecdi Emre; Guzel, Aydin Emre; Annafianto, N. Fajar R.; Özkan, Mehmet Akif; Akgun, Toygar; Erbas, Cengiz (2018 IEEE/ACS 15TH INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS (AICCSA), 2018)
CRIS-Team WoS Importer:2019-02-22

Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain - Schmid, Moritz (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2015)

Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures - Eisenring, Michael; Teich, Jürgen; Thiele, Lothar (Proc. of HICSS'98, the Hawai'i Int. Conf. on Syst. Sci., 1998)
In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are inserted into the specification to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are refined according to given communication constraints (bus protocols, memory mapping, interrupts, DMA, etc.). A framework is described that uses an object-oriented approach to transform a given dataflow graph and to generate code for the actors as well as for the interfaces. The object-orientation enables an easy migration (retargeting) of typical communication primitives to other target architectures.
UnivIS-Import:2015-04-16:Pub.1998.tech.IMMD.inform.rapidp

RAP Model - Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience - Herkersdorf, Andreas; Engel, Michael; Glaß, Michael; Henkel, Jörg; Kleeberger, Veit B.; Kühn, Johannes M.; Marwedel, Peter; Mueller-Gritschneder, Daniel; Nassif, Sani R.; Rehman, Semeen; Rosenstiel, Wolfgang; Schlichtmann, Ulf; et al. (Dependable Embedded Systems, 2020)

RAVEN: Reinforcement Learning for Generating Verifiable Run-time Requirement Enforcers for MPSoCs - Esper, Khalil; Spieck, Jan; Sixdenier, Pierre-Louis André Edouard; Wildermann, Stefan; Teich, Jürgen (Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023), 2023)
In embedded systems, applications frequently have to meet non-functional requirements regarding, e.g., real-time or energy consumption constraints, when executing on a given MPSoC target platform. Feedback-based controllers have been proposed that react to transient environmental factors by adapting the DVFS settings or degree of parallelism following some predefined control strategy. However, it is, in general, not possible to give formal guarantees for the obtained controllers to satisfy a given set of non-functional requirements. Run-time requirement enforcement has emerged as a field of research for the enforcement of non-functional requirements at run-time, allowing to define and formally verify properties on respective control strategies specified by automata. However, techniques for the automatic generation of such controllers have not yet been established. In this paper, we propose a technique using reinforcement learning to automatically generate verifiable feedback-based enforcers. For that, we train a control policy based on a representative input sequence at design time. The learned control strategy is then transformed into a verifiable enforcement automaton which constitutes our run-time control model that can handle unseen input data. As a case study, we apply the approach to generate controllers that are able to increase the probability of satisfying a given set of requirement verification goals compared to multiple state-of-the-art approaches, as can be verified by model checkers.<br
Keywords: Verification; Runtime Requirement Enforcement; Reinforcement Learning; Finite State Machines; Model Checking

Raw Filtering of JSON data on FPGAs - Hahn, Tobias; Becher, Andreas; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe, 2022)
Many Big Data applications include the processing of data streams on semi-structured data formats such as JSON. A disadvantage of such formats is that an application may spend a significant amount of processing time just on unselectively parsing all data. To relax this issue, the concept of raw filtering is proposed with the idea to remove data from a stream prior to the costly parsing stage. However, as accurate filtering of raw data is often only possible after the data has been parsed, raw filters are designed to be approximate in the sense of allowing false-positives in order to be implemented efficiently. Contrary to previously proposed CPU-based raw filtering techniques that are restricted to string matching, we present FPGA-based primitives for filtering strings, numbers and also number ranges. In addition, a primitive respecting the basic structure of JSON data is proposed that can be used to further increase the accuracy of introduced raw filters. The proposed raw filter primitives are designed to allow for their composition according to a given filter expression of a query. Thus, complex raw filters can be created for FPGAs which enable a drastical decrease in the amount of generated false-positives, particularly for IoT workload. As there exists a trade-off between accuracy and resource consumption, we evaluate primitives as well as composed raw filters using different queries from the RiotBench benchmark. Our results show that up to 94.3% of the raw data can be filtered without producing any observed false-positives using only a few hundred LUTs.

Real-Time Range Image Preprocessing on FPGAs - Schmid, Moritz; Blocherer, Markus; Hannig, Frank; Teich, Jürgen (Proc. International Conference on Reconfigurable Computing and FPGAs, 2013)
Unprocessed range images acquired by some range sensing modality often show bumpy surfaces and distorted object boundaries, complicating post processing, such as 3D-registration and feature extraction. The effects are mostly caused by noise due to sensor limitations, but can be mitigated through applying image processing techniques, as for example defect pixel interpolation, bilateral temporal averaging, and edge-preserving noise filtering. In this work, we present an approach to perform preprocessing of range images on field programmable gate arrays (FPGAs) using single precision floating point arithmetic. Moreover, we present an FPGA infrastructure, including image acquisition from a host computer via PCI express. Although this work is based on range images obtained from a Microsoft Kinect range sensing camera, the presented approach is applicable to modalities for range image acquisition, in general. The proposed image processing pipeline can be run at 150MHz for VGA-resolution images and imposes a latency close to 2 ms. © 2013 IEEE.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.realti

Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays - Walter, Dominik; Witterauf, Michael; Teich, Jürgen (Proceedings of the 18th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), 2020)
A fundamental problem of massively parallel ac- celerator architectures is the management of typically small peripheral I/O buffers that decouple the accelerator from an external memory. Very often, these buffers cannot store the entire input and output data of one execution and must be updated, i.e., filled or drained, frequently. Moreover, if a processor array performs either a read on an empty bank or a write on a full bank, it must interrupt its execution immediately until the corresponding data transfer between the accelerator and an external memory has been carried out. As a consequence, the timing predictability of the array execution might be impaired. Therefore, a precise analysis of a schedule for all data transfers is inevitable. But the sequence of all data transfers cannot be stored entirely inside most accelerators. Thus, we must determine and schedule all necessary data transfers dynamically at runtime. In this paper, we present an approach to characterize all necessary data transfers and to issue them in advance so that the peripheral I/O buffers never run full or empty. Here, it is shown first that a deadline for each data transfer can be derived from a given loop schedule resulting in a traditional task scheduling program. Unfortunately, however, standard real-time scheduling techniques such as earliest deadline first (EDF) cannot be applied here, as each data transfer must not be interrupted and even existing non-preemptive variants of EDF are known to be prone to timing anomalies. As a solution, we present a strictly non-work-conserving variant of EDF together with an efficient schedulability test for periodic loop executions. In an experimental section, the scheduling approach is applied to a randomly generated set of loop programs observing that our algorithm is able to feasibly schedule 95% of the theoretically schedulable problem instances. Altogether, we provide a fully timing-predictable buffer management for massively parallel processor arrays that avoids any I/O related stalls of a processor array by construction.<br
Keywords: TCPA; Puffer; I/O Schedule

Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems - Pourmohseni, Behnaz; Smirnov, Fedor; Wildermann, Stefan; Teich, Jürgen (Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES), 2020)
Keywords: hard real-time; task migration; timing analysis; dynamic resource management; multi-core; many-core

Real-Time Waveform Matching with a Digitizer at 10 GS/s - Trautmann, Jens; Patsiatzis, Nikolaos; Becher, Andreas; Teich, Jürgen; Wildermann, Stefan (IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications, 2022)
Side-Channel Analysis (SCA) requires the detection of the specific time frame Cryptographic Operations (COs) takeplace in the side-channel signal. In laboratory conditions with full control over the Device under Test (DuT), dedicated trigger signals can be implemented to indicate the start and end of COs. For real-world scenarios, waveform-matching techniques have been established which compare the side-channel signal with a template of the CO’s pattern in real time to detect the CO in the side channel. State-of-the-art approaches are implemented on Field-Programmable Gate Arrays (FPGAs). However, current waveform-matching designs are processing the samples from Analog-to-Digital Converters (ADCs) sequentially and can only work with low sampling rates due to the limited clock speed of FPGAs. This makes it increasingly difficult to apply existing techniques on modern DuTs that are operating with clock speeds in the GHz range. In this paper, we present a parallel waveform-matching architecture that is capable of performing waveform matching at the speed of fast ADCs. We implement the proposed architecture in a high-end FPGA-based digitizer and apply it to detect AES COs from the side channel of a single-board computer operating at 1 GHz. Our implementation allows for waveform matching at 10 GS/s with high accuracy, thus offering a speedup of 50x compared to the fastest state-of-the-art implementation known to u
Keywords: Side-Channel Analysis; Waveform Matching; Parallel FPGA Design; Signal Processing

Recap of the 2016 DATE Conference & Exhibition - Fanucci, Luca; Teich, Jürgen (IEEE Design and Test of Computers, 2016)

ReCoBus-Builder - A Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs - Beckhoff, Christian; Koch, Dirk; Teich, Jürgen (Proceedings of International Conference on Field-Programmable Logic and Applications, 2008)
In this paper, we present the ReCoBus-Builder tool chain that simplifies the generation of dynamically reconfigurable systems to almost a push-button process. The generated systems provide one or more resource areas that will be used by different partially reconfigurable modules at runtime. It is possible to integrate multiple partially reconfigurable modules into the same resource area at the same time and these modules can communicate via a fixed bus infrastructure or dedicated point-to-point links with other parts of the system. This allows building encapsulated modules that will be integrated into the system by linking together bitstreams at runtime. We will demonstrate that bitstream linking can further be used to speed up the design process of static only systems by eliminating long synthesis runs or place and route steps, when only small portions of a design are exchanged.© 2008 IEEE.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.recobu

ReCoNet: Modeling and implementation of fault tolerant distributed reconfigurable hardware - Haubelt, Christian; Koch, Dirk; Teich, Jürgen (Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI2003), 2003)
Recent research was mainly focused on the OS support for a single reconfigurable chip. This paper presents a general approach to manage fault tolerant distributed reconfigurable hardware. In order to run such a system, three basic tasks must be implemented: (i) rerouting to compensate line errors, (ii) rebinding to compensate node failures, and (iii) hardware reconfiguration to allow the optimization of these systems during runtime. This paper proposes first ideas and solutions of these management functions. Furthermore, a prototype implementation consisting of four fully connected FPGAs is presented.
Keywords: Automotive engineering; Body area networks; Computer science; Delay; Energy consumption; Fault tolerance; Field programmable gate arrays; Hardware; Operating systems; Prototypes

ReCoNets-design methodology for embedded systems consisting of small networks of reconfigurable nodes and connections - Haubelt, Christian; Koch, Dirk; Reimann, Felix; Streichert, Thilo; Teich, Jürgen (Springer Netherlands, 2010)
Automotive, avionic or body-area networks are systems that consist of several communicating control units specialized for certain purposes. Typically, constraints regarding reliability, availability but also flexibility are imposed on these systems. In this chapter, we will present the ReCoNets approach for increasing reliability and flexibility of such systems by solving the hardware/software codesign problem online. A ReCoNet allows to migrate tasks implemented in hardware or software from one node to another. Typically, it consists of a network of communicating Field-Programmable Gate Arrays (FPGAs) and CPUs. Moreover, if a sufficient number of hardware/software resources is not available, the migration of functionality from hardware to software or vice versa is initiated by the system itself. For supporting such flexibility, new design methods as well as services integrated in a distributed operating system for networked embedded systems are revealed. Besides the formal definition of methods and concepts providing several self-x properties such as self-healing, self-adaptiveness and self-optimization, a ReCoNet demonstrator is presented hosting a driver assistance application. © 2010 Springer Science+Business Media B.V.

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays - Sousa, Éricles; Hannig, Frank; Teich, Jürgen (Proceedings of the International Embedded Systems Symposium (IESS), 2015)

Reconfigurable Computing Architectures - Reimann, Felix (Proceedings of the 1st Chinese-German Summer School, 2006)

Reconfigurable Computing Systems - Teich, Jürgen (it - Information Technology, 2007)
UnivIS-Import:2015-03-09:Pub.2007.tech.IMMD.inform.reconf

Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution - Schmitt, Christian; Schmid, Moritz; Kuckuk, Sebastian; Köstler, Harald; Teich, Jürgen; Hannig, Frank (Parallel Processing Letters, 2018)
Not only in the field of high-performance computing, field-programmable gate arrays (FPGAs) are a soaringly popular accelerator technology. However, they use a completely different programming paradigm and tool set compared to CPUs or even GPUs, adding extra development steps and requiring special knowledge, hindering widespread use in scientific computing. To bridge this programmability gap, domain-specific languages are a popular choice to generate low-level implementations from an abstract algorithm description. In this work, we demonstrate our approach for the generation of numerical solver implementations based on the multigrid method for FPGAs from the same code base that is also used to generate code for CPUs using a hybrid parallelization of MPI and OpenMP. Our approach yields in a hardware design that can compute up to 11 V-cycles per second with an input grid size of 4096x4096 and solution on the coarsest using the conjugate gradient method on a mid-range FPGA, beating vectorized, multi-threaded execution on an Intel Xeon processor.

Reconfigurable HW/SW Architecture of a Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System - Angermeier, Josef; Batzer, Ulrich; Claus, Christopher; Majer, Mateusz; Stechele, Walter; Teich, Jürgen (Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing, 2008)
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.reconf

Reconfigurable Implementation of Elliptic Curve Crypto Algorithms - Bednara, Marcus; J. Shokrollahi, J.; Teich, Jürgen; Daldrup, M.; von zur Gathen, J. (Proc. The 9th Reconfigurable Architectures Workshop, 2002)
UnivIS-Import:2015-04-16:Pub.2002.tech.IMMD.inform.reconf

ReCoNodes-optimization methods for module scheduling and placement on reconfigurable hardware devices - Ahmadinia, Ali; Angermeier, Josef; Fekete, Sandor P.; Kamphans, Tom; Koch, Dirk; Majer, Mateusz; Schweer, Nils; Teich, Jürgen; Tessars, Christopher; Van Der Veen, Jan C. (Springer Netherlands, 2010)
Placement and scheduling are recognized as the most important problems when exploiting the benefit of partially reconfigurable devices such as FPGAs. For example, dynamically loading and unloading modules onto an FPGA causes fragmentation, and-in turn-may decrease performance. To counteract this effect, we use methods from algorithmics and mathematical optimization to increase the performance and present algorithms for placing, scheduling, and defragmenting modules on FPGAs. Taking communication between modules into account, we further present strategies to minimize communication overhead. Finally, we consider scheduling module requests with time-varying resource demands. © 2010 Springer Science+Business Media B.V.

Reduction of Mobile Device Modem Energy via Adapative and Power-efficient Hybrid Online/Offline Grant Prediction for the Protocol Standards LTE and 5G - Brand, Peter (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2023)

Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores - Aliee, Hananeh; Banaiyianmofrad, Abbas; Glaß, Michael; Teich, Jürgen; Dutt, Nikil (Proc. Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'17), 2017)

Refactoring of Quantum and Reversible Circuits - Lukac, Martin; Nursultan, Saadat; Krylov, Georgiy; Keszöcze, Oliver (International Workshop on Quantum Compilation, 2020)

Registration of measured and simulated non-ideal geometry using optimization methods. - Paetzold, Kristin; Wittmann, Stefan; Stoll, Tobias; Helwig, Sabine (International Seminar on Computet Aided Tolerancing, 2007)
UnivIS-Import:2015-04-16:Pub.2007.tech.FT.FT-KLMEFK.regist

Regular Mapping for Coarse-grained Reconfigurable Architectures - Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004)
Similar to programmable devices such as processors or micro controllers also reconfigurable logic devices can be built as software, by programming the configuration of the device. In this paper, we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable architectures. The application areas of most of these architectures addressing computational-intensive algorithms like video and audio processing or wireless communication. Therefore, reconfigurable arrays are in direct competition with DSP processors which are traditionally used for digital signal processing. Hence, existing mapping methodologies are closely related to approaches from the DSP world. They try to employ pipelining and temporal partitioning but they do not exploit the full parallelism of a given algorithm and the computational potential of typically 2-dimensional arrays. We present a first case study for mapping regular algorithms onto reconfigurable arrays by using our design methodology which is characterized by loop parallelization in the polytope model. The case study shows that our regular mapping methodology may lead to highly efficient implementations taking the constraints of the architecture into account.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.regula

Regular State Machines - Strehl, Karsten; Teich, Jürgen; Thiele, Lothar (Parallel Algorithms and Applications, 2000)
UnivIS-Import:2015-03-09:Pub.2000.tech.IMMD.inform.regula

Regular State Machines - Teich, Jürgen; Thiele, Lothar (Presented at Workshop Seminar No. 98341, Tiling for Optimal Resource Utilization, 1998)

Reinforcement Learning for Power-Efficient Grant Prediction in LTE - Brand, Peter; Falk, Joachim; Ah Sue, Jonathan; Brendel, Johannes; Hasholzner, Ralph; Teich, Jürgen (21st International Workshop on Software and Compilers for Embedded Systems (SCOPES’18), 2018)
Keywords: Dynamic Network Communication; LTE Radio Systems; Machine Learning; Predictability; Power Efficient Data Transmission

Reliability Analysis and Optimization of Embedded Systems using Stochastic Logic and Importance Measures - Aliee, Hananeh (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2017)
Keywords: Reliability; Embedded Systems; Optimization; System-Level Design; Importance Measure; Stochastic Logic

Reliability-aware system synthesis - Teich, Jürgen; et al. (Proceedings of Design, Automation and Test in Europe (DATE 2007), 2007)
Increasing reliability is one of the most important design goals for current and future embedded systems. In this paper, we will put focus on the design phase in which reliability constitutes one of several competing design objectives. Existing approaches considered the simultaneous optimization of reliability with other objectives to be too extensive. Hence, they firstly design a system, secondly analyze the system for reliability and finally exchange critical parts or introduce redundancy in order to satisfy given reliability constraints or optimize reliability. Unfortunately, this may lead to suboptimal designs concerning other design objectives. Here, we will present a) a novel approach that considers reliability with all other design objectives simultaneously, b) an evaluation technique that is able to perform a quantitative analysis in reasonable time even for real-world applications, and c) experimental results showing the effectiveness of our approach. © 2007 EDAA.

Reliability of Space-Grade vs. COTS SRAM-Based FPGA in N-Modular Redundancy - Glein, Robert; Rittner, Florian; Becher, Andreas; Ziener, Daniel; Frickel, Jürgen; Teich, Jürgen; Heuberger, Albert (Proceedings of 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015)
In this paper, we evaluate the suitability of different SRAM-based FPGAs for harsh radiation environments (e.g., space). In particular, we compare the space-grade and radiation-hardened by design Virtex-5QV (XQR5VFX130) with the commercial off-the-shelf Kintex-7 (KC7K325T) from Xilinx. The advantages of the latter device are: 2.5 times the resources of the space-grade FPGA, faster switching times, less power consumption, and the support of modern design tools. We focus on resource consumption as well as reliability in dependence of single event upset rates for a geostationary earth orbit satellite application, the Heinrich Hertz satellite mission. For this mission, we compare different modular redundancy schemes with different voter structures for the qualification of a digital communication receiver. A major drawback of the Kintex-7 are current-step single event latchups, which are a risk for space missions. If the use of an external voter is not possible, we suggest triple modular redundancy with one single voter at the end, whereby the Virtex-5QV in this configuration is about as reliable as the Kintex-7 in an N-modular redundancy configuration with an external high-reliable voter.
Keywords: FPGA; radiation; space; TMR; NMR; Xilinx; Kintex; Virtex; single event upset; SEU; modular redundancy

Reliable Energy-Efficient Dynamic TDMA MAC Protocol for Wireless Body Area Networks - Pourmohseni, Behnaz; Eshghi, Mohammad (International journal of application or innovation in engineering & management, 2013)

ReOrder: Runtime Datapath Generation for High-Throughput Multi-Stream Processing - Becher, Andreas; Wildermann, Stefan; Mühlenthaler, Moritz; Teich, Jürgen (Proceedings of the International Conference on Reconfigurable Computing and FPGAs, 2016)

Representation of Function Variants for Embedded System Optimization and Synthesis - Ernst, Rolf; Richter, Kai; Teich, Jürgen; Thiele, Lothar; Ziegenbein, Dirk (Proc. 36th Design Automation Conference, 1999)
Many embedded systems are implemented with a set of alternative function variants to adapt the system to different applications or environments. This paper proposes a novel approach for the coherent representation and selection of function variants in the different phases of the design process. In this context, the modeling of reconfiguration of system parts is supported in a natural way. Using a real example from the video processing domain, the approach is explained and validated.
UnivIS-Import:2015-04-16:Pub.1999.tech.IMMD.inform.repres

Representation of Process Mode Correlation for Scheduling - Ernst, Rolf; Richter, Kai; Teich, Jürgen; Thiele, Lothar; Ziegenbein, Dirk (Proc. of ICCAD - the ACM/IEEE Int. Conf. on CAD, 1998)
The specification of embedded systems very often contains a mixture of different models of computation. In particular, the data flow and control flow associated to the transformative and reactive domains, respectively, are tightly coupled. The paper considers classes of applications that feature communicating processes whose functions depend on a finite set of computation modes. The change between these modes is synchronized by data communication. An approach is presented to model the correlation of process modes and to fully utilize this information for scheduling. A modeling example shows the optimization potential of the new approach.
UnivIS-Import:2015-04-16:Pub.1998.tech.IMMD.inform.repres

Representing mapping and scheduling decisions within dataflow graphs - Zebelein, Christian; Haubelt, Christian; Falk, Joachim; Schwarzer, Tobias; Teich, Jürgen (Proceedings of Forum on Specification & Design Languages (FDL 2013), 2013)
Choosing the right programming model for multiprocessor System-on-Chip (MPSoC) platforms is a challenging task: in order to provide for automatic hardware/software synthesis in a model-based design flow, the system model should be architecture-independent on the one hand, but should also allow the back-annotation of architecture-dependent mapping and scheduling decisions on the other hand. Here, architecture-independent dataflow models are particularly suitable. In a dataflow model, concurrent processes (actors) communicate via packets transmitted over channels. However, the back-annotation process is difficult, and previous approaches are either restricted to static dataflow actors or static schedules. Also, the semantics of the underlying dataflow actors are often different from the semantics of the scheduling mechanism, which limits the compositionality of the dataflow model. In this paper, we propose a modeling approach which unifies the representation of dataflow actors and scheduling mechanisms, while also providing for both, dynamic dataflow actors and dynamic scheduling decisions. We describe how various scheduling schemes can be represented by our approach, and show the applicability of the proposed approach by means of synthetic dataflow graphs. © 2013 European Electronic Chips & Systems design Initiative - ECSI.

Representing Models of Computation in SystemC - Falk, Joachim; Haubelt, Christian; Teich, Jürgen (GI/ITG/GMM-Workshop 2005, 2005)

ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing - Becher, Andreas; Herrmann, Achim; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 1st Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC), 2019)
Reconfigurable hardware such as Field-programmable Gate Arrays (FPGAs) is widely used for data processing in databases. Most of the related work focuses on accelerating one or a small set of specific operations like sort, join, regular expression matching. A drawback of such approaches is often the assumed static accelerator hardware architecture: Rather than adapting the hardware to fit the query, the query plan has to be adapted to fit the hardware. Moreover, operators or data types that are not supported by the accelerator have to be processed in software. As a remedy, approaches for exploiting the dynamic partial reconfigurability of FPGAs have been proposed that are able to adapt the datapath at runtime. However, on modern FPGAs, this introduces new challenges due to the heterogeneity of the available resources. In addition, not only the execution resources may be heterogeneous but also the memory resources. This work focuses on the architectural aspects of database (co-)processing on heterogeneous FPGA-based PSoC (programmable System-on-Chip) architectures including processors, specialized hardware components, multiple memory types and dynamically partially reconfigurable areas. We present an approach to support such (co-)processing called ReProVide. In particular, we introduce a model to formalize the challenging task of operator placement and buffer allocation onto such heterogeneous hardware and describe the difficulties of finding good placements. Furthermore, a detailed insight into different memory types and their peculiarities is given in order to use the strength of heterogeneous memory architectures. Here, we also highlight the implications of heterogeneous memories for the problem of query placemen
Keywords: FPGA; Shared Memory; Query Acceleration; Near-Memory Processing

Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-Chip Resilience - Herkersdorf, Andreas; Aliee, Hananeh; Engel, Michael; Glaß, Michael; Gimmler-Dumont, Christina; Henkel, Jörg; Kleeberger, Veit B.; Kochte, Michael A.; Kühn, Johannes M.; Mueller-Gritschneder, Daniel; Nassif, Sani R.; Rauchfuss, Holm; et al. (Microelectronics Reliability, 2014)

Resource-Aware Computer Vision Application on Heterogeneous Multi-Tile Architecture. - Sousa, Éricles; Paul, Johny; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Stechele, Walter (Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), 2014)

Resource-awareness on heterogeneous MPSoCs for image processing - Paul, Johny; Stechele, Walter; Oechslein, Benjamin; Erhardt, Christoph; Schedel, Jens; Lohmann, Daniel; Schröder-Preikschat, Wolfgang; Kröhnert, Manfred; Asfour, Tamim; Sousa, Éricles; Hannig, Frank; Lari, Vahid; et al. (Journal of Systems Architecture, 2015)
Multiprocessor system-on-chip (MPSoC) designs offer a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. On-chip MPPAs can be used to accelerate low-level image-processing algorithms with massive inherent parallelism. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, among others. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to under-utilization of some type of PEs while overloading others. In this work, we investigate the benefits of using a heterogeneous MPSoC for accelerating various stages within a real-world image-processing algorithm for object-recognition. A case study demonstrates that a resource-aware programming model called Invasive Computing helps to improve the throughput and worst observed latency of the application program, by dynamically mapping applications to different types of PEs available on a heterogeneous MPSo
Keywords: Computer vision; Heterogeneous processor; Image processing; Invasive Computing; MPSoC; Resource awareness

Resource-aware parameter tuning for real-time applications - Gabriel, Dirk; Stechele, Walter; Wildermann, Stefan (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2019)
Executing multiple applications on a multi-core system while the workload of all applications varies brings the challenge of dynamically adapting resource allocations and parametrizing with respect to constraints e.g. timing limits of real-time applications. We present a hybrid approach which extracts a set of Pareto-optimal operating points during design time which are used to dynamically parameterize the periodic application during run-time. The setup is done at the beginning of each iteration of the execution and exclusively allocates processing elements from the system depending on the current workload. The parametrization is performed with the observed information about workload complexity and allocated resources. Therefore guarantees on time limits can be granted for all iterations including situations when the number of available processing elements has been decreased sharply.
CRIS-Team Scopus Importer:2019-05-28
Keywords: Parameter tuning; Reliability; Resource reservation; Resource-aware application; Self-aware application

Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10 - Hannig, Frank; Roloff, Sascha; Snelting, Gregor; Teich, Jürgen; Zwinkau, Andreas (Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011)
The efficient use of future MPSoCs with f 000 or more processor cores requires new means of resource-aware programming to deal with increasing imperfections such as process variation, fault rates, aging effects, and power as well as thermal problems. In this paper, we apply a new approach called invasive computing that enables an application programmer to spread computations to processors deliberately and on purpose at certain points of the program. Such decisions can be made depending on the degree of application parallelism and the state of the underlying resources such as utilization, load, and temperature. The introduced programming constructs for resource-aware programming are embedded into the parallel computing language X10 as developed by IBM using a library-based approach. Moreover, we show how individual heterogeneous MPSoC architectures may be modeled for subsequent functional simulation by defining compute resources such as processors themselves by lightweight threads that are executed in parallel together with the application threads by the X10 run-time system. Thus, the state changes of each hardware resource may be simulated including temperature, aging, and other useful monitor functionality to provide a first high-level programming test-bed for invasive computing. Copyright © 2011 ACM.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.resour
Keywords: MPSoC; Resource-aware programming; Simulation; X10

Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals - Hannig, Frank; Teich, Jürgen (Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2004), 2004)
In this paper we present a significant extension of the quantified equation based algorithm class of piecewise regular algorithms. The main contributions of the following paper are: (1) the class of piecewise regular algorithms is extended by allowing run-time dependent conditionals, (2) a mixed integer linear program is given to derive optimal schedules of the novel class we call dynamic piecewise regular algorithms, and (3) in order to achieve highest performance, we present a speculative scheduling approach. The results are applied to an illustrative example.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.resour

Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms - Hannig, Frank; Teich, Jürgen (2004)

Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods - Sabih, Muhammad; Yayla, Mikail; Hannig, Frank; Teich, Jürgen; Chen, Jian-Jia (EuroMLSys '23: Proceedings of the 3rd Workshop on Machine Learning and System, 2023)
Binary neural networks (BNNs) are a highly resource-efficient variant of neural networks. The efficiency of BNNs for tiny machine learning (TinyML) systems can be enhanced by structured pruning and making BNNs robust to faults. When used with approximate memory systems, this fault tolerance can be traded off for energy consumption, latency, or cost. For pruning, magnitude-based heuristics are not useful because the weights in a BNN can either be -1 or +1. Global pruning of BNNs has not been studied well so far. Thus, in this paper, we explore gradient-based ranking criteria for pruning BNNs and use them in combination with a sensitivity analysis. For robustness, the state-of-the-art is to train the BNNs with bit-flips in what is known as fault-aware training. We propose a method to guide fault-aware training using gradient-based explainability methods. This allows us to obtain robust and efficient BNNs for deployment on tiny devices. Experiments on audio and image processing applications show that our proposed approach outperforms the existing approaches, making it useful for obtaining efficient and robust models for a slight degradation in accuracy. This makes our approach valuable for many TinyML use cases.<br
Keywords: Robustness; Explainable-AI; BNNs; DNNs; Binary Neural Networks

Robust Design of E/E Architecture Component Platforms - Graf, Sebastian; Reinhart, Sebastian; Glaß, Michael; Teich, Jürgen; Platte, Daniel (Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC 2015), 2015)

Robust Design of Embedded Systems - Lukasiewycz, Martin; Glaß, Michael; Teich, Jürgen (Proc. Design, Automation and Test in Europe, 2010)
This paper presents a methodology to evaluate and optimize the robustness of an embedded system in terms of invariability in case of design revisions. Early decisions in embedded system design may be revised in later stages resulting in additional costs. A method that quantifies the expected additional costs as the robustness value is proposed. Since the determination of the robustness based on arbitrary revisions is computationally expensive, an efficient set-based approach that uses a symbolic encoding as Binary Decision Diagrams is presented. Moreover, a methodology for the integration of the optimization of the robustness into a design space exploration is proposed. Based on an external archive that accepts also near-optimal solutions, this robustness-aware optimization is efficient since it does not require additional function evaluations as previous approaches. Two realistic case studies give evidence of the benefits of the proposed approach. © 2010 EDAA.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.robust

Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores - Ziener, Daniel; Schmid, Moritz; Teich, Jürgen (Design Methodologies for Secure Embedded Systems, 2010)
In this paper we analyze the robustness of watermarking techniques for FPGA IP cores against attacks. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, even if the protected cores are embedded into a product. Moreover, we have concentrated on higher abstraction levels for embedding the watermark, particularly at the logic level, where IP cores are distributed as netlist cores. With the presented watermarking methods, it is possible to watermark IP cores at the logic level and identify them with a high likelihood and in a reproducible way in a purchased product from a company that is suspected to have committed IP fraud. For robustness analysis we enhanced a theoretical watermarking model, originally introduced for multimedia watermarking. Finally, two exemplary watermarking techniques for netlist cores using different verification strategies are described and the robustness against attacks is analyzed. © 2010 Springer-Verlag Berlin Heidelberg.
UnivIS-Import:2015-04-20:Pub.2010.tech.IMMD.inform.robust_0

Robustness Approaches for the Examination Timetabling Problem under Data Uncertainty - Bassimir, Bernd; Wanka, Rolf (Proc. 9th Multidisciplinary International Conference on Scheduling: Theory and Applications, 2019)
In the literature the examination timetabling problem (ETTP) is often considered a post-enrollment problem (PE-ETTP). In the real world, universities often schedule their exams before students register using information from previous terms. A direct consequence of this approach is the uncertainty present in the resulting models. In this work we discuss several approaches available in the robust optimization literature. We consider the implications of each approach in respect to the examination timetabling problem and present how the most favorable approaches can be applied to the ETTP. Afterwards we analyze the impact of some possible implementations of the given robustness approaches on two real world instances and several random instances generated by our instance generation framework which we introduce in this work. <br
Keywords: Examination Timetabling; Robust Optimization; Test Instance Genera- tion

Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays - Sousa, Éricles; Hannig, Frank; Teich, Jürgen; Schlichtmann, Ulf; Chen, Qingqing (In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2015)
Massively Parallel Processor Arrays (MPPAs) can be nicely used in portable devices such as tablets and smartphones. However, applications running on mobile platforms require a certain performance level or quality (e.g., high-resolution image processing) that need to be satisfied while adhering to a certain power budget and temperature threshold. As a solution to the aforementioned challenges, we consider a resource-aware computing paradigm to exploit runtime adaptation without violating any thermal and/or power constraint in a programmable MPPA. For estimating the power consumption, we developed a mathematical model based on the post-synthesis implementation of an MPPA in different CMOS technologies while the temperature variation was emulated. We showcase our hardware/software mechanism to load new, on-the-fly configurations into the accelerator, considering quality/throughput tradeoffs for image processing applications. The results show that the average power consumption of a Sobel and Laplace operators using different number of processing elements amounts to 1.24mW and 10.35mW, respectively. Furthermore, only 1.64 μs are necessary for configuring a class of MPPA running at 550 MHz.

Run-time adaption for highly-complex multi-core systems - Henkel, Jörg; Narayanan, Vijaykrishnan; Parameswaran, Sri; Teich, Jürgen (11th ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013, 2013)
As embedded on-chip systems grow more and more complex and are about to be deployed in automotive and other demanding application areas (beyond the main-stream of consumer electronics), run-time adaptation is a prime design consideration for many reasons: i) reliability is a major concern when migrating to technology nodes of 32nm and beyond, ii) efficiency i.e. computational power per Watt etc. is a challenge as computing models do not keep up with hardware-provided computing capabilities, iii) power densities increase rapidly as Dennard Scaling fails resulting in what is dubbed "Dark Silicon", iv) highly complex embedded applications are hard to predict etc. All these scenarios (and further not listed here) make proactive and sophisticated run-time adaption techniques a prime design consideration for generations of multi-core architectures to come. The intend of this paper is to present problems and solutions of top research initiatives from diverse angels with the common denominator of the dire need for run-time adaption: The first part tackles the thermal problem i.e. high power densities and the related short and long-term effects it has on the reliability and it presents scalable techniques to cope the related problems. The second section demonstrates the potential of steep slope devices on thread scheduling of multi-cores. The third approach presents embedded pipelined architectures running complex multi-media applications whereas the fourth section introduces the paradigm of invasive computing i.e. a novel computing approach promising high efficiency through a highly-adaptive hardware/software architecture. In summary, the paper presents snapshots on four highlyadaptive solutions and platforms from different angles for challenges of complex future multi-core systems. © 2013 IEEE.

Runtime Analysis of a Discrete Particle Swarm Optimization Algorithm on Sorting and OneMax - Mühlenthaler, Moritz; Raß, Alexander; Schmitt, Manuel; Siegling, Andreas; Wanka, Rolf (Proceedings of the 14th ACM/SIGEVO Conference on Foundations of Genetic Algorithms, 2017)
We present the analysis of a discrete particle swarm optimization (PSO) algorithm that works on a significantly large class of discrete optimization problems. Assuming a black-box setting, we prove upper and lower bounds on the expected number of function evaluations required by the proposed algorithm to solve the sorting problem and the problem of maximizing the number of ones in a bitstring, i.e., the function OneMax. We show that depending on the probability of moving towards the attractor, the expected optimization time may be polynomial or exponential. The cornerstone of our analysis are Theta-bounds on the expected time it takes until the PSO returns to the attractor. We obtain these bounds by solving linear recurrence equations with constant and non-constant coefficients. We also introduce a useful indistinguishability property of states of a Markov chain in order to obtain lower bounds on the expected optimization time of our proposed PSO algorithm.
Keywords: Particle Swarm Optimization; Discrete Optimization; Run-time Analysis; Markov Chains

Runtime analysis of discrete particle swarm optimization algorithms: A survey - Mühlenthaler, Moritz; Raß, Alexander (it - Information Technology, 2019)
A discrete particle swarm optimization (PSO) algorithm is a randomized search heuristic for discrete optimization problems. A fundamental question about randomized search heuristics is how long it takes, in expectation, until an optimal solution is found. We give an overview of recent developments related to this question for discrete PSO algorithms. In particular, we give a comparison of known upper and lower bounds of expected runtimes and briefly discuss the techniques used to obtain these bound
Keywords: randomized search heuristics; particle swarm optimization; runtime analysis

Runtime Analysis of Discrete Particle Swarm Optimization Applied to Shortest Paths Computation - Raß, Alexander; Schreiner, Jonas; Wanka, Rolf (Evolutionary Computation in Combinatorial Optimization, 2019)
We mathematically analyze a discrete particle swarm optimization (PSO) algorithm solving the single-source shortest path (SSSP) problem. Key features are an improved and extended study on Markov chains expanding the adaptability of this technique and its application on the ubiquitous SSSP problem. The results are upper and lower bounds on the expected optimization time. For upper bounds, we combine return times within a Markov model with the well known fitness level method which is appropriate even for the non-elitist PSO algorithm. For lower bounds we prove that the recently introduced property of indistinguishability applies in this setting and we also combine it with a further Markov chain analysis.
Keywords: Discrete Particle Swarm Optimization; Runtime Analysis; Single-Source Shortest Paths; Markov Chains

Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems - Teich, Jürgen; Pourmohseni, Behnaz; Keszöcze, Oliver; Spieck, Jan; Wildermann, Stefan (Asia and South Pacific Design Automation Conference (ASP-DAC), 2020)
For many embedded applications, non-functional requirements such as safety, reliability, and execution time must be guaranteed in tight bounds on a given multi-core platform. Here, jitter in non-functional program execution qualities is caused either by outer influences such as faults injected by the environment, but can be induced also from the system management software itself, including thread-to-core mapping, scheduling and power management. A second huge source of variability typically stems from data-dependent workloads. In this paper, we classify and present techniques to enforce non-functional execution properties on multi-core programs. Based on a static design space exploration and analysis of influences of variability of non-functional properties, enforcement strategies are generated to guide the execution of periodically executed applications in given requirement corridors. Using the case study of a complex image streaming application, we show that by controlling DVFS settings of cores proactively, not only tight execution times, but also reliability requirements may be enforced dynamically while trying to minimize energy consumption.
Keywords: run-time enforcement; many-core systems; reliability; realtime

Run-Time Enforcement of Non-functional Program Properties on MPSoCs - Teich, Jürgen; Mahmoody, Pouya; Pourmohseni, Behnaz; Roloff, Sascha; Schröder-Preikschat, Wolfgang; Wildermann, Stefan (A Journey of Embedded and Cyber-Physical Systems, 2020)

Run-time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration - Bobda, Christophe; et al. (Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2003), 2003)
We present an efficient technique to implement multi-controller systems using partial reconfigurable hardware (FPGA). The control algorithm is implemented as a dedicated circuit. Partial runtime reconfiguration is used to increase the resource efficiency by keeping just the currently active controller modules on the FPGA while inactive controller modules are stored in an external memory. © Springer-Verlag Berlin Heidelberg 2003.
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.runtim

Run time Mapping of AdaptiveApplications onto Homogeneous NoC-based Reconfigurable Architectures - Wildermann, Stefan; Ziermann, Tobias; Teich, Jürgen (Proc. 2009 International Conference on Field-Programmable Technology, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.runtim

Run-Time Monitoring and Enforcement of Non-functional Program Properties of Invasive Programs: Terms and Definitions - Teich, Jürgen (2017)

Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures - Sousa, Éricles; Gangadharan, Deepak; Hannig, Frank; Teich, Jürgen (Proceedings of the EUROMICRO Digital System Design Conference (DSD), 2014)
This paper describes a runtime reconfigurable bus arbitration technique for concurrent applications on heterogeneous MPSoC architectures. Here, a hardware/software approach is introduced as part of a runtime framework that enables selecting and adapting different policies (i. e., fixed-priority, TDMA, and Round-Robin) such that the performance goals of concurrent applications can be satisfied. To evaluate the hardware cost, we compare our proposed solution with respect to a well-known SPARC V8 architecture supporting fixed-priority arbitration. Notably, even providing the flexibility for selecting up to three different policies, our reconfigurable arbiter needs only 25% and 7% more LUTs and slices registers, respectively. The reconfiguration overhead for changing between different policies is 56 cycles and for programming new time slots, only 28 cycles are necessary. For demonstrating the benefits of this reconfiguration framework, we setup a mixed hard/soft real-time scenario by considering four applications with different timeliness requirements. The experimental results show that by reconfiguring the arbiter, less processing elements can be used for achieving a specific target frame rate. Moreover, adjusting the time slots for TDMA, we can speedup a soft real-time algorithm while still satisfying the deadline for hard real-time applications.
Keywords: Concurrent Applications; Heterogeneous MPSoC Architectures; Reconfigurable Bus Arbitration; Runtime

Run-time Requirement Enforcement for Loop Programs on Processor Arrays - Witterauf, Michael; Teich, Jürgen (Proceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), 2018)
Loop bounds are often unknown until run time, making it difficult to analyze non-functional properties such as latency at compile-time. Similarly, static allocations of processing resources to loop computations might be too conservative with respect to given performance requirements, or not optimal with respect to the energy consumption. To still satisfy requirements when accelerating loop nests under this uncertainty of loop bounds, we formalize and propose an approach to run-time requirement enforcement: at run time, select a mapping among a set of candidates that satisfies a given set of requirements while optimizing secondary objectives. Because the candidate search space of suitable mappings might be prohibitively large to evaluate at run time, we further introduce two approaches to reduce its cardinality: 1) architecture-specific reduction by solving for parts of the mapping from the requirements, and 2) design-time reduction by finding a k-subset of mappings that maximizes the number of loop bounds where the requirements are satisfied. We implemented our proposed run-time requirement enforcement techniques for a representative class of programmable processor array architecture called Tightly Coupled Procesor Array and demonstrate their effectiveness with a case study. The case study shows the effectiveness of our approach: We can satisfy given latency requirements while easily saving up to 10% in energy. <br

Run-Time Scenario-Based MPSoC Mapping Reconfiguration Using Machine Learning Models - Spieck, Jan; Wildermann, Stefan; Teich, Jürgen (Post-workshop proceedings of 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD, 2020)
Applications with highly input-dependent workload and execution behavior cannot be optimally executed by a single mapping of application tasks to a heterogeneous multi-core target architecture. Albeit mapping a task to a resource with high computational power may be suitable for input triggering a high workload of this task, it may be more efficient to map another task to the resource in case of input providing low workload for the former and high workload for the latter. As a remedy, we propose to group inputs evoking similar workload and execution characteristics into so-called workload scenarios for which specialized mappings targeted at the common workload distribution in the scenario are provided. Optimized mappings for each scenario can be determined by a scenario-based design space exploration at design time. At run time, applications process a stream of input data whose scenario affiliation is a priori unknown. This entails two coupled tasks: First, we have to identify the scenario of the current input data based on its execution characteristics. Second, we have to choose an application mapping for processing the current input prior to its execution on the basis of the concluded scenarios of the past input and the currently active scenario-associated mapping. Note that switching between scenarios may come at a non-negligible reconfiguration cost that could decrease the advantage gained by a more suitable mapping. Both tasks are tackled by a proposed run-time reconfiguration manager, which is built on machine learning models. These models learn a strategy for identifying scenarios and selecting adequate mappings by design-time training. Here, different machine learning models are compared for their applicability. An evaluation of the run-time manager based on a ray tracing and stitching application shows significant latency improvements compared to an approach with a single mapping optimized for the average-case input.
Keywords: scenario-based dse; heterogeneous architecture; data-driven mapping; run-time manager; machine learning model

Runtime Stress-Aware Replica Placement on Reconfigurable Devices under Safety Constraints - Angermeier, Josef; Ziener, Daniel; Glaß, Michael; Teich, Jürgen (Proceedings of the International Conference on Field-Programmable Technology, 2011)
Ever shrinking device structures result in an increased susceptibility of modern embedded systems to radiation and temperature-dependent aging effects. This work introduces a runtime placement algorithm for dynamically reconfigurable systems that have to meet varying safety requirements. The algorithm first allocates replicas of modules to cope with soft-errors and meet the safety-level of the module and then places the modules onto the FPGA in such a way that the stress, and therefore aging, is minimized. For the replica allocation, a lifetime analysis is employed to predict the reliability of a module depending on its sensitive configuration bits and the expected runtime of the module. Moreover, the temperature profile of each active module is utilized to predict the degradation of each part of the reconfigurable area. The presented algorithm then equally distributes active modules to minimize the degradation effects while respecting placement constraints that arise from the need for majority voting between the different replicas of a module. A case study gives evidence of the capability of the proposed online placing algorithm to harden a system against radiation effects and meet safety constraints while extending the overall lifetime of the reconfigurable device by minimizing stress. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.runtim

Sample-Based Motion Planning for Multi-Robot Systems - Muradi, Murad; Wanka, Rolf (Proc. 6th International Conference on Control, Automation and Robotics (ICCAR), 2020)
We present a methodology for robot path planning and smoothing based on the probabilistic roadmap algorithm and simulated annealing algorithm. Furthermore, a fast and accurate collision detection and a suitable format for the abstract description of robot problems are introduced. The methods are tested on the automotive sealing process by applying them to a practical proble
Keywords: robotics; motion planning; collision detecting; path smoothing; probabilistic roadmap; simulated annealing

Sampling rate impact on energy consumption of biomedical signal processing systems - Tobola, Andreas; Streit, Franz-Josef; Espig, Chris; Korpok, Oliver; Leutheuser, Heike; Sauter, Christian; Lang, Nadine; Schmitz, Björn; Hofmann, Christian; Struck, Matthias; Weigand, Christian; Eskofier, Björn; et al. (12th International Conference on Wearable and Implantable Body Sensor Networks (BSN), 2015)
UnivIS-Import:2016-06-01:Pub.2015.tech.IMMD.IMMD5.sampli

SAS - A Framework for Symmetry-based Approximate Synthesis - Jungnitz, Niklas; Keszöcze, Oliver (Design Automation Conference, 2024)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. The latter is of special interest in the field of Internet of Things. In this paper we present SAS, a framework for symmetry-based approximate logic synthesis. Given a Boolean multi-output function, SAS approximates it by (partially) replacing its output functions by symmetric functions with minimal Hamming distance. The framework is capable of restricting the introduced error with respect to a parameterized error metric that covers many real-word use-cases. Experimental results on common benchmark sets as well as large bit width arithmetic Boolean functions confirm the effectiveness of the proposed framework. SAS is capable of synthesizing Boolean functions with size reductions of up to ≈ 45% while, at the same time, respecting the specified threshold on the error metric. The framework is publicly available as open-source software on GitHub.<br
Keywords: Approximate Computing; BDD; AIG; Optimization; Logic Synthesis

SAT-based techniques in system synthesis - Haubelt, Christian; Teich, Jürgen; Feldmann, Rainer; Monien, Burkhard (Proceedings of Design, Automation and Test in Europe (DATE 2003), 2003)
SAT-based verification of electronic systems has become very popular in recent years. In this paper, we show that SAT-techniques are also applicable and helpful during the synthesis and the optimization of a system. Therefore, we must consider two questions: (i) how to represent specifications; and (ii) how to quantify properties of embedded systems by boolean formulas. Thus, we reduce the well known binding problem to the Boolean satisfiability problem. Next, we show how to quantify the degree of fault tolerance of a system using quantified Boolean formulas (QBFs). These problems correspond to typical subroutines often used during design space exploration. We show by experiment that problem instances of reasonable size are easily solved by the QBF solver QSOLVE. © 2003 IEEE.

SAT-decoding in evolutionary algorithms for discrete constrained optimization problems - Lukasiewycz, Martin; Glaß, Michael; Haubelt, Christian; Teich, Jürgen (In Proceedings of the 2007 IEEE Congress on Evolutionary Computation (CEC 2007), 2007)
For complex optimization problems, several population-based heuristics like Multi-Objective Evolutionary Algorithms have been developed. These algorithms are aiming to deliver sufficiently good solutions in an acceptable time. However, for discrete problems that are restricted by several constraints it is mostly a hard problem to even And a single feasible solution. In these cases, the optimization heuristics typically perform poorly as they mainly focus on searching feasible solutions rather than optimizing the objectives. In this paper, we propose a novel methodology to obtain feasible solutions from constrained discrete problems in population-based optimization heuristics. At this juncture, the constraints have to be converted into the Propositional Satisfiability Problem (SAT). Obtaining a feasible solution is done by the DPLL algorithm which is the core of most modern SAT solvers. It is shown in detail how this methodology is implemented in Multi-objective Evolutionary Algorithms. The SAT solver is used to obtain feasible solutions from the genetic encoded information on arbitrarily hard solvable problems where common methods like penalty functions or repair strategies are failing. Handmade test cases are used to compare various configurations of the SAT solver. On an industrial example, the proposed methodology is compared to common strategies which are used to obtain feasible solutions. © 2007 IEEE.

Scalable ECG Hardware and Algorithms for Extended Runtime of Wearable Sensors - Tobola, Andreas; Espig, Chris; Streit, Franz-Josef; Korpok, Oliver; Leutheuser, Heike; Schmitz, Björn; Hofmann, Christian; Struck, Matthias; Weigand, Christian; Eskofier, Björn; Fischer, Georg (2015 IEEE International Symposium on Medical Measurements and Applications, 2015)
Everything in nature tries to reach the lowest possible energy level. Therefore any natural or artificial system must have the ability to adjust itself to the changing requirements of its surrounding environment. In this paper we address this issue by an ECG sensor designed to be adjustable during runtime, having the ability to reduce the power consumption at cost of the informational content. Accessible for everyone, standard ECG hardware and open source software has been used to realize an ECG processing system for wearable applications. The average power consumption has been measured for each mode of operation. Finally we take conclusion to conciser context-aware scaling as key feature to address the energy issue of wearable sensor system
UnivIS-Import:2015-07-08:Pub.2015.tech.IMMD.IMMD5.scalab

Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays - Kissler, Dmitrij; Gran, Daniel; Salcic, Zoran; Hannig, Frank; Teich, Jürgen (IEEE Embedded Systems Letters, 2011)
This letter presents a systematic approach to efficiently handle a very large number of power domains in modern coarse-grained reconfigurable arrays in order to tightly match the different computational demands of processed algorithms with corresponding power consumption. It is based on a new highly scalable and generic power control network and additionally uses the state-of-the-art common power format based front-to-backend design methodology for a fully automated implementation. The power management is transparent to the user and is seamlessly integrated into the overall reconfiguration process: reconfiguration-controlled power gating. Furthermore, for the first time, a coarse-grained reconfigurable case study design with as many as 24 switchable power domains with detailed results on power savings and overheads is presented. The application of the proposed technique results in 60% active leakage and 90% standby leakage power reduction for several digital signal processing algorithms. © 2009 IEEE.
UnivIS-Import:2015-04-14:Pub.2011.tech.IMMD.inform.scalab
Keywords: Coarse-grained reconfigurable arrays; common power format; power gating

Scenario-Based Energy Estimation of Heterogeneous Integrated Systems at System Level - Glock, Stefan; Rosales, Rafael; Reutelhuber, Franz; Glaß, Michael; Teich, Jürgen; Fischer, Georg; Weigel, Robert; Ußmüller, Thomas (Proc. 43rd European Microwave Conference, 2013)
One of the most important figures of merit concerning mobile devices is their energy efficiency. However, the modeling of such systems is mainly focused on the functional aspects, but not on the power consumption. Therefore, power estimations can only be accomplished late in the design process, after all architectural decisions have been taken. This might lead to designs that are not optimal with respect to power consumption. To overcome these limitations, this article proposes an efficient and flexible power modeling methodology at system level for heterogeneous integrated systems, allowing to combine state-dependent and environmental dependent power models. In a case study, the energy consumption of an RF transceiver of a mobile phone is estimated in a real-life scenario, including the baseband module, the radio channel, and the base transceiver station in a simulative way. © 2013 European Microwave Association.
elib2cris::1512001600,glock2013b

Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs - Spieck, Jan; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 57th Annual Design Automation Conference (DAC), 2020)

SCF - State Machine Controlled Flow Diagrams - Naedele, Martin; Strehl, Karsten; Teich, Jürgen; Thiele, Lothar; Ziegenbein, Dirk (1998)

Scheduling and communication-aware mapping of HW-SW modules for dynamically and partially reconfigurable SoC architectures - Angermeier, Josef; Fekete, Sandor P.; Göhringer, Diana; Majer, Mateusz; Teich, Jürgen; Van Der Veen, Jan C. (Proc. of the 20th International Conference on Architecture of Computing Systems, 2007)
UnivIS-Import:2015-04-16:Pub.2007.tech.IMMD.inform.schedu

Scheduling Hardware/Software Systems Using Symbolic Techniques - Ernst, Rolf; Strehl, Karsten; Teich, Jürgen; Thiele, Lothar; Ziegenbein, Dirk (Proc. CODES'99, the 7th Int. Workshop on Hardware/Software Co-Design, 1999)
In this paper, a scheduling method for heterogeneous embedded systems is developed. At first, an internal representation model called FunState is presented which enables the explicit representation of non-determinism and scheduling using a combination of functions and state machines. The new scheduling method is able to deal with mixed data/control flow specifications and takes into account different mechanisms of non-determinism as occurring in the design of embedded systems. Constraints imposed by other already implemented components are respected. The scheduling approach avoids the explicit enumeration of execution paths by using symbolic techniques and guarantees to find a deadlock-free and bounded schedule if one exists. The generated schedule consists of statically scheduled basic blocks which are dynamically called at run time.
UnivIS-Import:2015-04-16:Pub.1999.tech.IMMD.inform.schedu

Scheduling of partitioned regular algorithms on processor arrays with constrained resources - Teich, Jürgen; Thiele, Lothar; Zhang, L (Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP´96)Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP´96)Int. Conf. on Application-Specific Systems, Architectures, and Processors, 1996)
A single integer linear programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: 1) Not only constraints on the number of available processors and communication capabilities are taken into account, but also processor caches and constraints on the size of available memories are modeled and taken into account in the optimization model. 2) Different types of processors can be handled. 3) The size of the optimization model (number of integer variables) is independent of the size of the tiles to be executed. Hence, 4) the number of integer variables in the optimization model is greatly reduced such that problems of relevant size can be solved in practical execution time.
UnivIS-Import:2015-04-16:Pub.1996.tech.IMMD.inform.schedu

Scheduling Techniques for High-Throughput Loop Accelerators - Hannig, Frank (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2009)
UnivIS-Import:2015-04-02:Pub.2009.tech.IMMD.inform.schedu

Schwach-programmiert macht stark - Kissler, Dmitrij; Hannig, Frank; Teich, Jürgen (Design & Elektronik, 2007)
UnivIS-Import:2015-04-14:Pub.2007.tech.IMMD.inform.schwac

Searching RC5-Keys with Distributed Reconfigurable Computing - Koch, Dirk; Teich, Jürgen; Körber, Mathias (Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms, 2006)
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.search

Secure Boot from Non-Volatile Memory for Programmable SoC-Architectures - Streit, Franz-Josef; Fritz, Florian; Becher, Andreas; Wildermann, Stefan; Werner, Stefan; Schmidt-Korth, Martin; Pschyklenk, Michael; Teich, Jürgen (IEEE Proceedings of the 13th International Symposium on Hardware Oriented Security and Trust, 2020)
In modern embedded systems, the trust in comprehensive security standards all along the product life cycle has become an increasingly important access-to-market requirement. However, these security standards rely on mandatory immunity assumptions such as the integrity and authenticity of an initial system configuration typically loaded from Non-Volatile Memory (NVM). This applies especially to FPGA-based programmable system-on-chip (PSoC) architectures, since object codes as well as configuration data easily exceed the capacity of a secure boot ROM. In this context, an attacker could try to alter the content of the NVM device in order to manipulate the system. The PSoC therefore relies on the integrity of the NVM particularly at boot-time. In this paper, we propose a methodology for securely booting from an NVM in a potentially unsecure environment by exploiting the reconfigurable logic of the FPGA. Here, the FPGA serves as a secure anchor point by performing required integrity and authenticity verifications prior to the configuration and execution of any user application loaded from the NVM on the PSoC. The proposed secure boot process is based on the following assumptions and steps: 1) The boot configuration is stored on a fully encrypted Secure Digital memory card (SD card) or alternatively Flash acting as NVM. 2) At boot time, a hardware design called Trusted Memory-Interface Unit (TMIU) is loaded to verify first the authenticity of the deployed NVM and then after decryption the integrity of its content. To demonstrate the practicability of our approach, we integrated the methodology into the vendor-specific secure boot process of a Xilinx Zynq PSoC and evaluated the design objectives performance, power and resource cost
Keywords: Secure Boot; Non-Volatile Memory Protection; Programmable System-on-Chip; FPGA; Hardware/Software Co-Design

SEIS - Sicherheit in Eingebetteten IP-Basierten Systemen - Glaß, Michael; Herrscher, Daniel; Piastowski, Martin; Meier, Herbert; Schoo, Peter (ATZ - Automobiltechnische Zeitschrift, 2010)
UnivIS-Import:2015-03-09:Pub.2010.tech.IMMD.inform.seissi

Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics - Pirkl, Jutta; Becher, Andreas; Echavarria Gutiérrez, Jorge Alfonso; Teich, Jürgen; Wildermann, Stefan (Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017)

Self-Adaptive Hardware/Software Reconfigurable Networks - Concepts, Methods, and Implementation - Streichert, Thilo (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2008)

Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor - Paul, Johny; Stechele, Walter; Sousa, Éricles; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Kröhnert, Manfred; Asfour, Tamim (Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), 2014)
The recent years have shown the emergence of heterogeneous system architecture (HSA), which offers massive computational power assembled into a compact design. Computer vision applications with massive inherent parallelism highly benefits from such heterogeneous processors with on-chip CPU and GPU units. The highly parallel and compute intensive parts of the application program can be mapped to the GPU while the control flow and high level tasks may run on the CPU. However, they pose considerable challenge to software development due to their hybrid architecture. Sharing of resources (GPU or CPU) among applications running concurrently, leads to variations in processing interval and prolonged processing intervals leads to low quality results (frame drops) for computer vision algorithms. In this work, we propose resource-awareness and self organisation within the application layer to adapt to available resources on the heterogeneous processor. The benefits of the new model is demonstrated using a widely used computer vision algorithm called Harris corner detector. A resource-aware runtime-system and a heterogeneous processor were used for evaluation and the results indicate a well constrained processing interval and reduced frame-drops. Our evaluations demonstrate up to 20% improvements in processing rate and accuracy of the detected corner points for Harris corner detectio
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.selfad

Self-adaptive potential-based stopping criteria for Particle Swarm Optimization with forced moves - Bassimir, Bernd; Schmitt, Manuel; Wanka, Rolf (Swarm Intelligence, 2020)
We study the variant of Particle Swarm Optimization that applies random velocities in a dimension instead of the regular velocity update equations as soon as the so-called potential of the swarm falls below a certain small bound in this dimension, arbitrarily set by the user. In this case, the swarm performs a forced move. In this paper, we are interested in how, by counting the forced moves, the swarm can decide for itself to stop its movement because it is improbable to find better candidate solutions than the already-found best solution. We formally prove that when the swarm is close to a (local) optimum, it behaves like a blind-searching cloud and that the frequency of forced moves exceeds a certain, objective function-independent value. Based on this observation, we define stopping criteria and evaluate them experimentally showing that good candidate solutions can be found much faster than setting upper bounds on the iterations and better solutions compared to applying other solutions from the literature.<br
Keywords: Particle Swarm Optimization; Stopping criterion; Heuristics

Self diagnostics and isolation mechanisms for mixed criticality systems - Tellabi, Asmaa; Ruland, Christoph; Waedt, Karl; Abdelbast, Sabri (Journal of Communications Software and Systems, 2019)
Virtualization is a technology that is frequently employed in computers and servers to provide isolation for execution environments, and to support the execution of multiple Operating Systems (OS) on the same hardware platform. In the embedded systemś world, virtualization has been a rising trend, essentially because it offers an isolation mechanism that provides hardware manufactureŕ independence and it avoids obsolescence issues. The isolation mechanism supports safety and security measures, and assists in the certification of safety-critical systems. Virtualization offers improved performances, better transparency, portability and interoperability by integrating hardware and software resources, and also networking services into one computing entity. It makes the integration process of Mixed Criticality Systems (MCS) easier. For industries, Field-Programmable Gate Arrays (FPGAs) hardware solutions provide the needed level of flexibility and performance. In this paper, a Self-test application is integrated in the hardware and also in the software level. The importance of self-test applications for Instrumentation and Control (I&C) systems will be discussed in the context of virtualization. For this implementation a type 1 hypervisor called Xtratum is used. An analysis of inter-partition communication channelś performance will be provided including the implications multicore approaches will have on communication. The novelty of this work is to study the isolation impact multicore approaches can have on inter-partitions communications in Xtratum. Another novel aspect is the implementation of a self-test application in the hypervisor and the board as well.
CRIS-Team Scopus Importer:2019-12-31
Keywords: Cortex A9; FPGA; MCS; Multi-core.; Self-test; Virtualization; Xtratum

Self-Integration for Virtualization of Embedded Many-Core Systems - Wildermann, Stefan; Teich, Jürgen (Proceedings of the Workshop on Self-Improving System Integration (SISSY 2014), 2014)

Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems - Ziermann, Tobias; Salcic, Zoran; Teich, Jürgen (Proc. of the 8th International Conference on Autonomic and Trusted Computing, 2011)
A growing number of control systems are distributed and based on the use of a communication bus. The distributed nodes execute periodic tasks, which access the bus by releasing the messages using a priority-based mechanism with the goal of minimal message response times. Instead of randomly accessing the bus, a dynamic scheduling of messages technique based on adaptation of time offsets between message releases is used. The presented algorithm, called DynOAA, is executing on each node of the distributed system. It takes into account the current traffic on the bus and tries to avoid simultaneous release of messages by different nodes, hence reduces the likelihood of conflicts and need for repeated release. In this paper, we first address single bus (segment) systems and then extend the model and the offset adaptation algorithm to systems that use multiple buses (segments) connected by a communication gateway. A rating function based on the average of maximum response times is used to analyze DynOAA for the case of CAN-bus systems based on bit-accurate simulations. Experiments show the robustness of the algorithm (1) in case of fully asynchronous systems, (2) ability to deal with systems that change their configuration (add or remove message release nodes) dynamically and (3) model systems containing multiple bus segments connected by a gateway. The approach is also applicable to other priority-based bus systems. © 2011 Springer-Verlag.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.selfor

Self-Organizing Bandwidth Sharing in Priority-based Medium Access - Wildermann, Stefan; Ziermann, Tobias; Teich, Jürgen (Proc. 3rd IEEE International Conference on Self-Adaptive and Self-Organizing Systems, 2009)
In this paper, we present an analysis of self-organizing bandwidth sharing in priority-based medium access. For this purpose, the priority-based Access Game is introduced. Analysis shows that a fair distribution of bandwidth cannot be achieved in this game. Therefore, we enhance this game by introducing a constraint that demands a small amount of the overall bandwidth being free. Fair bandwidth sharing is one Nash Equilibrium of this enhanced game, but not a unique one. Based upon this theoretical analysis, a multi-agent reinforcement learning algorithm is proposed, where each agent tries to maximize its success rate for accessing the medium, while avoiding to violate the bandwidth constraint. We experimentally evaluate this mechanism for a system comprised of selfish agents. Experimental results show that the system is able to self-organize itself towards a fair distribution of bandwidth in a totally decentralized way without the need of global information or coordination. © 2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.selfor

Self-organizing computer vision for robust object tracking in smart cameras - Wildermann, Stefan; Oetken, Andreas; Teich, Jürgen; Salcic, Zoran (Proceedings of the 7th International Conference on Autonomic and Trusted Computing, 2010)
Computer vision is one of the key research topics of modern computer science and finds application in manufacturing, surveillance, automotive, robotics, and sophisticated human-machine-interfaces. These applications require small and efficient solutions which are commonly provided as embedded systems. This means that there exist resource constraints, but also the need for increasing adaptivity and robustness. This paper proposes an autonomic computing framework for robust object tracking. A probabilistic tracking algorithm is combined with the use of multi-filter fusion of redundant image filters. The system can react on unpredictable changes in the environment through self-adaptation. Due to resource constraints, the number of filters actively used for tracking is limited. By means of self-organization, the system structure is re-organized to activate filters adequate for the current context. The proposed framework is designed for, but not limited to, embedded computer vision. Experimental evaluations demonstrate the benefit of the approach. © 2010 Springer-Verlag.

Self-organizing Core Allocation - Ziermann, Tobias; Wildermann, Stefan; Teich, Jürgen (Proc. Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.selfor

Self-Organizing Multi-cue Fusion for FPGA-based Embedded Imaging - Wildermann, Stefan; Walla, Gregor; Ziermann, Tobias; Teich, Jürgen (Proc. 19th International Conference on Field-Programmable Logic and Applications, 2009)
Self-organization is a natural concept that helps complex systems to adapt themselves autonomically to their environment. In this paper, we present a self-organizing framework for multi-cue fusion in embedded imaging. This means that several simple image filters are used in combination to lead to a more robust system behavior. Human motion tracking serves as a show case. The system adapts to changes in the environment while tracking a person. Besides this, system customization can be simplified. The designer just has to select a desired set of image filters for a given task. The system then finds the appropriate parameters, e.g., the weighting of different cues. With the option of partial re-configuration, FPGAs support this type of customization. An FPGA-based prototype implementation demonstrates the feasibility of this approach. Tracking and adaptation work in real-time with 25 FPS and a resolution of 640x480. ©2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.selfor_1

(Self-)reconfigurable finite state machines: Theory and implementation - Teich, Jürgen; et al. (Proc. DATE 2002, Design, Automation and Test in Europe, 2002)
In this paper, we introduce the concept of (self-)reconfigurable finite state machines as a formal model to describe state-machines implemented in hardware that may be reconfigured during operation. By the advent of reconfigurable logic devices such as FPGAs, this model may become important to characterize and implement (self-)reconfigurable hardware. An FSM is called (self-)reconfigurable if reconfiguration of either output function or transition function is initiated by the FSM itself and not based on external reconfiguration events. We propose an efficient hardware realisation and give algorithmic solutions and bounds for the reconfiguration overhead of migrating a given FSM specification into a new target FSM. © 2002 IEEE.

Semi-Automatic Generation of mixed Hardware-Software Prototypes from Simulink Models - Streubühr, Martin; Jäntsch, Michael; Haubelt, Christian; Teich, Jürgen; Schneider, Axel (11. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2008)

Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces - Trautmann, Jens; Beckers, Arthur; Wouters, Lennert; Gierlichs, Benedikt; Wildermann, Stefan; Verbauwhede, Ingrid; Teich, Jürgen (IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2022)
Locating a cryptographic operation in a side channel trace, i.e. finding out where it is in the time domain, without having a template, can be a tedious task even for unprotected implementations. The sheer amount of data can be overwhelming. In a simple call to OpenSSL for AES-128 ECB encryption of a single data block, only 0.00028% of the trace relate to the actual AES-128 encryption. The rest is overhead. We introduce the (to our best knowledge) first method to locate a cryptographic operation in a side channel trace in a largely automated fashion. The method exploits meta information about the cryptographic operation and requires an estimate of its implementation's execution time. The method lends itself to parallelization and our implementation in a tool greatly benefits from GPU acceleration. The tool can be used offline for trace segmentation and for generating a template which can then be used online in real-time waveform-matching based triggering systems for trace acquisition or fault injection. We evaluate it in six scenarios involving hardware and software implementations of different cryptographic operations executed on diverse platforms. Two of these scenarios cover realistic protocol level use-cases and demonstrate the real-world applicability of our tool in scenarios where classical leakage-detection techniques would not work. The results highlight the usefulness of the tool because it reliably and efficiently automates the task and therefore frees up time of the analyst. The method does not work on traces of implementations protected by effective time randomization countermeasures, e.g., random delays and unstable clock frequency, but is not affected by masking, shuffling and similar countermeasures.<br

(Semi)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications - Keszöcze, Oliver; Keiner, Bettina; Richter, Matthias; Antpöhler, Gottfried; Wille, Robert (Natural Language Processing for Electronic Design Automation, 2020)
Caused by the challenges in the design of today’s hardware and software systems, tools for electronic design automation (EDA) became impressively powerful. However, these accomplishments can also be exploited in other domains. In fact, the steps of formalizing and checking legal regulations share many similarities with established EDA design steps. In this work, this is demonstrated by proposing the application of EDA tools in the domain of law processing. We propose a (semi)automatic translation of real rules and regulations into a formal representation. Afterwards, we discuss how—similar to the hardware/ software design—these formalization can be utilized in the respective domain.<br

Seque: Lean and Energy-aware Data Management for IoT Gateways - Sixdenier, Pierre-Louis André Edouard; Wildermann, Stefan; Ottens, Martin; Teich, Jürgen (IEEE International Conference on Edge Computing and Communications (EDGE), 2023)

SIDAM: A Design Space Exploration Framework for Multi-Sensor Embedded Systems Powered by Energy Harvesting - Sixdenier, Pierre-Louis André Edouard; Wildermann, Stefan; Ziegler, Daniel; Teich, Jürgen (International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII), 2022)
Multi-sensor embedded systems often consist of a central unit being responsible to manage a heterogeneous set of attached sensors. Particularly when such systems are deployed in areas without access to a static power supply, they have to be powered using energy harvesting to operate autonomously. Objectives such as availability and data loss rate depend on the set of attached sensors, the system configuration (e.g., used PV module, batteries, and data storage), as well as environmental factors such as the location of the deployed system. Moreover, also the employed energy management strategy and its parametrization severely influence the system characteristics. In fact, different strategies can lead to different tradeoffs in terms of the above objectives. In this paper we propose a design methodology to automatically explore the design space of configurations of multi-sensor embedded systems and to determine and configure the best energy management strategy for a given sensor configuration and location. Our methodology includes a real-time analysis and a simulation-based DSE to explore the design space. We investigate a case study from a biomonitoring project and demonstrate the benefits of the proposed design methodology: A system—including its configuration and energy management strategy—has to be tailored to the characteristics of the set of attached sensors and the location it operates. Else designs exhibit suboptimal characteristics when operating at sites or for sensor sets for which they were not optimized.<br

Simulating Realistic IoT Network Traffic Using Similarity-based DSE - Brand, Peter; Falk, Joachim; Maier, Tanja; Teich, Jürgen (2021 International Conference on Computational Science and Computational Intelligence (CSCI), 2021)
CRIS-Team WoS Importer:2022-08-26

Simulating shallow water waves with lazy activation of patches using ActorX10 - Pöppl, Alexander; Bader, Michael; Schwarzer, Tobias; Glaß, Michael (Proceedings of the Second International Workshop on Extreme Scale Programming Models and Middleware (ESPM2), 2016)

Simulation-based Uncertainty Correlation Modeling in Reliability Analysis - Khosravi, Faramarz; Müller, Malte; Glaß, Michael; Teich, Jürgen (Proceedings of the Institution of Mechanical Engineers, Part O: Journal of Risk and Reliability, 2018)
Due to destructive effects like temperature and radiation, today’s embedded systems have to deal with unreliable components. The intensity of these effects depends on uncertain aspects like environmental or usage conditions such that highly safety-critical systems are pessimistically designed for worst-case mission profiles. These uncertain aspects may affect several components simultaneously, implying correlation across uncertainties in their reliability. This paper enables a state-of-the-art uncertainty-aware reliability analysis technique to consider multiple arbitrary correlations, i. e. components’ reliability is affected by several uncertain aspects to different degrees. This analysis technique combines reliability models such as binary decision diagrams with a Monte Carlo simulation, and derives the uncertainty distribution of the system’s reliability with insights on mean, quantile intervals, etc. The proposed correlation method aims at generating correlated samples from the uncertainty distribution of components’ reliability such that the shape and statistical properties of each individual distribution remain unchanged. Experimental results confirm that the proposed correlation model enables the employed uncertainty-aware analysis to accurately calculate uncertainty at system leve
Keywords: Reliability analysis; uncertainty correlation modeling; Monte Carlo simulation; system-level design

Simulation of Resource-Aware Applications on Heterogeneous Architectures - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Proc. of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), 2012)
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.simula

Simulative buffer analysis of local image processing algorithms described by windowed synchronous data flow - Keinert, Joachim; Haubelt, Christian; Teich, Jürgen (Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Acoustics, Speech, and Signal Processing (IC-SAMOS VII), 2007)
Embedded real-time image processing applications working on large images have to process and store huge amounts of data. Consequently the organization of the memory buffers and the precise determination of the required buffer sizes are critical steps for efficient system implementation. In this paper, we propose a new method, that permits the analysis to be performed automatically for local image processing algorithms. The latter ones are specified by help of the Windowed Synchronous Data Flow (WSDF) model, a multi-dimensional model of computation which has been especially designed to represent local image processing algorithms. This paper introduces a corresponding buffer organization leading to solutions comparable to hand-built designs concerning the required memory. Special care is taken, so that also large problems in terms of the image size can be analyzed. The applicability of our approach is demonstrated by help of a JPEG2000 decoder model. © 2007 IEEE.

SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation - Plagwitz, Patrick; Hannig, Frank; Teich, Jürgen; Keszöcze, Oliver (Proceedings of the 20th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024)
Convolutional Neural Networks (CNNs) are widely employed to solve various problems, e.g., image classification. Due to their compute- and data-intensive nature, CNN accelerators have been developed as ASICs or on FPGAs. The increasing complexity of applications has caused resource costs and energy requirements of these accelerators to grow. Spiking Neural Networks (SNNs) are an emerging alternative to CNN implementations, promising higher resource and energy efficiency. The main research question addressed in this paper is whether SNN accelerators truly meet these expectations of reduced energy demands compared to their CNN equivalents when implemented on modern FPGAs. For this purpose, we analyze multiple SNN hardware accelerators for FPGAs regarding performance and energy efficiency. We also present a novel encoding scheme of spike event queues and a novel memory organization technique to improve SNN energy efficiency further. Both techniques have been integrated into a state-of-the-art SNN architecture and evaluated for MNIST, SVHN, and CIFAR-10 data sets and corresponding network architectures on two differently sized modern FPGA platforms. A result of our empirical analysis is that for complex benchmarks such as SVHN and CIFAR-10, SNNs do live up to their expectations.<br

Social Interaction in Particle Swarm Optimization, the Ranked FIPS, and Adaptive Multi-Swarms - Jordan, Johannes Michael; Helwig, Sabine; Wanka, Rolf (Proceedings of the Genetic and Evolutionary Computation Conference, 2008)

Solving hierarchical optimization problems using MOEAs - Teich, Jürgen; Haubelt, Christian; Mostaghim, Sanaz; Tyagi, Ambrish (Evolutionary Multi-Criterion Optimization, 2003)
In this paper, we propose an approach for solving hierarchical multi-objective optimization problems (MOPs). In realistic MOPs, two main challenges have to be considered: (i) the complexity of the search space and (ii) the non-monotonicity of the objective-space. Here, we introduce a hierarchical problem description (chromosomes) to deal with the complexity of the search space. Since Evolutionary Algorithms have been proven to provide good solutions in non-monotonic objective-spaces, we apply genetic operators also on the structure of hierarchical chromosomes. This novel approach decreases exploration time substantially. The example of system synthesis is used as a case study to illustrate the necessity and the benefits of hierarchical optimization. © Springer-Verlag Berlin Heidelberg 2003.

Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study - Afzal, Ayesha; Schmitt, Christian; Alhaddad, Samer; Grynko, Yevgen; Teich, Jürgen; Förstner, Jens; Hannig, Frank (Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018)
In scientific computing, unstructured meshes are a crucial foundation for the simulation of real-world physical phenomena. Compared to regular grids, they allow resembling the computational domain with a much higher accuracy, which in turn leads to more efficient computations. There exists a wealth of supporting libraries and frameworks that aid programmers with the implementation of applications working on such grids, each built on top of existing parallelization technologies. However, many approaches require the programmer to introduce a different programming paradigm into their application or provide different variants of the code. SYCL is a new programming standard providing a remedy to this dilemma by building on standard C ++17 with its so-called single-source approach: Programmers write standard C ++ code and expose parallelism using C++17 keywords. The application is then transformed into a concrete implementation by the SYCL implementation. By encapsulating the OpenCL ecosystem, different SYCL implementations enable not only the programming of CPUs but also of heterogeneous platforms such as GPUs or other devices. For the first time, this paper showcases a SYCL-based solver for the nodal Discontinuous Galerkin method for Maxwell’s equations on unstructured meshes. We compare our solution to a previous C-based implementation with respect to programmability and performance on heterogeneous platforms.<br

Solving multi-objective Pseudo-Boolean problems - Lukasiewycz, Martin; Glaß, Michael; Haubelt, Christian; Teich, Jürgen (Proceedings of Tenth International Conference on Theory and Applications of Satisfiability Testing (SAT 2007), 2007)
Integer Linear Programs are widely used in areas such as routing problems, scheduling analysis and optimization, logic synthesis, and partitioning problems. As many of these problems have a Boolean nature, i.e., the variables are restricted to 0 and 1, so called Pseudo-Boolean solvers have been proposed. They are mostly based on SAT solvers which took continuous improvements over the past years. However, Pseudo-Boolean solvers are only able to optimize a single linear function while fulfilling several constraints. Unfortunately many real-world optimization problems have multiple objective functions which are often conflicting and have to be optimized simultaneously, resulting in general in a set of optimal solutions. As a consequence, a single-objective Pseudo-Boolean solver will not be able to find this set of optimal solutions. As a remedy, we propose three different algorithms for solving multi-objective Pseudo-Boolean problems. Our experimental results will show the applicability of these algorithms on the basis of several test cases. © Springer-Verlag Berlin Heidelberg 2007.

Sorting on a massively parallel system using a library of basic primitives: Modeling and experimental results - Wachsmann, Alf; Wanka, Rolf (Proc 3rd International Conference on Parallel Processing (Euro-Par), 1997)
We present a comparative study of implementations of the following sorting algorithms on the Parsytec SC320 reconflgurable, asynchronous, massively parallel MIMD machine: Bitonic Sort, Odd-Even Merge Sort, Odd-Even Merge Sort with guarded split&merge. and two variants of Samplesort. The experiments are performed on 2- up to 5-dimensional wrapped butterfly networks with 8 up to 160 processors. We make use of library functions that provide primitives for global variables and synchronization, and we show that it is possible to implement efficient and portable programs easily. In order to predict the performance, we model the runtime of an access to a global variable by a certain trilinear function and the runtime of a synchronization by a certain bilinear function. Our experiments show that, in the context of parallel sorting, this model that can be applied easily is sufficiently detailed to give good runtime predictions. The experiments confirming the predictions point out that Odd-Even Merge Sort with guarded split&merge is the fastest method if the processors hold few keys. If there are many keys per processor, a combination of Samplesort and Odd-Even Merge Sort is the fastest method.

Spatiotemporal modeling of first and second wave outbreak dynamics of COVID‐19 in Germany - Lippold, Dorothee; Kergaßner, Andreas; Burkhardt, Christian; Kergaßner, Matthias; Loos, Jonas; Nistler, Sarah; Steinmann, Paul; Budday, Dominik; Budday, Silvia (Biomechanics and Modeling in Mechanobiology, 2021)
The COVID-19 pandemic has kept the world in suspense for the past year. In most federal countries such as Germany, locally varying conditions demand for state- or county-level decisions to adapt to the disease dynamics. However, this requires a deep understanding of the mesoscale outbreak dynamics between microscale agent models and macroscale global models. Here, we use a reparameterized SIQRD network model that accounts for local political decisions to predict the spatiotemporal evolution of the pandemic in Germany at county resolution. Our optimized model reproduces state-wise cumulative infec- tions and deaths as reported by the Robert Koch Institute and predicts the development for individual counties at convincing accuracy during both waves in spring and fall of 2020. We demonstrate the dominating effect of local infection seeds and identify effective measures to attenuate the rapid spread. Our model has great potential to support decision makers on a state and community politics level to individually strategize their best way forward during the months to come.
Keywords: COVID-19 · SIQRD model · Mesoscale outbreak dynamics · Germany

SPEAR-JSON: Selective parsing of JSON to enable accelerated stream processing on FPGAs - Hahn, Tobias; Wildermann, Stefan; Teich, Jürgen (IEEE Proceedings of the 33rd International Conference on Field Programmable Logic and Applications, 2023)
Big Data applications frequently involve the processing of data streams encoded in semi-structured data formats such as JSON. A major challenge is that the parsing of such data formats is usually highly complex. Accelerating JSON parsing on FPGAs has therefore become a focus of recent research. FPGA accelerators were presented which serve as a co-processor for a CPU to convert JSON into a format that is easier for the CPU to process, e.g., Apache Arrow. However, in case the parsed data should be further processed on the FPGA, such solutions are insufficient as the format created is unsuitable for further processing on FPGAs and, above all, because the accelerators have an immense resource requirement. We, therefore, present a novel FPGA parser architecture that is able to interpret JSON data to selectively extract attributes based on a query expression into a format suitable for stream processing on the FPGA. We furthermore show how the sparsity of JSON can be used to implement a resource-efficient design, only requiring few FPGA resources. This leaves the major share of resources free for accelerating subsequent processing steps of a given application. Our experimental evaluation shows that we can achieve a throughput of 36.5 MB/s per kLUTs which is about 2.5 times higher than the throughput per LUT achievable on the most efficient related approach.
Keywords: JSON; FPGA; parsing; architecture

Special Issue on Applied Reconfigurable Computing - Hannig, Frank; Derrien, Steven (Journal of Signal Processing Systems, 2022)
CRIS-Team WoS Importer:2022-09-02

Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems - Bosio, Alberto; Barbareschi, Mario; Savino, Alessandro; Han, Jie; Teich, Jürgen (IEEE Design & Test, 2023)

Special Issue on Heterogeneous Real-Time Image Processing - Fey, Dietmar; Hannig, Frank (Journal of Real-Time Image Processing, 2018)

Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications - Henkel, Jörg; Sidduh, Lokesh; Bauer, Lars; Teich, Jürgen; Wildermann, Stefan; Tahoori, Mehdi B.; Mayahinia, Mahta; Castrillon, Jeronimo; Khan, Asif Ali; Farzaneh, Hamid; de Lima, João Paulo C.; Chen, Jian-Jia; et al. (Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), 2023)
This paper explores the challenges and opportunities of integrating non-volatile memories (NVMs) into embedded systems for ma- chine learning. NVMs offer advantages such as increased memory density, lower power consumption, non-volatility, and compute-in- memory capabilities. The paper focuses on integrating NVMs into embedded systems, particularly in intermittent computing, where systems operate during periods of available energy. NVM technolo- gies bring persistence closer to the CPU core, enabling efficient designs for energy-constrained scenarios. Next, computation in re- sistive NVMs is explored, highlighting its potential for accelerating machine learning algorithms. However, challenges related to relia- bility and device non-idealities need to be addressed. The paper also discusses memory-centric machine learning, leveraging NVMs to overcome the memory wall challenge. By optimizing memory lay- outs and utilizing probabilistic decision tree execution and neural network sparsity, NVM-based systems can improve cache behavior and reduce unnecessary computations. In conclusion, the paper emphasizes the need for further research and optimization for the widespread adoption of NVMs in embedded systems presenting relevant challenges, especially for machine learning applications. <br
Keywords: Non Volatile Memories; Machine Learning; Compute In Memory; Design Space Exploration

Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System - Beena Gopalakrishnan Nair, Lekshmi; Becher, Andreas; Wildermann, Stefan; Meyer-Wegener, Klaus; Teich, Jürgen (Datenbank-Spektrum, 2021)
FPGAs are promising target architectures for hardware acceleration of database query processing, as they combine the performance of hardware with the programmability of software. In particular, they are partially reconfigurable at runtime, which allows for the runtime adaptation to a variety of queries. However, reconfiguration costs some time, and a region of the FPGAis not available for computations during its reconfiguration. Techniques to avoid or at least hide the reconfiguration latencies can improve the overall performance. This paper presents optimizations based on query look-ahead, which follows the idea of exploiting knowledge about subsequent queries for scheduling the reconfigurations such that their overhead is minimized. We evaluate our optimizations with a calibrated model for various parameter settings. Improvements in execution time can be “calculated" even if only being able to look one query ahea
Keywords: Query optimization - Hardware acceleration - Reconfiguration - FPGAs

Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead - Ahmadinia, Ali; Teich, Jürgen (Proceedings of the IFIP International Conference on VLSI-SOC, 2003)
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.speedi

SPI - An Internal Representation for Heterogeneously Specified Embedded Systems - Ernst, Rolf; Richter, Kai; Teich, Jürgen; Thiele, Lothar; Ziegenbein, Dirk (Proc. GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 1999)
UnivIS-Import:2015-04-16:Pub.1999.tech.IMMD.inform.spiani

SPI - A System Model for Heterogeneously Specified Embedded Systems - Teich, Jürgen; Ernst, Rolf; Richter, Kai; Thiele, Lothar; Ziegenbein, Dirk (IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 2002)
Embedded systems typically include reactive and transformative functions, often described in different languages and semantics which are well established in their respective application domains. Additionally, a large part of the system functionality and components is reused from previous designs including legacy code. There is little hope that a single language will replace this heterogeneous set of languages. A design process must be able to bridge the semantic differences for verification and synthesis and should account for limited knowledge of system properties. This paper presents the system property intervals (SPI) model, which employs behavioral intervals and process modes to allow the common representation of different languages and semantics. This model is the basis of a workbench which is targeted at the design of heterogeneously specified embedded systems.
UnivIS-Import:2015-03-09:Pub.2002.tech.IMMD.inform.spiasy
Keywords: Embedded systems design automation; Function variants; Multilanguage design; Process modes; Property intervals; System modeling

SPI Workbench - Entwurf gemischt reaktiv/transformativer Systeme - Ernst, Rolf; Richter, Kai; Teich, Jürgen; Ziegenbein, Dirk (AES 2000, Workshop Architekturentwurf für eingebettete Systeme, 2000)
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.spiwor

SPI-Workbench – Modellierung, Analyse und Optimierung eingebetteter Systeme - Haubelt, Christian; Jersak, Marek; Richter, Kai; Strehl, Karsten; Ziegenbein, Dirk; Ernst, Rolf; Teich, Jürgen; Thiele, Lothar (Proceedings of INFORMATIK 2005 - Informatik LIVE, 2005)

SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide - Beena Gopalakrishnan Nair, Lekshmi; Becher, Andreas; Meyer-Wegener, Klaus; Wildermann, Stefan; Teich, Jürgen (Proceedings of EDBT, 2020)

Stochastic Timing Analysis of Communicating Tasks with Internal State - Teich, Jürgen (2006)

Strategies for finding good local guides in multi-objective particle swarm optimization - Mostaghim, Sanaz; Teich, Jürgen (Proceedings of the Swarm Intelligence Symposium, 2003)
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.strate

Strategies for finding good local guides in multi-objective particle swarm optimization (MOPSO) - Mostaghim, Sanaz; Teich, Jürgen (2003 IEEE Swarm Intelligence Symposium, SIS 2003, 2013)
In multi-objective particle swarm optimization (MOPSO) methods, selecting the best local guide (the global best particle) for each particle of the population from a set of Pareto-optimal solutions has a great impact on the convergence and diversity of solutions, especially when optimizing problems with high number of objectives. This paper introduces the Sigma method as a new method for finding best local guides for each particle of the population. The Sigma method is implemented and is compared with another method, which uses the strategy of an existing MOPSO method for finding the local guides. These methods are examined for different test functions and the results are compared with the results of a multi-objective evolutionary algorithm (MOEA).
Keywords: Computational modeling; Evolutionary computation; Iterative methods; Optimization methods; Particle swarm optimization; Search methods; Stochastic processes; Testing

Stress-Aware Module Placement on Reconfigurable Devices - Angermeier, Josef; Ziener, Daniel; Glaß, Michael; Teich, Jürgen (Proceedings of the International Conference on Field-Programmable Logic and Applications, 2011)
A lot of research has been spent on improving the reliability and extending the lifetime of ASIC and SoC devices, but only little on improving the long-term reliability of dynamically reconfigurable systems. In order to increase the lifetime of a reconfigurable device, we propose a placement strategy to distribute the stress equally on the reconfigurable resources at runtime such that all have a similar level of degradation. Thereby, we present a new aging model which is applied to estimate the influence of aging effects on dynamically reconfigurable devices, and which can be evaluated at runtime, while providing quite accurate aging results. Furthermore, we present a new stress-aware placement algorithm that takes the degradation of the reconfigurable resources into account and can significantly extend the lifetime of reconfigurable devices. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.stress

Strongly Adaptive Token Distribution - Wanka, Rolf; et al. (Algorithmica, 1996)
The token distribution (TD) problem, an abstract static variant of load balancing, is defined as follows: let M be a (parallel processor) network with set P of processors. Initially, each processor P ∈ P has a certain amount l(P) of tokens. The goal of a TD algorithm, run on M, is to distribute the tokens evenly among the processors. In this paper we introduce the notion of strongly adaptive TD algorithms, i.e., algorithms whose running times come close to the best possible runtime, the off-line complexity of the TD problem, for each individual initial token distribution l. Until now, only weakly adaptive algorithms have been considered, where the running time is measured in terms of the maximum initial load maxl(P)|P ∈ P. We design an almost optimal, strongly adaptive algorithm on mesh-connected networks of arbitrary dimension extended by a single 1-bit bus. This result shows that an on-line TD algorithm can come close to the optimal (off-line) bound for each individual initial load. Furthermore, we exactly characterize the off-line complexity of arbitrary initial token distributions on arbitrary networks. As an intermediate result, we design almost optimal weakly adaptive algorithms for TD on mesh-connected networks of arbitrary dimension.
Keywords: Parallel algorithms; Token distribution

Supervised Learning Grant Prediction for Cellular Mobile Device Power Savings - Ah Sue, Jonathan (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2021)

Supporting Composition in Symbolic System Synthesis - Haubelt, Christian; Neubauer, Kai; Glaß, Michael (International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS), 2016)

Swarm Intelligence - Wanka, Rolf (it - Information Technology, 2019)

SYCL Code Generation for Multigrid Methods - Groth, Stefan; Schmitt, Christian; Teich, Jürgen; Hannig, Frank (22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES '19), 2019)
Multigrid methods are fast and scalable numerical solvers for partial differential equations (PDEs) that possess a large design space for implementing their algorithmic components. Code generation approaches allow formulating multigrid methods on a higher level of abstraction that can then be used to derive a problem- and hardware-specific solutions. Since these problems have a considerable implementation variability, it is crucial to investigate a general mapping of core components in multigrid methods to the target software. With SYCL there exists a high-level C++ abstraction layer that is capable of targeting a multitude of architectures. We contribute a general way to map multigrid components to SYCL functionality and provide a performance evaluation for specific algorithmic components.
Keywords: Code generation; SYCL; Multigrid methods

Symbiose von Hardware und Software - Teich, Jürgen (2000)
UnivIS-Import:2015-03-09:Pub.2000.tech.IMMD.inform.symbio

Symbiose von Hardware und Software - Teich, Jürgen (Hardware/Software Codesign, 2001)
UnivIS-Import:2015-04-20:Pub.2001.tech.IMMD.inform.symbio

Symbolic archive representation for a fast nondominance test - Lukasiewycz, Martin; Glaß, Michael; Haubelt, Christian; Teich, Jürgen (4th International Conference on Evolutionary Multi-Criterion Optimization, EMO 2007, 2007)
Archives are used in Multi-Objective Evolutionary Algorithms to establish elitism. Depending on the optimization problem, an unconstrained archive may grow to an immense size. With the growing number of nondominated solutions in the archive, testing a new solution for nondominance against this archive becomes the main bottleneck during optimization. As a remedy to this problem, we will propose a new data structure on the basis of Binary Decision Diagrams (BDDs) that permits a nondominance test with a runtime that is independent from the archive size. For this purpose, the region in the objective space weakly dominated by the solutions in the archive is represented by a BDD. We will present the algorithms for constructing the BDD as well as the nondominance test. Moreover, experimental results from using this symbolic data structure will show the efficiency of our approach in test cases where many candidates have to be tested but only few have to be added to the archive. © Springer-Verlag Berlin Heidelberg 2007.

Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems - Wildermann, Stefan; Reimann, Felix; Ziener, Daniel; Teich, Jürgen (Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, part of ESWeek'11, 2011)
In today's complex embedded systems not all applications are running all the time, but depend on the operational mode. By incorporating knowledge about the temporal behavior of such multi-mode systems, it is possible to share hardware by means of partial reconfiguration, and thus, reduce costs and improve performance. In this paper, we specify the temporal behavior of the functionality by applying known models based on state machines. In addition, we introduce an architectural model that allows to express the characteristics of nowadays partially reconfigurable architectures, focusing on FPGAs. We develop a symbolic encoding of this novel system specification, which allows to perform a unified system synthesis for allocation, binding, placement of partially reconfigurable modules, and routing the on-chip communication. The proposed encoding enables the use of sophisticated optimization techniques, coupling a SAT solver with a Multi-objective Evolutionary Algorithm. The proposed methodology is highly applicable for building multi-mode systems on advanced reconfigurable technology. We demonstrate this by experiments on test-cases from the image processing domain applying state-of-the-art technology. The results show the superiority of the presented approach in terms of run-time and quality of the found solutions compared to existing system synthesis approaches. Copyright 2011 ACM.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.symbol_5

Symbolic inner loop parallelisation for massively parallel processor arrays - Tanase, Alexandru-Petru; Witterauf, Michael; Teich, Jürgen; Hannig, Frank (Proceedings of the 12th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), 2014)
This paper presents a first solution to the unsolved problem of symbolically scheduling a given loop nest with uniform data dependences using inner loop parallelization, in particular, the locally parallel, globally sequential (LPGS) mapping technique. This technique is needed in the case of loop program specifications for which the iterations shall be scheduled on a processor array of unknown size at compile time while keeping the local memory consumption independent of the problem size of the mapped loop nest. We show that it is possible to derive such parameterized LPGS schedules statically by proposing a mixed compile-/runtime approach: At compile time, we first determine the set of all schedule candidates, each latency-optimal for a different scanning order of the loop nest. Then we devise an exact parameterized formula for determining the latency of the resulting symbolic schedules, thus making each schedule fully predictable. At runtime, once the size of the processor array becomes known, a simple prolog selects the overall latency-optimal schedule that is then dynamically activated and executed on the processor array. Hence, our approach avoids any further runtime optimization and expensive re-compilations while achieving the same results as computing an optimal static schedule for each possible combination of array and problem size.

Symbolic Loop Compilation for Tightly Coupled Processor Arrays - Witterauf, Michael; Walter, Dominik; Hannig, Frank; Teich, Jürgen (ACM Transactions on Embedded Computing Systems, 2021)
Tightly Coupled Processor Arrays (TCPAs), a class of massively parallel loop accelerators, allow applications to offload computationally expensive loops for improved performance and energy efficiency. To achieve these two goals, executing a loop on a TCPA requires an efficient generation of specific programs as well as other configuration data for each distinct combination of loop bounds and number of available processing elements (PEs). Since both these parameters are generally unknown at compile time—the number of available PEs due to dynamic resource management, and the loop bounds because they depend on the problem size—, both the programs and configuration data must be generated at runtime. However, pure just-in-time compilation is impractical because mapping a loop program onto a TCPA entails solving multiple NP-complete problems. As a solution, this article proposes a a unique mixed static/dynamic approach called symbolic loop compilation. It is shown that at compile time, the NP-complete problems (modulo scheduling, register allocation, and routing) can still be solved to optimality in a symbolic way resulting in a so-called symbolic configuration, a space-efficient intermediate representation parameterized in the loop bounds and number of PEs. This phase is called symbolic mapping. At runtime, for each requested accelerated execution of a loop program with given loop bounds and known number of available PEs, a concrete configuration, including PE programs and configuration data for all other components, is generated from the symbolic configuration according to these parameter values. This phase is called instantiation. We describe both phases in detail and show that instantiation runs in polynomial time with its most complex step, program instantiation, not directly depending on the number of PEs and thus scaling to arbitrary sizes of TCPAs. To validate the efficiency of this mixed static/dynamic compilation approach, we apply symbolic loop compilation to a set of real-world loop programs from several domains, measuring both compilation time and space requirements. Our experiments confirm that a symbolic configuration is a space-efficient representation suited for systems with little memory—in many cases, a symbolic configuration is smaller than even a single concrete configuration instantiated from it—and that the times for the run-time phase of program instantiation and configuration loading are negligible and moreover independent of the size of the available processor array. To give an example, instantiating a configuration for a matrix-matrix multiplication benchmark takes equally long for 4x4 and 32x32 PEs.

Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays - Tanase, Alexandru-Petru; Witterauf, Michael; Hannig, Frank; Teich, Jürgen (Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), 2015)
Loop parallelization techniques for massively parallel processor arrays using one-level tiling are often either I/O- or memory-bounded, exceeding the target architecture's capabilities. Furthermore, if the number of available processing elements is only known at runtime - as in adaptive systems - static approaches fail. To solve these problems, we present a hybrid compile/runtime technique to symbolically parallelize loop nests with uniform dependences on multiple levels. At compile time, two novel transformations are performed: (a) symbolic hierarchical tiling followed by (b) symbolic multi-level scheduling. By tuning the size of the tiles on multiple levels, a trade-off between the necessary I/O-bandwidth and memory is possible, which facilitates obeying resource constraints. The resulting schedules are symbolic with respect to the number of tiles; thus, the number of processing elements to map onto does not need to be known at compile time. At runtime, when the number is known, a simple prolog chooses a feasible schedule with respect to I/O and memory constraints that is latency-optimal for the chosen tile size. In this way, our approach dynamically chooses latency-optimal and feasible schedules while avoiding expensive re-compilations.
Keywords: Mathematical model; Memory management; Processor scheduling; Runtime; Schedules; Silicon

Symbolic loop parallelization of static control programs - Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Proc. of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), 2012)
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.symbol

Symbolic Mapping of Loop Programs onto Processor Arrays - Teich, Jürgen; Tanase, Alexandru-Petru; Hannig, Frank (Journal of Signal Processing Systems, 2014)
In this paper, we present a solution to the problem of joint tiling and scheduling a given loop nest with uniform data dependencies symbolically. This challenge arises when the size and number of available processors for parallel loop execution is not known at compile time. But still, in order to avoid any overhead of dynamic (run-time) recompilation, a schedule of loop iterations shall be computed and optimized statically. In this paper, it will be shown that it is possible to derive parameterized latency-optimal schedules statically by proposing a two step approach: First, the iteration space of a loop program is tiled symbolically into orthotopes of parametrized extensions. Subsequently, the resulting tiled program is also scheduled symbolically, resulting in a set of latency-optimal parameterized schedule candidates. At run time, once the size of the processor array becomes known, simple comparisons of latency-determining expressions finally steer which of these schedules will be dynamically selected and the corresponding program configuration executed on the resulting processor array so to avoid any further run-time optimization or expensive recompilation. Our theory of symbolic loop parallelization is applied to a number of loop programs from the domains of signal processing and linear algebra. Finally, as a proof of concept, we demonstrate our proposed methodology for a massively parallel processor array architecture called tightly coupled processor array (TCPA) on which applications may dynamically claim regions of processors in the context of invasive computing.
UnivIS-Import:2015-04-20:Pub.2014.tech.IMMD.inform.symbol_0
Keywords: Symbolic Loop Parallelisation

Symbolic Message Routing for Multi-Objective Optimization of Automotive E/E Architecture Component Platforms - Graf, Sebastian; Glaß, Michael; Teich, Jürgen (Proceedings of 18. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015), 2015)

Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays - Tanase, Alexandru-Petru; Witterauf, Michael; Teich, Jürgen; Hannig, Frank (ACM Transactions on Embedded Computing Systems, 2017)

Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays - Teich, Jürgen; Tanase, Alexandru-Petru; Hannig, Frank (Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, 2013)
In this paper, we present a first solution to the unsolved problem of joint tiling and scheduling a given loop nest with uniform data dependencies symbolically. This problem arises for loop programs for which the iterations shall be optimally scheduled on a processor array of unknown size at compile-time. Still, we show that it is possible to derive parameterized latency-optimal schedules statically by proposing two new program transformations: In the first step, the iteration space is tiled symbolically into orthotopes of parametrized extensions. The resulting tiled program is subsequently scheduled symbolically. Here, we show that the maximal number of potential optimal schedules is upper bounded by 2n n! where n is the dimension of the loop nest. However, the real number of optimal schedule candidates being much less than this. At run-time, once the size of the processor array becomes known, simple comparisons of latency-determining expressions finally steer which of these schedules will be dynamically activated and the corresponding program configuration executed on the resulting processor array so to avoid any further run-time optimization or expensive recompilations. © 2013 IEEE.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.symbol

Symbolic Parallelization of Nested Loop Programs - Tanase, Alexandru-Petru (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2017)

Symbolic Parallelization of Nested Loop Programs - Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Springer, 2018)

Symbolic quasi-static scheduling of actor-oriented SystemC models - Gladigau, Jens; Haubelt, Christian; Teich, Jürgen (Proceedings of Forum on specification & Design Languages 2008 (FDL08), 2008)
In this paper, we propose a quasi-static scheduling (QSS) method applicable to actor-oriented SystemC designs. QSS determines a schedule where several static schedules are combined in a dynamic schedule to reduce runtime overhead. This is done by performing as much static scheduling as possible at compile time, and only treating data-dependent control flow as runtime decision. Our approach improves known quasi-static approaches in a way that it is directly applicable to real world designs, and has less restrictions on the underlying model. The effectiveness of the approach based on symbolic computation is demonstrated by scheduling a SystemC design of a network packet filter. © 2008 IEEE.

Symbolic reliability analysis and optimization of ECU networks - Glaß, Michael; Lukasiewycz, Martin; Reimann, Felix; Haubelt, Christian; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE 2008), 2008)
Increasing reliability at a minimum amount of extra cost is a major challenge in todays ECU network design. Considering reliability as an objective already in early design phases has the potential to avoid expensive modifications in later design phases. Hence, there is a need for an appropriate optimization process and efficient analysis techniques to evaluate the found implementations. In this paper, we will show how symbolic techniques can be used to efficiently analyze and optimize such reliable systems. The contribution of this paper is (1) a symbolic reliability analysis that makes use of a partitioned structure function and (2) a symbolic optimization process based on binary ILP solvers. Our case study from the automotive area will show a significant speed-up using our analysis technique. Moreover, our optimization approach is able to offer implementations with considerably improved reliability at no additional costs as well as implementations with reduced costs without decreasing their reliability. © 2008 EDA

Symbolic reliability analysis of self-healing networked embedded systems - Glaß, Michael; Lukasiewycz, Martin; Reimann, Felix; Haubelt, Christian; Teich, Jürgen (Proceedings of the 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP 2008), 2008)
In recent years, several network online algorithms have been studied that exhibit self-x properties such as self-healing or self-adaption. These properties are used to improve systems characteristics like, e.g., fault-tolerance, reliability, or load-balancing. In this paper, a symbolic reliability analysis of self-healing networked embedded systems that rely on self-reconfiguration and self-routing is presented. The proposed analysis technique respects resource constraints such as the maximum computational load or the maximum memory size, and calculates the achievable reliability of a given system. This analytical approach considers the topology of the system, the properties of the resources, and the executed applications. Moreover, it is independent of the used online algorithms that implement the self-healing properties, but determines the achievable upper bound for the systems reliability. Since this analysis is not tailored to a specific online algorithm, it allows a reasonable decision making on the used algorithm by enabling a rating of different self-healing strategies. Experimental results show the effectiveness of the introduced technique even for large networked embedded systems. © 2008 Springer-Verlag Berlin Heidelberg.

Symbolic scheduling of SystemC dataflow designs - Gladigau, Jens; Haubelt, Christian; Teich, Jürgen (Languages for Embedded Systems and their Applications, 2009)
In this chapter, we propose a quasi-static scheduling (QSS) method applicable to SystemC dataflow designs. QSS determines a schedule where several static schedules are combined in a dynamic schedule. This, among others, reduces runtime overhead. QSS is done by performing as much static scheduling as possible at compile time, and only treating data-dependent control flow as runtime decision. Our approach improves known quasi-static approaches in a way that it is automatically applicable to real world designs, and has less restrictions on the underlying model. The effectiveness of the approach based on symbolic computation is demonstrated by scheduling a SystemC design of a network packet filter. © 2009 Springer Science+Business Media B.V.
Keywords: Quasi-static; Software scheduling; Symbolic methods; SystemC

Symbolic System-level Design Methodology for Multi-Mode Reconfigurable Systems - Wildermann, Stefan; Reimann, Felix; Ziener, Daniel; Teich, Jürgen (Design Automation For Embedded Systems, 2012)
Modern embedded systems provide a variety of functionality as operational modes, each corresponding to a mutually exclusive phase of operation. This paper provides a system level design methodology tailored for such multi-mode systems. By incorporating knowledge about the temporal behavior, it is possible to share hardware by means of partial reconfiguration on sophisticated Field Programmable Gate Arrays (FPGAs), and thus, reduce costs and improve performance. The presented methodology is based on an exploration model, which specifies the temporal behavior of the system functionality as well as the architectural characteristics of nowadays reconfigurable technology. We develop a symbolic encoding of this system specification, which enables unified system synthesis by applying sophisticated optimization techniques to perform allocation, binding, placement of partially reconfigurable modules, and routing the on-chip communication. The presented system-level design methodology complies with the state-of-the-art synthesis tools and communication technologies for partially reconfigurable systems. We demonstrate this by experiments on test cases from the image processing domain applying state-of-the-art technology. The results give evidence of the efficiency of the methodology and show the superiority in terms of runtime and quality of the found solutions compared to existing system-level synthesis approaches. © 2012 Springer Science+Business Media New York.
UnivIS-Import:2015-03-09:Pub.2012.tech.IMMD.inform.symbol_0
Keywords: Design space exploration; Field-programmable gate arrays; Partial reconfiguration; System level design

Symbolic system level reliability analysis - Glaß, Michael; Lukasiewycz, Martin; Reimann, Felix; Haubelt, Christian; Teich, Jürgen (Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2010)
More and more embedded systems provide a multitude of services, implemented by a large number of networked hardware components. In early design phases, dimensioning such complex systems in terms of monetary costs, power consumption, reliability etc. demands for new analysis approaches at the electronic system level. In this paper, two symbolic system level reliability analysis approaches are Introduced. First, a formal approach based on Binary Decision Diagrams is presented that allows to calculate exact reliability measures for small to moderatesized systems. Second, a simulative approach is presented that hybridizes a Monte Carlo simulation with a SAT solver and delivers adequate approximations of the reliability measures for large and complex systems. ©2010 IEEE.

Symbolic system synthesis in the presence of stringent real-time constraints - Reimann, Felix; Lukasiewycz, Martin; Glaß, Michael; Haubelt, Christian; Teich, Jürgen (2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011, 2011)
Stringent real-time constraints lead to complex search spaces containing only very few or even no valid implementations. Hence, while searching for a valid implementation a substantial amount of time is spent on timing analysis during system synthesis. This paper presents a novel system synthesis approach that efficiently prunes the search space in case real-time constraints are violated. For this purpose, the reason for a constraint violation is analyzed and a deduced encoding removes it permanently from the search space. Thus, the approach is capable of proving both the presence and absence of a correct implementation. The key benefit of the proposed approach stems from its integral support for real-time constraint checking. Its efficiency, however, results from the power of deduction techniques of state-of-the-art Boolean Satisfiability (SAT) solvers. Using a case study from the automotive domain, experiments show that the proposed system synthesis approach is able to find valid implementations where former approaches fail. Moreover, it is up to two orders of magnitude faster compared to a state-of-the-art approach. © 2011 ACM.
Keywords: Algorithms; Design

Symbolic system synthesis using answer set programming - Andres, Benjamin; Gebser, Martin; Schaub, Torsten; Haubelt, Christian; Reimann, Felix; Glaß, Michael (Proceedings of the 12th International Conference on Logic Programming and Nonmonotonic Reasoning (LPNMR), 2013)
Recently, Boolean Satisfiability (SAT) solving has been proposed to tackle the increasing complexity in high-level system design. Working well for system specifications with a limited amount of routing options, they tend to fail for densely connected computing platforms. This paper proposes an automated system design approach employing Answer Set Programming (ASP). ASP provides a stringent semantics, allowing for an efficient representation of routing options. An automotive case-study illustrates that the proposed ASP-based system design approach is competitive for sparsely connected computing platforms, while it outperforms SAT-based approaches for dense Networks-on-Chip by an order of magnitude. © 2013 Springer-Verlag.

Symbolic voter placement for dependability-aware system synthesis - Reimann, Felix; Glaß, Michael; Lukasiewycz, Martin; Keinert, Joachim; Haubelt, Christian; Teich, Jürgen (Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2008)
This paper presents a system synthesis approach for dependable embedded systems. The proposed approach significantly extends previous work by automatically inserting fault detection and fault toleration mechanisms into an implementation. The main contributions of this paper are 1) a dependability-aware system synthesis approach that automatically performs a redundant task binding and placement of voting structures to increase both, reliability and safety, respectively, 2) an efficient dependability analysis approach to evaluate lifetime reliability and safety, and 3) results from synthesizing a Motion-JPEG decoder for an FPGA platform using the proposed system synthesis approach. As a result, a set of high-quality solutions of the decoder with maximized reliability, safety, performance, and simultaneously minimized resource requirements is achieved. Copyright 2008 ACM.

Symbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen - Gladigau, Jens; Blendinger, Frank; Haubelt, Christian; Teich, Jürgen (11. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2008)

Symmetry-eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures - Schwarzer, Tobias; Weichslgartner, Andreas; Glaß, Michael; Wildermann, Stefan; Brand, Peter; Teich, Jürgen (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018)

Syntax and execution behavior of SysteMoC - Falk, Joachim; Haubelt, Christian; Teich, Jürgen (2005)

Synthese zuverlässiger und flexibler Systeme - Glaß, Michael; Lukasiewycz, Martin; Haubelt, Christian; Streichert, Thilo; Teich, Jürgen (Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), 2007)

Synthesis and Exploration of Loop Accelerators for Systems-on-a-Chip - Dutta, Hritam (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2011)

Synthesis and Optimization of Digital Hardware/Software Systems - Teich, Jürgen (1996)

Synthesis and Optimization of Digital Hardware/Software Systems - Teich, Jürgen (In System Design Automation, 2001)
UnivIS-Import:2015-04-20:Pub.2001.tech.IMMD.inform.synthe_7

Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge - Reiche, Oliver; Häublein, Konrad; Reichenbach, Marc; Schmid, Moritz; Hannig, Frank; Teich, Jürgen; Fey, Dietmar (Journal of Systems Architecture, 2015)
In the domain of image processing, often real-time constraints are required. In particular, in safety-critical applications, timing is of utmost importance. A common approach to maintain real-time capabilities is to offload computations to dedicated hardware accelerators, such as Field Programmable Gate Arrays (FPGAs). Designing such architectures is per se already a challenging task, but finding the right design point between achieving as much throughput as necessary while spending as few resources as possible is an even bigger challenge. To address this design challenge in the domain of image processing, several approaches have been presented that introduce an additional layer of abstraction between the developer and the actual target hardware. One approach is to use a Domain-Specific Language (DSL) to generate highly optimized code for synthesis by general purpose High-Level Synthesis (HLS) frameworks. Another approach is to instantiate a generic VHDL IP-Core library for local imaging operators. Elevating the description of image algorithms to such a higher abstraction level can significantly reduce the complexity for designing hardware accelerators targeting FPGAs. We provide a comparison of results for both approaches, a non-expert algorithm developer can achieve. Furthermore, we present an automatic optimization process to give the algorithm developer even more control over trading execution time for resource usage, that could be applied on top of both approaches. To evaluate our optimization procedure, we compare the resulting FPGA accelerators to highly optimized Graphics Processing Unit (GPU) implementations of several image filters relevant for close-to-sensor image and video processing with stringent real-time constraints, such as in the automotive domain.
UnivIS-Import:2016-02-10:Pub.2015.tech.IMMD.IMMD3._synth
Keywords: Hardware Accelerators; Image Processing; Synthesis; Code Generation

Synthesis of FPGA Implementations from Loop Algorithms - Teich, Jürgen; Bednara, Marcus (Proc. of the First International Conference on Engineering of Reconfigurable Systems and Algorithms, 2001)
UnivIS-Import:2015-04-16:Pub.2001.tech.IMMD.inform.synthe

Synthesis of multi-dimensional high-speed FIFOs for out-of-order communication - Keinert, Joachim; Haubelt, Christian; Teich, Jürgen (Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), 2008)
Due to increasing complexity of modern real-time image processing applications, classical hardware development at register transfer level becomes more and more the bottleneck of technological progress. Modeling those applications by help of multi-dimensional data flow and providing efficient means for their synthesis in hardware is one possibility to alleviate the situation. The key element of such descriptions is a multi-dimensional FIFO whose hardware synthesis shall be investigated in this paper. In particular, it considers the occurring out-of-order communication and proposes an architecture which is able to handle both address generation and flow control in an efficient manner. The resulting implementation allows reading and writing one pixel per clock cycle with an operation frequency of up to 300 MHz. This is even sufficient to process very huge images occurring in the domain of digital cinema in real-time. © 2008 Springer-Verlag Berlin Heidelberg.

Synthesizing High-Performance Image Processing Applications with Hipacc - Özkan, Mehmet Akif; Reiche, Oliver; Qiao, Bo; Membarth, Richard; Teich, Jürgen; Hannig, Frank (Demo at the University Booth at Design, Automation and Test in Europe (DATE), 2019)
Programming heterogeneous platforms to achieve high performance is laborious since writing efficient code requires tuning at a low level with architecture-specific optimizations and is based on drastically differing programming models. Performance portability across different platforms can be achieved by decoupling the algorithm description from the target implementation. We present Hipacc (http://hipacc-lang.org), a framework consisting of an open-source image processing DSL and a compiler to target CPUs, GPUs, and FPGAs from the same program. We demonstrate Hipacc’s productivity by considering real-world computer vision applications, e.g., optical flow, and generating target code (C++, OpenCL, C-based HLS) for three platforms (CPU and GPU in a laptop and an FPGA board). Finally, we showcase the real-time processing of images acquired by a USB camera on these platform

Synthesizing Passive Networks by applying Genetic Programming and Evolution Strategies - Kralicek, Peter; John, Werner; Reinhold, Christian; Teich, Jürgen (Proceedings of the Congress on Evolutionary Computation (CEC'03), 2003)
In order to accurately predict the behavior of micro-electronic systems with nodal based software tools like SPICE, it is necessary to know appropriate equivalent circuits of the systems of interest. In microwave and RF engineering, this equivalent networks often have to be derived form measurement or EM field calculation via scattering parameters. In this contribution, a methodology is suggested that combines evolutionary algorithms (EAs) with a nodal based assembly technique in order to synthesize passive equivalent networks. Using only the knowledge of the scattering parameters, both structure and component values of an equivalent circuit of a system are determined by EA. © 2003 IEEE.
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.synthe_6

Systematic design concepts for signal processing arrays (invited paper) - Teich, Jürgen; Thiele, Lothar (Frequenz, 1990)

Systematic Design of Self-Adaptive Embedded Systems with Applications in Image Processing - Wildermann, Stefan (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2012)

Systematic Integration of Parameterized Local Search Into Evolutionary Algorithms - Bambha, Neil; Bhattacharyya, Shuvra S.; Zitzler, Eckart; Teich, Jürgen (IEEE Transactions on Evolutionary Computation, 2004)
Application-specific, parameterized local search algorithms (PLSAs), in which optimization accuracy can be traded off with run time, arise naturally in many optimization contexts. We introduce a novel approach, called simulated heating, for systematically integrating parameterized local search into evolutionary algorithms (EAs). Using the framework of simulated heating, we investigate both static and dynamic strategies for systematically managing the tradeoff between PLSA accuracy and optimization effort. Our goal is to achieve maximum solution quality within a fixed optimization time budget. We show that the simulated heating technique better utilizes the given optimization time resources than standard hybrid methods that employ fixed parameters, and that the technique is less sensitive to these parameter settings. We apply this framework to three different optimization problems, compare our results to the standard hybrid methods, and show quantitatively that careful management of this tradeoff is necessary to achieve the full potential of an EA/PLSA combination.
UnivIS-Import:2015-03-09:Pub.2004.tech.IMMD.inform.system_1
Keywords: Evolutionary algorithm (EA); Hybrid global/local search

Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms - Bambha, Neil; Bhattacharyya, Shuvra S.; Teich, Jürgen; Zitzler, Eckart (Proceedings of the Genetic and Evolutionary Computation Conference, 2004)
Application-specific, parameterized local search algorithms (PLSAs), in which optimization accuracy can be traded off with run-time, arise naturally in many optimization contexts. We introduce a novel approach, called simulated heating, for systematically integrating parameterized local search into evolutionary algorithms (EAs). Using the framework of simulated heating, we investigate both static and dynamic strategies for systematically managing the trade-off between PLSA accuracy and optimization effort. Our goal is to achieve maximum solution quality within a fixed optimization time budget. We show that the simulated heating technique better utilizes the given optimization time resources than standard hybrid methods that employ fixed parameters, and that the technique is less sensitive to these parameter settings. We demonstrate our techniques on the well-known binary knapsack problem and two problems in electronic design automation. We compare our results to the standard hybrid methods, and show quantitatively that careful management of this trade-off is necessary to achieve the full potential of an EA/PLSA combination. © Springer-Verlag Berlin Heidelberg 2004.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.system

SYSTEMCODESIGNER - An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications - Keinert, Joachim; Streubühr, Martin; Schlichter, Thomas; Falk, Joachim; Gladigau, Jens; Teich, Jürgen; Haubelt, Christian; Meredith, Michael (ACM Transactions on Design Automation of Electronic Systems, 2009)
With increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable RTL code from C/C based input descriptions and software generation for embedded processors is automated as well, an efficient ESL synthesis methodology combining both is still missing. This article presents SystemCoDesigner, a novel SystemC-based ESL tool to automatically optimize a hardware/software SoC (System on Chip) implementation with respect to several objectives. Starting from a SystemC behavioral model, SystemCoDesigner automatically extracts the mathematical model, performs a behavioral synthesis step, and explores the multiobjective design space using state-of-the-art multiobjective optimization algorithms. During design space exploration, a single design point is evaluated by simulating highly accurate performance models, which are automatically generated from the SystemC behavioral model and the behavioral synthesis results. Moreover, SystemCoDesigner permits the automatic generation of bit streams for FPGA targets from any previously optimized SoC implementation. Thus SystemCoDesigner is the first fully automated ESL synthesis tool providing a correct-by- construction generation of hardware/software SoC implementations. As a case study, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput, ranging from software-only solutions to pure hardware implementations that reach real-time performance for QCIF streams on a 50MHz FPGA. © 2009 ACM.
UnivIS-Import:2015-04-14:Pub.2009.tech.IMMD.inform.system
Keywords: Hardware/software codesign; System design

SystemCoDesigner: Automatic design space exploration and rapid prototyping from behavioral models - Haubelt, Christian; Schlichter, Thomas; et al. (Proceedings of 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), 2008)
SystemCoDesigner is an ESL tool developed at the University of Erlangen-Nuremberg, Germany. SystemCoDesigner offers a fast design space exploration and rapid prototyping of behavioral SystemC models. Together with Forte Design Systems, a fully automated approach was developed by integrating behavioral synthesis into the design flow. Starting from a behavioral SystemC model, hardware accelerators can be generated automatically using Forte Cynthesizer and can be added to the design space. The resulting design space is explored automatically by optimizing several objectives simultaneously using state of the art multi-objective optimization algorithms. As a result, SystemCoDesigner presents optimized hardware/software solutions to the designer who can select any of them for rapid prototyping on an FPGA basis. Thus, SystemCoDesigner bridges the gap from ESL to RTL and increases the confidence in early design decisions. Copyright 2008 ACM.
Keywords: Design space exploration; ESL design; Rapid prototyping

System design for flexibility - Haubelt, Christian; Teich, Jürgen; Richter, Kai; Ernst, Rolf (Proc. DATE 2002, Design, Automation and Test in Europe, 2002)
With the term flexibility, we introduce a new design dimension of an embedded system that quantitatively characterizes its feasibility in implementing not only one, but possibly several alternative behaviors. This is important when designing systems that may adapt their behavior during operation, e.g., due to new environmental conditions, or when dimensioning a platform-based system that must implement a set of different behaviors. A hierarchical graph model is introduced that allows us to model flexibility and cost of a system formally. Based on this model, an efficient exploration algorithm to find the optimal flexibility/cost-tradeoff-curve of a system using the example of the design of a family of set-top boxes is proposed. © 2002 IEEE.

System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures - Hannig, Frank; Schmid, Moritz; Lari, Vahid; Boppu, Srinivas; Teich, Jürgen (Proc. ACM International Conference on Computing Frontiers, 2013)
As data locality is a key factor for the acceleration of loop programs on processor arrays, we propose a buffer architecture that can be configured at run-time to select between different schemes for memory access. In addition to traditional address-based memory banks, the buffer architecture can deliver data in a streaming manner to the processing elements of the array, which supports dense and sparse stencil operations. Moreover, to minimize data transfers to the buffers, the design contains an interlinked mode, which is especially targeted at 2-D kernel computations. The buffers can be used individually to achieve high data throughput by utilizing a maximum number of I/O channels to the array, or concatenated to provide higher storage capacity at a reduced amount of I/O channels. Copyright 2013 ACM.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.system
Keywords: Processor array; Reconfigurable buffer; System integration

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance - Lari, Vahid; Hannig, Frank; Teich, Jürgen (Proceedings of the 4th International Symposium on Embedded Multicore Systems-on-Chip, 2009)
This paper studies the loosely integration of application accelerators consisting of an array of tightly-coupled lightweight reconfigurable processors into a system-on-a-chip. In order to explore a multitude of design variations a C++ simulation model of the accelerator has been integrated with a system-on-a-chip environment consisting of a general purpose processor, a DMA controller, an interrupt controller and a memory module. Dependent on the applications, different kinds of I/O buffers are designed around the processor array and the effects of the buffer size on the overall execution time are evaluated. The evaluations are based on new mathematical estimation models derived from the system and application constraints. The estimations are validated with experimental results with an error less than 1%. Exploring several designs points that using our architecture along with suitable buffer sizes, can improve the system execution time, one to two magnitudes for the selected algorithms. © 2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.system_5
Keywords: Coarse-grained reconfigurable architectures; Double buffering mechanism; System performance evaluation; System-on-a-chip; Virtual system prototyping

System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems - Pourmohseni, Behnaz (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2021)