Enforcement FSMs - Specification and Verification of Non-Functional Properties of Program Executions on MPSoCs - Esper, Khalil; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2021)
Many embedded system applications impose hard real-time, energy or safety requirements on corresponding programs typically concurrently executed on a given MPSoC target platform. Even when mutually isolating applications in space or time, the enforcement of such properties, e.g., by adjusting the number of processors allocated to a program or by scaling the voltage/frequency mode of involved processors, is a difficult problem to solve, particularly in view of typically largely varying environmental input (workload) per execution. In this paper, we formalize the related control problem using finite state machine models for the uncertain environment determining the workload, the system response (feedback), as well as the enforcer strategy. The contributions of this paper are as follows: a) Rather than trace-based simulation, the uncertain environment is modeled by a discrete-time Markov chain (DTMC) as a random process to characterize possible input sequences an application may experience. b) A number of important verification goals to analyze different enforcer FSMs are formulated in PCTL for the resulting stochastic verification problem, i.e., the likelihood of violating a timing or energy constraint, or the expected number of steps for a system to return to a given execution time corridor. c) Applying stochastic model checking, i.e., PRISM to analyze and compare enforcer FSMs in these properties, and finally d) proposing an approach for reducing the environment DTMC by partitioning equivalent environmental states (i.e., input states leading to an equal system response in each MPSoC mode) such that verification times can be reduced by orders of magnitude to just a few ms for real-world examples.
Keywords: probabilistic model cheking; MPSoC; PCTL; Markov chain; verification; finite state machine; runtime requirement enforcement

Entdecke die Möglichkeiten - Dorsch, Rainer; Haubelt, Christian; Teich, Jürgen (Design & Elektronik, 2008)
UnivIS-Import:2015-04-14:Pub.2008.tech.IMMD.inform.entdec

Entwurfsautomatisierung elektronischer Systeme auf Systemebene - Teich, Jürgen (VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik (GMM), GMM-Fachbericht, 2003)
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.entwur

Environment Mapping Using Massively Parallel Architectures - Fickenscher, Jörg; Bouzouraa, Mohammed Essayed; Hannig, Frank; Teich, Jürgen (Vehicle Intelligence, 2017)

Erlangen slot machine: An FPGA-based dynamically reconfigurable computing platform - Angermeier, Josef; Bobda, Christophe; Majer, Mateusz; Teich, Jürgen (Springer Netherlands, 2010)
Dynamically partially reconfigurable architectures combine high performance and flexibility. They offer a novel possibility to dynamically load and execute hardware modules, previously only known for software modules. In order to realize these promises, the following dilemmas had to be solved: the too often limited memory of reconfigurable architectures for many data-intensive applications, the restricted communication possibilities for partial hardware modules, the unflexible tool flow for partial module design, and the IO-pin dilemma, that the placement of hardware modules, with requirements for input and output signals to the periphery, was predetermined to a single position. These were physical restrictions and technical problems limiting the scope or applicability of dynamically partially reconfigurable architectures. This led us to the development of a new FPGA-based reconfigurable computer called Erlangen Slot Machine, a platform for interdisciplinary research on dynamically reconfigurable systems. It leverages many architectural constraints of existing platforms and allows a user to partially reconfigure hardware modules arranged in so-called slots. The uniqueness of this computer stems from a) a new slot-oriented hardware architecture, b) a set of novel inter-module communication techniques, and c) concepts for dynamic and partial reconfiguration management. © 2010 Springer Science+Business Media B.V.

Error Analysis for Loop Programs using Anytime Instructions in Approximate Computing - Keszöcze, Oliver; König, Moritz; Brand, Marcel; Teich, Jürgen (Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2020)
Approximate Computing is a novel design paradigm sacrificing computational accuracy for gains in other non-functional properties. We present a tool that allows to automatically analyze approximated loop programs for the resulting error and range of output values. Our tool allows to model non-uniform distributions for the input variables. We further support the novel concept of Anytime Instructions: Anytime Instructions encode the number of most-significant mantissa bits to be computed in floating point operations. They are typically used to achieve execution time and energy reductions. First experiments using the tool show promising results.<br

ESL Power and Performance Estimation for Heterogeneous MPSoCs Using SystemC - Streubühr, Martin; Rosales, Rafael; Hasholzner, Ralph; Haubelt, Christian; Teich, Jürgen (Forum on specification and Design Languages 2011, 2011)

Estimating the Execution Time of CNN Inference on GPUs - Groth, Stefan; Schmid, Moritz; Teich, Jürgen; Hannig, Frank (Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), 2024)

Ethernet and IP for Automotive E/E-Architectures - Technology, Analysis, Migration Concepts and Infrastructure - Kern, Andreas (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2013)

Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs - Echavarria Gutiérrez, Jorge Alfonso; Schütz, Katja; Becher, Andreas; Wildermann, Stefan; Teich, Jürgen (AxC18: 3rd Workshop on Approximate Computing, 2018)
Approximate computing allows to tackle conflicting objectives, such as power and accuracy of computations. In this paper we first describe how knowledge of stimuli's specific features can help in quantifying and improving power savings by means of approximate computing. We investigate FPGA implementations of several approximate circuits and compare their power consumption with non-approximating versions. In particular, we study approximate arithmetics and a clock-gate based technique called memoization. Moreover, we compare the accuracy of estimation techniques for power consumption evaluation versus real measurements under controlled environments. We also experimentally quantify the relationship between switching activity and power consumption. Two important results are concluded from our investigations: (1) Approximate arithmetics do not necessarily consume less power than conventional circuits, whereas memoization techniques can in fact reduce power consumption. (2) Simulation-based power evaluation for approximate FPGA implementations can reach fidelity values up to about 90% in input-dependent power characteristics. Yet, to evaluate absolute savings, measurements are neede
Keywords: Switching Activity; Power Consumption; Approximate Computing.

Evaluation of Watermarking methods for FPGA-based IP-cores - Ziener, Daniel; Teich, Jürgen (2005)

Evolutionary Algorithm Based Exploration of Software Schedules for Digital Signal Processors - Bhattacharyya, Shuvra S.; Teich, Jürgen; Zitzler, Eckart (Proc. GECCO'99, the Genetic and Evolutionary Computation Conference, 1999)
UnivIS-Import:2015-04-16:Pub.1999.tech.IMMD.inform.evolut

Evolutionary Algorithms for the Synthesis of Embedded Software - Bhattacharyya, Shuvra S.; Teich, Jürgen; Zitzler, Eckart (IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 2000)
This paper addresses the problem of trading off between the minimization of program and data memory requirements of single-processor implementations of dataflow programs. Based on the formal model of synchronous dataflow (SDF) graphs, so-called single appearance schedules are known to be program-memory optimal. Among these schedules, buffer memory schedules are investigated and explored based on a two-step approach: 1) An evolutionary algorithm (EA) is applied to efficiently explore the (in general) exponential search space of actor firing orders; 2) For each order, the buffer costs are evaluated by applying a dynamic programming post-optimization step (GDPPO). This iterative approach is compared to existing heuristics for buffer memory optimization.
UnivIS-Import:2015-03-09:Pub.2000.tech.IMMD.inform.evolut

Exact Design of Digital Microfluidic Biochips - Keszöcze, Oliver; Wille, Robert; Drechsler, Rolf (Springer, 2018)

Exact Markov chain-based runtime analysis of a discrete particle swarm optimization algorithm on sorting and OneMax - Mühlenthaler, Moritz; Raß, Alexander; Schmitt, Manuel; Wanka, Rolf (Natural Computing, 2021)
Meta-heuristics are powerful tools for solving optimization problems whose structural properties are unknown or cannot be exploited algorithmically. We propose such a meta-heuristic for a large class of optimization problems over discrete domains based on the particle swarm optimization (PSO) paradigm. We provide a comprehensive formal analysis of the performance of this algorithm on certain “easy” reference problems in a black-box setting, namely the sorting problem and the problem OneMax. In our analysis we use a Markov model of the proposed algorithm to obtain upper and lower bounds on its expected optimization time. Our bounds are essentially tight with respect to the Markov model. We show that for a suitable choice of algorithm parameters the expected optimization time is comparable to that of known algorithms and, furthermore, for other parameter regimes, the algorithm behaves less greedy and more explorative, which can be desirable in practice in order to escape local optima. Our analysis provides a precise insight on the tradeoff between optimization time and exploration. To obtain our results we introduce the notion of indistinguishability of states of a Markov chain and provide bounds on the solution of a recurrence equation with non-constant coefficients by integration. <br

Exact One-Pass Synthesis of Digital Microfluidic Biochips - Keszocze, Oliver; Wille, Robert; Ho, Tsung-Yi; Drechsler, Rolf (51st Annual Design Automation Conference, DAC 2014, 2014)

Exact Partitioning of Affine Dependence Algorithms - Teich, Jürgen (Proc. SAMOS - Systems, Architectures, Modeling and Simulation Workshop, 2001)
UnivIS-Import:2015-04-16:Pub.2001.tech.IMMD.inform.exactp

Exact Partitioning of Affine Dependence Algorithms - Teich, Jürgen; Thiele, Lothar (Embedded Processor Design Challenges, Lecture Notes in Computer Science (LNCS), 2002)
UnivIS-Import:2015-04-20:Pub.2002.tech.IMMD.inform.exactp

Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures - Keszöcze, Oliver; Mohammadzadeh, Naser; Wille, Robert (Design, Automation and Test in Europe, 2021)

ExaSlang: A Domain-Specific Language for Highly Scalable Multigrid Solvers - Schmitt, Christian; Kuckuk, Sebastian; Hannig, Frank; Köstler, Harald; Teich, Jürgen (Proc. of the 4th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), 2014)
High-performance computing (HPC) systems are becoming increasingly parallel and heterogeneous. As a consequence, HPC applications, such as simulation software, need to be especially designed towards these systems to achieve optimal performance. This, in turn, leads to higher complexity, making software engineers and scientists require a deep knowledge of the hardware and its technologies. As a remedy, domain-specific languages (DSLs) are a convenient technology for domain experts to describe settings and problems they want to solve using terms and models familiar to them. This specification is transformed into a target language, i.e., source code in another programming language or a binary executable, by a specialized compiler. We propose ExaSlang, a language for the specification of numerical solvers based on the multigrid method targeting distributed-memory systems. Furthermore, we present the transformation framework that drives the corresponding source-to-source compiler. It emits C++ code utilizing a hybrid OpenMP and MPI parallelization. Moreover, we substantiate our approach with scaling results of our code scaling up to the complete JUQUEEN cluster, consisting of 28,672 nodes, with a total of 458,752 core
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.exasla

ExaSlang and the ExaStencils Code Generator - Kuckuk, Sebastian; Schmitt, Christian; Kronawitter, Stefan (PASC'15, 2015)

ExaStencils: Advanced multigrid solver generation - Lengauer, Christian; Apel, Sven; Bolten, Mathias; Chiba, Shigeru; Rüde, Ulrich; Teich, Jürgen; Größlinger, Armin; Hannig, Frank; Köstler, Harald; Claus, Lisa; Grebhahn, Alexander; Groth, Stefan; et al. (Lecture notes in computational science and engineering, 2020)
Present-day stencil codes are implemented in general-purpose programming languages, such as Fortran, C, or Java, Python or derivates thereof, and harnesses for parallelism, such as OpenMP, OpenCL or MPI. Project ExaStencils pursued a domain-specific approach with a language, called ExaSlang, that is stratified into four layers of abstraction, the most abstract being the formulation in continuous mathematics and the most concrete a full, automatically generated implementation. At every layer, the corresponding language expresses not only computational directives but also domain knowledge of the problem and platform to be leveraged for optimization. We describe the approach, the software technology<br
Keywords: computational algorithms; system software; application software; data management an exploration; programming; software tools; HPC; EcaStencils; ExaSlang

ExaStencils – Advanced Multigrid Solver Generation - Lengauer, Christian; Apel, Sven; Bolten, Mathias; Chiba, Shigeru; Rüde, Ulrich; Teich, Jürgen; Größlinger, Armin; Hannig, Frank; Köstler, Harald; Claus, Lisa; Grebhahn, Alexander; Groth, Stefan; et al. (Software for Exascale Computing – SPPEXA 2016-2019, 2020)
Present-day stencil codes are implemented in general-purpose programming languages, such as Fortran, C, or Java, Python or derivates thereof, and harnesses for parallelism, such as OpenMP, OpenCL or MPI. Project ExaStencils pursued a domain-specific approach with a language, called ExaSlang, that is stratified into four layers of abstraction, the most abstract being the formulation in continuous mathematics and the most concrete a full, automatically generated implementation. At every layer, the corresponding language expresses not only computational directives but also domain knowledge of the problem and platform to be leveraged for optimization. We describe the approach, the software technology behind it and several case studies that demonstrate its feasibility and versatility: high-performance stencil codes can be engineered, ported and optimized more easily and effectively.<br

ExaStencils: Advanced Stencil-Code Engineering - Lengauer, Christian; Apel, Sven; Größlinger, Armin; Grebhahn, Alexander; Kronawitter, Stefan; Bolten, Matthias; Rittich, Hannah; Hannig, Frank; Köstler, Harald; Rüde, Ulrich; Teich, Jürgen; Kuckuk, Sebastian; et al. (Proceedings of Euro-Par 2014: Parallel Processing Workshops, 2014)
Project ExaStencils pursues a radically new approach to stencil-code engineering. Present-day stencil codes are implemented in general-purpose programming languages, such as Fortran, C, or Java, or derivates thereof, and harnesses for parallelism, such as OpenMP, OpenCL or MPI. ExaStencils favors a much more domain-specific approach with languages at several layers of abstraction, the most abstract being the mathematical formulation, the most concrete the optimized target code. At every layer, the corresponding language expresses not only computational directives but also domain knowledge of the problem and platform to be leveraged for optimization. This approach will enable a highly automated code generation at all layers and has been demonstrated successfully before in the U.S. projects FFTW and SPIRAL for certain linear transform
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.exaste

ExaStencils: Advanced Stencil-Code Engineering - First Project Report - Lengauer, Christian; Apel, Sven; Bolten, Mathias; Größlinger, Armin; Hannig, Frank; Köstler, Harald; Rüde, Ulrich; Teich, Jürgen; Grebhahn, Alexander; Kronawitter, Stefan; Kuckuk, Sebastian; Rittich, Hannah; et al. (2014)
Project ExaStencils pursues a radically new approach to stencil-code engineering. Present-day stencil codes are implemented in general-purpose programming languages, such as Fortran, C, or Java, or derivates thereof, and harnesses for parallelism, such as OpenMP, OpenCL or MPI. ExaStencils favors a much more domain-specific approach with languages at several layers of abstraction, the most abstract being the mathematical formulation, the most concrete the optimized target code. At every layer, the corresponding language expresses not only computational directives but also domain knowledge of the problem and platform to be leveraged for optimization. This approach will enable a highly automated code generation at all layers and has been demonstrated successfully before in the U.S. projects FFTW and SPIRAL for certain linear transform
UnivIS-Import:2016-06-30:Pub.2014.tech.IMMD.lsinfs.exaste

Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures - Roloff, Sascha; Schafhauser, David; Hannig, Frank; Teich, Jürgen (Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015)
We present a parallel execution-driven simulator for the efficient simulation of heterogeneous tile-based multi-core architectures. Here, the architecture is composed of several tiles connected via a network-on-chIP and each tile contains local memory as well as several possibly different types of compute resources. Partitioned Global Address Space (PGAS) is a programming model matching very well the needs for programming of such modern multi-core architectures. In order to provide performance estimations for parallel software and enable architecture design space exploration, fast functional and timing simulation techniques are required. Thus, we present a simulator that meets this requirement by combining a fast direct-execution simulation approach with different parallelization strategies. Here, we propose four novel parallel discrete-event simulation techniques, which map thread-level parallelism within the applications to core-level parallelism on the target architecture and back to thread-level parallelism on the host machine. In order to achieve this, the correct synchronization and activation of the host threads is necessary being the main focus of this paper. Experiments with parallel real-world applications are used to compare the different techniques against each other and demonstrate that 10.4 times faster simulations than a sequential simulation can be achieved on a 12-core Intel Xeon processo

Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror - Grebhahn, Alexander; Kuckuk, Sebastian; Schmitt, Christian; Köstler, Harald; Siegmund, Norbert; Apel, Sven; Hannig, Frank; Teich, Jürgen (Parallel Processing Letters, 2014)
UnivIS-Import:2015-03-11:Pub.2014.tech.IMMD.inform.experi

Explanation of Stagnation at Points that are not Local Optima in Particle Swarm Optimization by Potential Analysis - Raß, Alexander; Schmitt, Manuel; Wanka, Rolf (Companion of Proc. 17th Genetic and Evolutionary Computation Conference (GECCO), 2015)
This paper investigates the frequently observed phenomenon of stagnation which appears on particle swarm optimization (PSO). We introduce a measure of significance of single dimensions and provide experimental and theoretical evidence that the classical PSO, even with swarm parameters known (from the literature) to be good, almost surely does not converge to a local optimum (stagnation) if too few particles are used. Stagnation is an undesirable property of PSO.
Keywords: Particle swarm optimization; stagnation; potential

Explanation of Stagnation at Points that are not Local Optima in Particle Swarm Optimization by Potential Analysis [Extended Version] - Raß, Alexander; Schmitt, Manuel; Wanka, Rolf (2015)
Particle Swarm Optimization (PSO) is a nature-inspired meta-heuristic for solving continuous optimization problems. In the literature, the potential of the particles of swarm has been used to show that slightly modified PSO guarantees convergence to local optima. Here we show that under specific circumstances the unmodified PSO, even with swarm parameters known (from the literature) to be good, almost surely does not yield convergence to a local optimum is provided. This undesirable phenomenon is called stagnation. For this purpose, the particles' potential in each dimension is analyzed mathematically. Additionally, some reasonable assumptions on the behavior if the particles' potential are made. Depending on the objective function and, interestingly, the number of particles, the potential in some dimensions may decrease much faster than in other dimensions. Therefore, these dimensions lose relevance, i.e., the contribution of their entries to the decisions about attractor updates becomes insignificant and, with positive probability, they never regain relevance. If Brownian Motion is assumed to be an approximation of the time-dependent drop of potential, practical, i.e., large values for this probability are calculated. Finally, on chosen multidimensional polynomials of degree two, experiments are provided showing that the required circumstances occur quite frequently. Furthermore, experiments are provided showing that even when the very simple sphere function is processed the described stagnation phenomenon occurs. Consequently, unmodified PSO does not converge to any local optimum of the chosen functions for tested parameter settings.
Keywords: Particle swarm optimization; stagnation; potential

Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing - Tanase, Alexandru-Petru; Lari, Vahid; Hannig, Frank; Teich, Jürgen (Proc. International Conference on Parallel Computing, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.exploi_3

Exploiting Data-Redundancy in Reliability-Aware Networked Embedded System Design - Lukasiewycz, Martin; Glaß, Michael; Teich, Jürgen (Proc. 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009)
This paper presents a system-level design methodology for networked embedded systems that exploits existing data-redundancy to increase their reliability. The presented approach not only supports a reliability-aware embedded system design from scratch, but also enables the redesign of existing systems to increase the reliability with a minimal communication overhead. The proposed approach contributes (a) algorithms to automatically identify inherent data-redundancy and (b) an automatic design space exploration that is capable of exploiting the revealed data-redundancy. A symbolic analysis is presented that quantifies the reliability of a system, enabling the usage of reliability as one of multiple conflicting optimization objectives. The proposed approach is applied to a realworld case study from the automotive area, showing a significantly increased reliability with a negligible communication overhead. Copyright 2009 ACM.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.exploi
Keywords: Design space exploration; Networked embedded systems; Reliability

Exploiting Electronic Design Automation for Checking Legal Regulations: A Vision - Keszöcze, Oliver; Wille, Robert (Languages, Design Methods, and Tools for Electronic System Design, 2016)
This book brings together a selection of the best papers from the seventeenth edition of the Forum on specification and Design Languages Conference (FDL), which took place on October 14-16, 2014, in Munich, Germany. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology system

Exploiting Independent Subformulas: A Faster Approximation Scheme for #k-SAT - Schmitt, Manuel; Wanka, Rolf (Information Processing Letters, 2013)
We present an improvement on Thurley's recent randomized approximation scheme for #k-SAT where the task is to count the number of satisfying truth assignments of a Boolean function Φ given as an n-variable k-CNF. We introduce a novel way to identify independent substructures of Φ and can therefore reduce the size of the search space considerably. Our randomized algorithm works for any k. For #3-SAT, it runs in time O(ε- 2×1.51426n), for #4-SAT, it runs in time O(ε-2×1.60816n), with error bound ε. © 2013 Elsevier B.V. All rights reserved.
UnivIS-Import:2015-03-09:Pub.2013.tech.IMMD.infalg._explo_5
Keywords: #k-SAT; Algorithms; Analysis of algorithms; Randomized algorithms; Satisfiability

Exploiting Model-Knowledge in High-Level Synthesis - Zebelein, Christian; Falk, Joachim; Haubelt, Christian; Teich, Jürgen (Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’12), 2012)

Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems - Brand, Peter; Ah Sue, Jonathan; Brendel, Johannes; Falk, Joachim; Hasholzner, Ralph; Teich, Jürgen; Wildermann, Stefan (20th International Workshop on Software and Compilers for Embedded Systems (SCOPES’17), 2017)
Keywords: Dynamic Network Communication; LTE Radio Systems; Machine Learning; Predictability; Power Efficient Data Transmission

EXPLORA - Generic Design Space Exploration During Embedded System Synthesis - Cieslok, Frank; Esau, Heinrich; Teich, Jürgen (Proc. DIPES 2000, Int. IFIP Workshop on Distributed and Parallel Embedded Systems, 2000)
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.explor

EXPLORA- generic design space exploration during embedded system synthesis - Cieslok, Frank; Esau, Heinrich; Teich, Jürgen (Springer New York LLC, 2001)
The need for design space exploration on different levels of abstraction during synthesis of electronic systems has received wide attention recently. Unfortunately, there are almost no tools available on the EDA market that allow a designer to enhance his synthesis tool suite by design space exploration capabilities easily. A versatile tool for design space exploration must be targetable to different synthesis tools. Also, different optimization (exploration) algorithms should be able to be connected to such a versatile tool. Here, we present an approach that enables design space exploration with support to couple different exploration algorithms and synthesis tools. Our JAVA based tool called EXPLORA is also able to visualize the exploration results and can be adapted to new problems and abstraction levels within hours. © 2001 by Springer Science+Business Media New York.

Exploration of Distributed Automotive Systems using Compositional Timing Analysis - Lukasiewycz, Martin; Glaß, Michael; Teich, Jürgen; Chakraborty, Samarjit (Embedded Systems Development: From Functional Models to Implementations, 2014)
UnivIS-Import:2015-04-20:Pub.2013.tech.IMMD.inform.explor

Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design - Wang, Bo; Xu, Yang; Hasholzner, Ralph; Drewes, Christian; Rosales, Rafael; Graf, Sebastian; Falk, Joachim; Glaß, Michael; Teich, Jürgen (In Proceedings of the 19. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2016), 2016)

Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-specific Multi-core SoCs - Wang, Bo; Glaß, Michael; Falk, Joachim; Ahmed, Imtiaz; Teich, Jürgen (In Proc. of the 33rd International Conference on Architecture of Computing Systems (ARCS), 2020)

Exploration, Partitioning and Simulation of Reconfigurable Systems - Dittmann, Florian; Rammig, Franz; Streubühr, Martin; Haubelt, Christian; et al. (it - Information Technology, 2007)
UnivIS-Import:2015-04-14:Pub.2007.tech.IMMD.inform.explor

Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems - Letras, Martin; Falk, Joachim; Teich, Jürgen (IEEE Access, 2024)
This paper presents an approach for reducing the memory requirements of periodically executed dataflow applications, while minimizing the period when deployed on a many-core target. Often, implementations of dataflow applications suffer from data duplication if identical data has to be processed by multiple actors. In fact, multi-cast (also called fork) actors can produce huge memory overheads when storing and communicating copies of the same data. As a remedy, so-called Multi-Reader Buffers (MRBs) can be utilized to forward identical data to multiple actors in a First In First Out (FIFO) manner while storing each data item only once by sharing. However, using MRBs may increase the achievable period due to contention when accessing the shared data. This paper proposes a novel multi-objective design space exploration approach that selectively replaces multi-cast actors with MRBs and explores actor and FIFO channel mappings to find trade-offs between the objectives of period, memory footprint, and core cost. In distinction to the state-of-the-art, our approach considers (i) memory-size constraints for on-chip memories, (ii) hierarchical memories to implement the buffers, e.g., tile-local memories, (iii) supports heterogeneous many-core platforms, i.e., core-type dependent actor execution times, and (iv) optimizes the buffer placement and overall scheduling to minimize the execution period by proposing a novel combined actor and communication scheduling heuristic for period minimization called Communication-Aware Periodic Scheduling on Heterogeneous Many-core Systems (CAPS-HMS) . Our results show that the explored Pareto fronts improve a hypervolume indicator over a reference approach by up to 66% for small to mid-size applications and 90% for large applications. Moreover, selectively replacing multi-cast actors with corresponding MRBs proves to be always superior to never or always replacing them. Finally, it is shown that the quality of the explored Pareto fronts does not degrade when replacing the efficient scheduling heuristic CAPS-HMS by an exact Integer Linear Program (ILP) solver that requires orders of magnitude higher solver times and thus cannot be applied to large scale dataflow network problem
Keywords: Many-Core Systems; Dataflow Networks; Mapping; Pareto Optimization; Memory Management; Modulo Scheduling

Extending Partial Suborders - Fekete, Sandor P.; Köhler, Ekkehard; Teich, Jürgen (Electronic Notes in Discrete Mathematics, 2001)
We consider the problem of finding a transitive orientation T of a comparability graph G = (V, E), such that a given partial order P is extended. Existing algorithms for this problem require the full knowledge of E, so they are of limited use in the context of a branch-and-bound algorithm, where only parts of E may be known at any stage. We present a new approach to the problem by describing a pair of necessary and sufficient conditions for the existence of an orientation T, based on two simple forbidden subconfigurations. This allows it to solve higher-dimensional packing and scheduling problems of interesting size to optimality. We have implemented this approach and the computational results are convincing.
UnivIS-Import:2015-04-20:Pub.2001.tech.IMMD.inform.extend

Extensive resilience analysis of function models of complex systems - Guillouët, Yann; Keszöcze, Oliver; Sill Torres, Frank (Resilience Week, 2021)
The knowledge about the responses to hazardous events is of importance throughout the whole life cycle of a complex system, regardless whether during design or operation phases. These responses also allow to draw conclusions about the resilience of the system. Consequently, there is a need for an extensive consideration of all possible hazardous events a system can be exposed to. This work presents a method for determining the hazards with the most critical system response in terms of resilience. Therefore, we introduce a method for modeling failure propagation under consideration of dynamic behavior in function models. This method is then extended for assessing resilience for random hazard scenarios. Finally, we propose two solutions for determining the most critical hazard scenarios, and thus, provide a base for improvements of the system.<br
Keywords: resilience; hazards; function models; complex systems; evolutionary algorithm

Fairness in Academic Course Timetabling - Mühlenthaler, Moritz (Springer International Publishing, 2015)
UnivIS-Import:2015-04-02:Pub.2015.tech.IMMD.infalg._fairn

Fairness in Academic Course Timetabling - Mühlenthaler, Moritz (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2015)

Fairness in Academic Course Timetabling - Mühlenthaler, Moritz; Wanka, Rolf (Annals of Operations Research, 2014)
We consider the problem of creating fair course timetables in the setting of a university. The central idea is that undesirable arrangements in the course timetable, i.e., violations of soft constraints, should be distributed in a fair way among the stakeholders. We propose and discuss in detail two fair versions of the popular curriculum-based course timetabling (CB-CTT) problem, the MMF-CB-CTT problem and the JFI-CB-CTT problem, which are based on max-min fairness (MMF) and Jain's fairness index (JFI), respectively. For solving the MMF-CB-CTT problem, we present and experimentally evaluate an optimization algorithm based on simulated annealing. We introduce three different energy difference measures and evaluate their impact on the overall algorithm performance. The proposed algorithm improves the fairness on 20 out of 32 standard instances compared to the known best timetables. The JFI-CB-CTT problem formulation focuses on the trade-off between fairness and the aggregated soft constraint violations. Here, our experimental evaluation shows that the known best solutions to 32 CB-CTT standard instances are quite fair with respect to JFI. Our experiments show that the fairness can often be improved at the cost of only a small increase in the overall amount of penalty. © 2014 Springer Science+Business Media New York.
UnivIS-Import:2015-03-09:Pub.2014.tech.IMMD.infalg._fairn
Keywords: Curriculum-based course timetabling; Fairness index; Max-min fairness

Fairness in Academic Timetabling - Mühlenthaler, Moritz; Wanka, Rolf (Proc. 9th Int. Conf. on the Practice and Theory of Automated Timetabling (PATAT), 2012)
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.infalg._fairn

Families of Smith Form Decompositions to simplify Multidimensional Filter Design - Evans, Brian L.; Kalker, Ton A.; Teich, Jürgen (Proc. IEEE Asilomar Conf. on Signals, Systems and Computers, 1994)
UnivIS-Import:2015-04-16:Pub.1994.tech.IMMD.inform.famili

Fast and Feasible Periodic Sorting Networks of Constant Depth - Kutylowski, Miroslaw; Lorys, Krzysztof; Oesterdiekhoff, Brigitte; Wanka, Rolf (Proceedings of the 35th IEEE Symposium on Foundations of Computer Science (FOCS), 1994)

Fast Approximate AIG-Based Synthesis - Heil, Annika; Keszöcze, Oliver (International Workshop on Boolean Problems, 2022)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as smaller area, shorter delay, or less power consumption. Synthesizing approximate circuits is a difficult task due to the inherent complexity of evaluating error metrics used to indicate the quality of the approximated circuit. We present a novel and fast greedy, bucket-based Approximate Logic Synthesis technique working on AND-Inverter Graphs that iteratively performs XOR and constant replacements. It minimizes both, the area of the approximated circuit and, the error introduced by the approximations. We exploit properties of the replacement operations to speed up the computation of the weighted Hamming distance error metric, allowing the algorithm to have a very short execution time. The effectiveness of the presented method is evaluated in a set of experiments, including the state-of-the-art benchmark library EvoApproxLibLITE<br
Keywords: Approximate Computing; (XOR)-And-Inverter Graph; Logic Synthesis

Fast Approximate AIG-Based Synthesis - Heil, Annika; Keszöcze, Oliver (Advanced Boolean Techniques, 2023)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as smaller area, shorter delay, or less power consumption. Synthesizing approximate circuits is a difficult task due to the inherent complexity of evaluating error metrics used to indicate the quality of the approximated circuit. We present a novel and fast greedy, bucket-based Approximate Logic Synthesis technique working on AND-Inverter Graphs that iteratively performs XOR and constant replacements. It minimizes both, the area of the approximated circuit and, the error introduced by the approximations. We exploit properties of the replacement operations to speed up the computation of the weighted Hamming distance error metric, allowing the algorithm to have a very short execution time. The effectiveness of the presented method is evaluated in a set of experiments, including the state-of-the-art benchmark library EvoApproxLibLITE</sup

Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Proc. of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2012)
Many domain-specific MPSoCs are heterogeneous and tiled by nature. For evaluating important architectural decisions such as tile structure and core selection within each tile for future 100 - 1000 core designs, fast and flexible simulation approaches are mandatory. Thus, cycle-accurate simulation techniques or co-simulation approaches using simulator coupling are improper. In this paper, we evaluate heterogeneous tiled MPSoCs using a timing-approximate simulation approach. This simulation approach takes particularly into account applications with highly dynamic thread and workload distributions and resource-aware program behavior. Here, the application itself may decide which set of resources is claimed in dependence on run-time status information of the resources (e. g., temperature, load). In order to verify performance goals of the heterogeneous MPSoC apart from functional correctness, we propose a timing-approximate simulation approach, which is based on a discrete-event host-compiled simulation and a time-warping mechanism to scale the elapsed execution times on the simulation host to the simulated target. It allows the investigation of phases of thread (re-)distribution and resource-awareness with an appropriate accuracy. For selected case studies, it is shown how architectural parameters may be varied very fast enabling the exploration of different designs for cost, performance, and other design objectives. © 2012 ACM.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.fastar
Keywords: C.1.2 [Processor Architectures]: Multiple Data Stream Architectures (Multiprocessors)-parallel processors; C.1.3 [Processor Architectures]: Other Architecture Styles-heterogeneous (hybrid) systems; C.4 [Performance of Systems]: Measurement techniques; Modeling techniques; Performance; Measurement; Experimentation

FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Becher, Andreas; Teich, Jürgen; Ziener, Daniel (Proceedings of 2016 International Conference on Field Programmable Technology, 2016)
During the design of embedded systems, many design decisions have to be made to trade off between conflicting objectives such as cost, performance, and power. Approximate computing allows to optimize each objective, yet for the sake of accuracy. This means that a functional flaw is allowed to produce an error as long as this is small enough to maintain a feasible operation of the system or guarantee a certain accuracy of the results. In this paper, we propose a new technique for approximate addition optimized for LUT-Based FPGAs with segmented carry chains. Our optimized adder structure is able to a) best exploit artifacts of LUT-Based FPGAs such as unused inputs and b) provide a smaller average error than previously proposed approximate adder structures, as well as c) a reduced critical path delay than dedicated accurate logic in modern FPGAs. We present a novel stochastic error calculus that is able to take into account also non-uniform input distributions and present a detailed comparison of approximate adder structures proposed in literature with our novel LUT-Based approximate arithmetic structur
Keywords: Approximate Adder; Approximate computing; LUT-Based FPGAs; Low-latency Adders.

Fault effects in FlexRay-based networks with hybrid topology - Dehbashi, Mehdi; Lari, Vahid; Miremadi, Seyed Ghassem; Shokrollah-Shirazi, Mohammad (Proceedings of the 3th International Conference on Availability, Reliability and Security (ARES'08), 2008)
This paper investigates fault effects and error propagation in a FlexRay-based network with hybrid topology that includes a bus subnetwork and a star subnetwork "The investigation is based on about 43500 bit-flip fault injection inside different parts of the FlexRay communication controller. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. Then, this controller is exploited to setup a FlexRay-based network composed of eight nodes (four nodes in the bus subnetwork and four nodes in the star subnetwork). The faults are injected in a node of the bus subnetwork and a node of the star subnetwork of the hybrid network. Then, the faults resulting in the three kinds of errors, namely, content errors, syntax errors and boundary violation errors are characterized. The results of fault injection show that boundary violation errors and content errors are negligibly propagated to the star subnetwork. And syntax errors propagation is almost equal in the both bus and star subnetworks. Totally, the percentage of errors propagation in the bus subnetwork is more than the star subnetwork © 2008 IEEE.

Fault tolerance analysis of distributed reconfigurable systems using SAT-based techniques - Feldmann, Rainer; Haubelt, Christian; Monien, Burkhard; Teich, Jürgen (Proceedings of 13th International Conference on Field Programmable Logic and Applications, 2003)
The ability to migrate tasks from one reconfigurable node to another improves the fault tolerance of distributed reconfigurable systems. The degree of fault tolerance is inherent to the system and can be optimized during system design. Therefore, an efficient way of calculating the degree of fault tolerance is needed. This paper presents an approachbased on satisfiability testing (SAT) which regards the question: How many resources may fail in a distributed reconfigurable system without losing any functionality? We will show by experiment that our new approach can easily be applied to systems of reasonable size as we will find in the future in the field of body area networks and ambient intelligence. © Springer-Verlag Berlin Heidelberg 2003.

Fault-tolerant communication in invasive networks on chip - Heißwolf, Jan; Weichslgartner, Andreas; Zaib, Aurang; Friederich, Stephanie; Masing, Leonard; Stein, Carsten; Duden, Marco; Klöpfer, Roman; Teich, Jürgen; Wild, Thomas; Herkersdorf, Andreas; Becker, Jürgen (Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2015)
Dependability and fault tolerance will play an ever increasing role when using future technology nodes. The paper presents a fault-tolerance strategy for invasive networks on chip (i-NoC). The strategy focuses on permanent faults, resulting from either process fluctuations or aging effects and briefly outlines counter measurements against transient faults. We propose a scalable scheme for detection and localization of defects in NoCs. The localization scheme is used as a basis for disabling faulty routers. We propose a transparent bypass scheme to circumvent faulty routers and regions. It uses an architecture extension in the form of an additional lightweight network layer. The fault tolerance layer can be configured at run time according to the current fault map of the architecture. The presented evaluations analyze the fault coverage of the proposed detection and localization strategy. We also investigate the implementation cost and performance impact of the fault tolerance network layer.
Keywords: Containers; Fault tolerance; Fault tolerant systems; Ports (Computers); Routing; Switches; Testing

Fault-Tolerant Low-Precision DNNs using Explainable AI - Sabih, Muhammad; Hannig, Frank; Teich, Jürgen (2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), 2021)
Hardware-efficient machine learning systems deployed in safety-critical systems need to be optimized for two conflicting objectives. One is making neural networks more compact and efficient by techniques such as quantization and pruning. The other is making them robust against faults. Robustness of Deep Neural Networks (DNNs) becomes a challenge in low-bit precision neural networks such as networks quantized with 8-bit integer precision or less and on custom DNN accelerators with emerging memory technologies and techniques such as approximate memory. Errors in the processing of DNNs can be modeled as bit-flips at the software level. These bit-flips can be caused by persistent memory errors, manifesting themselves in corrupted DNN weights, or they can be caused by transient soft errors.In this work, we introduce an open-source fault-injection framework to simulate both persistent errors and transient errors on PyTorch. Subsequently, we propose novel algorithms that utilize explainable AI methods to make DNNs robust against both kinds, i.e., persistent memory errors and transient soft errors, while keeping the overhead small. We show that our approach can be beneficially used here to mitigate (1) persistent errors by identifying important bits in weights and selectively protecting these using error correcting codes, and (2) transient errors by identifying important samples in activations and selectively protecting these using Triple Modular Redundancy (TMR). Our proposed method outperforms the previously known work on selectively protecting DNN bits in terms of performance and creates further opportunities for research in the area of utilizing explainable AI for robustness.<br
Keywords: Explainable AI; reliable DNNs; robust DNNs; Sensitivity; Quantization (signal); Neural networks; Memory management; Software algorithms; Redundancy; Robustness

Fault tree analysis using stochastic logic: A reliable and high speed computing - Aliee, Hananeh; Zarandi, Hamid R. (Annual Reliability and Maintainability Symposium, RAMS 2011, 2011)
Fault tree analysis is a widespread-use approach for analyzing reliability and safety in critical systems. In this paper, a new approach is introduced to analyze fault trees based on stochastic logic. Applying stochastic logic makes it possible to present floating point numbers as bit streams, in which the quantity of '1' bits is proportional to the evaluated number. In addition, using stochastic logic-based circuits to analyze fault-trees makes the circuits reliable against possible fau lts in the computation circuitry. Moreover, stochastic logic-based fault-tree analysis is fast, since both static and dynamic fau lt tree gates can be easily mapped to their equivalents in stochastic logic, and then be implemented on hardware. The method is based on Monte Carlo algorithm, in which, the failure rates of basic components of a given system are computed at different time slots. At the next step, the whole system's failure rate could be calculated using the stochastic circuitry implemented on hardware. Repeating the experiments for several time slots, results in the reliability-time plot of the system. The experimental results show that this technique is fast and reliable, with negligible calculation error. © 2011 IEEE.
Keywords: fault tree; Monte Carlo Simulation; reliability; stochastic logic

Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024) - Meumeu Yomsi, Patrick; Wildermann, Stefan (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2024)

Flexibility/cost-tradeoffs of platform-based systems - Haubelt, Christian; Teich, Jürgen; Richter, Kai; Ernst, Rolf (Embedded Processor Design Challenges, 2002)
This paper provides a quantitative characterization of an embedded system’s capability to implement alternative behaviors. This new objective in system-level design is termed flexibility and is most notable in the field of adaptive and reconfigurable systems, where a system may change its behavior during operation. Different behaviors are also taken into consideration while implementing platform-based systems. Based on a hierarchical graph model which permits formal modeling of flexibility and implementation cost of a system, an efficient exploration algorithm to find the optimal flexibility/cost-tradeoff-curve is proposed. The feasibility of our approach is demonstrated by a case study concerning the design of a family of Set-Top boxes.

FlexRay Schedule Optimization of the Static Segment - Lukasiewycz, Martin; Glaß, Michael; Milbredt, Paul; Teich, Jürgen (Proc. 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009)
The FlexRay bus is the prospective automotive standard communication system. For the sake of a high exibility, the protocol includes a static time-triggered and a dynamic event-triggered segment. This paper is dedicated to the scheduling of the static segment in compliance with the automotive-specific AUTOSAR standard. For the determination of an optimal schedule in terms of the number of used slots, a fast greedy heuristic as well as a complete approach based on Integer Linear Programming are presented. For this purpose, a scheme for the transformation of the scheduling problem into a bin packing problem is proposed. Moreover, a metric and optimization method for the extensibility of partially used slots is introduced. Finally, the provided experimental results give evidence of the benefits of the proposed methods. On a realistic case study, the proposed methods are capable of obtaining better results in a significantly smaller amount of time compared to a commercial tool. Additionally, the experimental results provide a case study on incremental scheduling, a scalability analysis, an exploration use case, and an additional test case to emphasis the robustness and exibility of the proposed methods. Copyright 2009 ACM.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.flexra
Keywords: FlexRay; Optimization; Scheduling

FlexRay Static Segment Scheduling - Lukasiewycz, Martin; Glaß, Michael; Teich, Jürgen; Milbredt, Paul (Advances in Real-Time Systems, 2012)
UnivIS-Import:2015-04-20:Pub.2012.tech.IMMD.inform.flexra

Foreword DFG SPP1148 session: - Teich, Jürgen (2008 International Conference on Field Programmable Logic and Applications, FPL, 2008)

Formal analysis of the startup delay of SOME/IP service discovery - Seyler, Jan; Streichert, Thilo; Glaß, Michael; Navet, Nicolas; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE 2015), 2015)
An automotive network needs to start up within the millisecond range. This includes the physical startup, the software boot time, and the configuration of the network. The introduction of Ethernet into the automotive industry expanded the design space drastically and is increasing the complexity of configuring every element in the network. To add more flexibility to automotive Ethernet networks, the concept of Service Discovery was migrated from consumer electronics to AUTOSAR within the SOME/IP middleware. A network is not fully functional until every client has found its service. Consequently, this time interval adds to the startup time of a network. This work presents a formal analysis model to calculate the waiting time of every client to receive the first offer from its service. The model is able to determine the worst case of a given parameter set. Based on this, a method for calculating the total startup time of a system is derived. The model is implemented in a free-to-use octave program and validated by comparing the analytical results to a timing-accurate simulation and an experimental setup. In every case the worst-case assumption holds true - the gap between the maximum of the simulation and the presented method is less than 1.3%.

Formalizing TLM with Communicating State Machines - Niemann, Bernardt; Haubelt, Christian; Uribe, Maite; Teich, Jürgen (Advances in Design and Specification Languages for Embedded Systems, 2007)

Formal Reliability Analysis of Switched Ethernet Automotive Networks under Transient Transmission Errors - Smirnov, Fedor; Glaß, Michael; Reimann, Felix; Teich, Jürgen (Proceedings of the 53nd ACM/EDAC/IEEE Design Automation Conference (DAC 2016), 2016)

Formal Timing Analysis of Non-Scheduled Traffic in Automotive Scheduled TSN Networks - Smirnov, Fedor; Glaß, Michael; Reimann, Felix; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017)

FPGA Architecture Extensions for Preemptive Multitasking and Hardware Defragmentation - Ahmadinia, Ali; Bobda, Christophe; Kalte, Heiko; Koch, Dirk; Teich, Jürgen (Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004)
The focus in this paper is put onto extensions to typical FPGA hardware architectures in order to support some operating system functions. In particular, we examine the problem of preemptive multitasking and hardware defragmentation on a reconfigurable system based on FPGAs with a dynamically changing set of hardware tasks that can be replaced considering internal states. © 2004 IEEE.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.fpgaar_4

FPGA-Based Accelerator Design from a Domain-Specific Language - Özkan, Mehmet Akif; Reiche, Oliver; Hannig, Frank; Teich, Jürgen (Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL), 2016)
A large portion of image processing applications often come with stringent requirements regarding performance, energy efficiency, and power. FPGAs have proven to be among the most suitable architectures for algorithms that can be processed in a streaming pipeline. Yet, designing imaging systems for FPGAs remains a very time consuming task. High-Level Synthesis, which has significantly improved due to recent advancements, promises to overcome this obstacle. In particular, Altera OpenCL is a handy solution for employing an FPGA in a heterogeneous system as it covers all device communication. However, to obtain efficient hardware implementations, extreme code modifications, contradicting OpenCL’s data-parallel programming paradigm, are necessary. In this work, we explore the programming methodology that yields significantly better hardware implementations for the Altera Offline Compiler. We furthermore designed a compiler back end for a domain-specific source-to-source compiler to leverage the algorithm description to a higher level and generate highly optimized OpenCL code. Moreover, we advanced the compiler to support arbitrary bit width operations, which are fundamental to hardware designs. We evaluate our approach by discussing the resulting implementations throughout an extensive application set and comparing them with example designs, provided by Altera. In addition, as we can derive multiple implementations for completely different target platforms from the same domain-specific language source code, we present a comparison of the achieved implementations in contrast to GPU implementations.

FPGA-Based Dynamically Reconfigurable SQL Query Processing - Ziener, Daniel; Bauer, Florian; Becher, Andreas; Dennl, Christopher; Meyer-Wegener, Klaus; Schürfeld, Ute; Teich, Jürgen; Vogt, Jörg-Stephan; Weber, Helmut (ACM Transactions on Reconfigurable Technology and Systems, 2015)

FPGA-Based Dynamically Reconfigurable SQL Query Processing - Ziener, Daniel; Weber, Helmut; Vogt, Jörg-Stephan; Schürfeld, Ute; Meyer-Wegener, Klaus; Teich, Jürgen; Dennl, Christopher; Becher, Andreas; Bauer, Florian (ACM Transactions on Reconfigurable Technology and Systems, 2016)
In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, a specialized hardware accelerator pipeline is composed and configured on the FPGA from a set of presynthesized hardware modules. These partially reconfigurable hardware modules are gathered in a library covering all major SQL operations like restrictions and aggregations, as well as more complex operations such as joins and sorts. Moreover, this holistic query processing approach in hardware supports different data processing strategies including row-as column-wise data processing in order to optimize data communication and processing. This article gives an overview of the proposed query processing methodology and the corresponding library of modules. Additionally, a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations. With the help of this performance analysis, architectural bottlenecks may be exposed and future optimized architectures, besides the two prototypes presented here, may be determined.
UnivIS-Import:2017-12-18:Pub.2016.tech.IMMD.inform.fpgaba_0
Keywords: Dynamic partial reconfiguration; FPGA; Reconfigurable computing; SQL processing

FPGA-based Testbed for Timing Behavior Evaluation of the Controller Area Network (CAN) - Ziermann, Tobias; Butiu, Alexander; Teich, Jürgen; Ziener, Daniel (Proc. of the 2012 International Conference on Reconfigurable Computing (ReConFig), 2012)
The Controller Area Network (CAN) is one of the most popular networks for industrial distributed embedded systems, particularly automotive systems. In these systems the timely transmission of data messages is a key requirement. In this paper, a physical testbed is presented that allows the evaluation of the timing behavior of CAN message transmissions. The use of FPGAs as processing nodes allows to accurately perform measurements without influencing the original system due to the inherent parallelism of programmable hardware. As a case study, the improvement of response times by using dynamic scheduling of messages is shown with the testbed. Furthermore, the testbed helps to identify time critical simulation parameters. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.fpgaba

FPGA Core Watermarking Based on Power Signature Analysis - Ziener, Daniel; Teich, Jürgen (Proceedings of IEEE International Conference on Field-Programmable Technology, 2006)
In this paper we introduce a new method to watermark FPGA cores where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method, where the signature is extracted in this way. We are able to sign cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected. The power watermarking method works with all types of FPGAs, but with Xilinx FPGAs, we can integrate the watermarking algorithms and the signature into the functionality of the watermarked core. So it is very hard to remove the watermark without destroying the core. We introduce a detection algorithm which can decode the signature from a voltage trace with high probability. Additionally, a second algorithm is introduced which improves the detection probability in case of considerable noise sources. Using this algorithm, it is possible to decode the signature even if other cores operate on the same device at the same time. © 2006 IEEE.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.fpgaco

FPGA designs of parallel high performance GF(2^233) multipliers - Grabbe, Cornelia; Bednara, Marcus; Teich, Jürgen; von zur Gathen, J.; J. Shokrollahi, J. (Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS-2003), 2003)
For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. We have designed and optimized four high performance parallel GF(2) multipliers for an FPGA realization and analyzed the time and area complexities. One of the multipliers uses a new hybrid structure to implement the Karatsuba algorithm. For increasing performance, we make excessive use of pipelining and efficient control techniques and use a modern state-of-the-art FPGA technology. As a result we have, to our knowledge, the first hardware realization of subquadratic arithmetic and currently the fastest and most efficient implementation of 233 bit finite field multipliers.

FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review - Bustio-Martinez, Lazaro; Cumplido, Rene; Letras, Martin; Hernandez-Leon, Raudel; Feregrino-Uribe, Claudia; Hernandez-Palancar, Jose (ACM Computing Surveys, 2022)
In data mining, Frequent Itemsets Mining is a technique used in several domains with notable results. However, the large volume of data in modern datasets increases the processing time of Frequent Itemset Mining algorithms, making them unsuitable for many real-world applications. Accordingly, proposing new methods for Frequent Itemset Mining to obtain frequent itemsets in a realistic amount of time is still an open problem. A successful alternative is to employ hardware acceleration using Graphics Processing Units (GPU) and Field Programmable Gates Arrays (FPGA). In this article, a comprehensive review of the state of the art of Frequent Itemsets Mining hardware acceleration is presented. Several approaches (FPGA and GPU based) were contrasted to show their weaknesses and strengths. This survey gathers the most relevant and the latest research efforts for improving the performance of Frequent Itemsets Mining regarding algorithms advances and modern development platforms. Furthermore, this survey organizes the current research on Frequent Itemsets Mining from the hardware perspective considering the source of the data, the development platform, and the baseline algorithm.
CRIS-Team WoS Importer:2021-12-17

FPGA Implementation of an Invasive Computing Architecture - Arifin, Farhadur; Amouri, Abdulazim; Hannig, Frank; Teich, Jürgen (Proceedings of the IEEE International Conference on Field Programmable Technology, 2009)
Invasive computing is a novel paradigm for exploitation of run-time parallelism of future MPSoC architectures through resource-aware programming and dynamic reconfiguration of the underlying architectures. Based on the state and availability of resources, an invasive algorithm organizes its computation itself. This paper presents a general methodology for mapping invasive algorithms to FPGA-based dynamically reconfigurable architectures. A detailed description of a general invasive architecture on a reconfigurable platform is given. For 1D linear processor architectures, the applicability of this concept is tested and results show substantial flexibility gains with only marginal additional hardware cost. © 2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.fpgaim

FPGAs for Software Programmers - Koch, Dirk; Hannig, Frank; Ziener, Daniel (Springer, 2016)
This book makes powerful Field Programmable Gate Array (FPGA) and reconfigurable technology accessible to software engineers by covering different state-of-the-art high-level synthesis approaches (e.g., OpenCL and several C-to-gates compilers). It introduces FPGA technology, its programming model, and how various applications can be implemented on FPGAs without going through low-level hardware design phases. Readers will get a realistic sense for problems that are suited for FPGAs and how to implement them from a software designer’s point of view. The authors demonstrate that FPGAs and their programming model reflect the needs of stream processing problems much better than traditional CPU or GPU architectures, making them well-suited for a wide variety of systems, from embedded systems performing sensor processing to large setups for Big Data number crunching. This book serves as an invaluable tool for software designers and FPGA design engineers who are interested in high design productivity through behavioural synthesis, domain-specific compilation, and FPGA overlays. Introduces FPGA technology to software developers by giving an overview of FPGA programming models and design tools, as well as various application examples; Provides a holistic analysis of the topic and enables developers to tackle the architectural needs for Big Data processing with FPGAs; Explains the reasons for the energy efficiency and performance benefits of FPGA processing; Provides a user-oriented approach and a sense for where and how to apply FPGA technology.
UnivIS-Import:2018-09-06:Pub.2016.tech.IMMD.inform.fpgasf

FPGA versus Software Programming - Why, When, and How? - Koch, Dirk; Ziener, Daniel; Hannig, Frank (FPGAs for Software Programmers, 2016)

Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration - Membarth, Richard; Hannig, Frank; Teich, Jürgen; Körner, Mario; Eckert, Wieland (Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP), 2011)
In the last decade, there has been a dramatic growth in research and development of massively parallel many-core architectures like graphics hardware, both in academia and industry. This changed also the way programs are written in order to leverage the processing power of a multitude of cores on the same hardware. In the beginning, programmers had to use special graphics programming interfaces to express general purpose computations on graphics hardware. Today, several frameworks exist to relieve the programmer from such tasks. In this paper, we present five frameworks for parallelization on GPU Accelerators, namely RapidMind, PGI Accelerator, HMPP Workbench, OpenCL, and CUDA. To evaluate these frameworks, a real world application from medical imaging is investigated, the 2D/3D image registration. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.framew

Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration - Membarth, Richard; Hannig, Frank; Teich, Jürgen; Körner, Mario; Eckert, Wieland (Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS), 2011)
The development of standard processors changed in the last years moving from bigger, more complex, and faster cores to putting several more simple cores onto one chip. This changed also the way programs are written in order to leverage the processing power of multiple cores of the same processor. In the beginning, programmers had to divide and distribute the work by hand to the available cores and to manage threads in order to use more than one core. Today, several frameworks exist to relieve the programmer from such tasks. In this paper, we present five such frameworks for parallelization on shared memory multi-core architectures, namely OpenMP, Cilk++, Threading Building Blocks, RapidMind, and OpenCL. To evaluate these frameworks, a real world application from medical imaging is investigated, the 2D/3D image registration. In an empirical study, a fine-grained data parallel and a coarse-grained task parallel parallelization approach are used to evaluate and estimate different aspects like usability, performance, and overhead of each framework. © 2011 Springer-Verlag.
UnivIS-Import:2015-07-08:Pub.2011.tech.IMMD.inform.framew_3
Keywords: 2D/3D Image Registration; Cilk++; Evaluation; Frameworks; Medical Imaging; OpenCL; OpenMP; Parallelization; RapidMind; Threading Building Blocks

From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization - Qiao, Bo; Reiche, Oliver; Hannig, Frank; Teich, Jürgen (Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2019)
Optimizing data-intensive applications such as image processing for GPU targets with complex memory hierarchies requires to explore the tradeoffs among locality, parallelism, and computation. Loop fusion as one of the classical optimization techniques has been proven effective to improve locality at the function level. Algorithms in image processing are increasing their complexities and generally consist of many kernels in a pipeline. The inter-kernel communications are intensive and exhibit another opportunity for locality improvement at the system level. The scope of this paper is an optimization technique called kernel fusion for data locality improvement. We present a formal description of the problem by defining an objective function for locality optimization. By transforming the fusion problem to a graph partitioning problem, we propose a solution based on the minimum cut technique to search fusible kernels recursively. In addition, we develop an analytic model to quantitatively estimate potential locality improvement by incorporating domain-specific knowledge and architecture details. The proposed technique is implemented in an image processing DSL and source-to-source compiler called Hipacc, and evaluated over six image processing applications on three Nvidia GPUs. A geometric mean speedup of up to 2.52 can be observed in our experiments.<br
Keywords: DSL; Image Processing; Kernel Fusion; GPU

From Model-based Design to Virtual Prototypes for Automotive Applications - Streubühr, Martin; Jäntsch, Michael; Haubelt, Christian; Teich, Jürgen (Proceedings of the Embedded World Conference, 2009)

FSM-Controlled Architectures for Linear Invasion - Arifin, Farhadur; Membarth, Richard; Amouri, Abdulazim; Hannig, Frank; Teich, Jürgen (Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.fsmcon

FSM Merging and Reduction for IP Cores Watermarking using Genetic Algorithms - Echavarria Gutiérrez, Jorge Alfonso; Morales-Reyes, Alicia; Cumplido, René; Salido, Miguel A. (Proceedings of 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014)
Keywords: IP Cores; Finite State Machine; Watermarking; Optimization; Genetic Algorithms

Fundamentals - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Modeling and Simulation of Invasive Applications and Architectures, 2019)
CRIS-Team WoS Importer:2019-11-08

FunState - An Internal Design Representation for Codesign - Ernst, Rolf; Griess, Matthias; Strehl, Karsten; Teich, Jürgen; Thiele, Lothar; Ziegenbein, Dirk (IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 2001)
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown how properties relevant for scheduling and verification of specification models such as Boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets can be represented in the FunState model of computation. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in the form of a periodic graph. The feasibility of the novel approach is shown with an asynchronous transfer mode switch example.
UnivIS-Import:2015-03-09:Pub.2001.tech.IMMD.inform.funsta
Keywords: Formal verification; High-level synthesis; Internal specification model; Model of computation; Symbolic scheduling

FunState - An Internal Design Representation for Codesign - Ernst, Rolf; Strehl, Karsten; Teich, Jürgen; Thiele, Lothar; Ziegenbein, Dirk (Proc. ICCAD'99, the IEEE/ACM Int. Conf. on Computer-Aided Design, 1999)
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown here how properties relevant for scheduling and verification of specification models like boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets may be represented in the FunState model. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in form of a periodic graph.
UnivIS-Import:2015-04-16:Pub.1999.tech.IMMD.inform.funsta

Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-core Systems - Wildermann, Stefan; Ziermann, Tobias; Teich, Jürgen (Proc. Design, Automation and Test in Europe, 2013)
Many-core architectures used in embedded systems will contain hundreds of processors in the near future. Already now, it is necessary to study how to manage such systems when dynamically scheduling applications with different phases of parallelism and resource demands. A recent research area called invasive computing proposes a decentralized workload management scheme of such systems: applications may dynamically claim additional processors during execution and release these again, respectively. In this paper, we study how to apply the concepts of invasive computing for realizing decentralized core allocation schemes in homogeneous many-core systems with the goal of maximizing the average speedup of running applications at any point in time. A theoretical analysis based on game theory shows that it is possible to define a core allocation scheme that uses local information exchange between applications only, but is still able to provably converge to optimal results. The experimental evaluation demonstrates that this allocation scheme reduces the overhead in terms of exchanged messages by up to 61.4% and even the convergence time by up to 13.4% compared to an allocation scheme where all applications exchange information globally with each other. © 2013 EDAA.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.gameth

Gateway Strategies for Embedding of Automotive CAN-frames into Ethernet-packets and Vice Versa - Kern, Andreas; Reinhard, Dominik; Streichert, Thilo; Teich, Jürgen (Proceedings of the 24th International Conference on Architecture of Computing Systems, 2011)
Today's automotive communication architectures are composed of up to five special purpose communication technologies with dedicated features to interconnect hundreds of comfort-, safety-, and infotainment-related distributed functions. In the future, the number and complexity of such highly distributed functions will further increase and the outcome of this are stronger requirements to the underlying communication architectures. Ethernet and IP, both standardized and widely used in other industrial sectors, could be one solution to handle the upcoming requirements and could homogenize the variety of communication technologies. This paper focuses on a transformation concept to connect a CAN-based network to an Ethernet/IP-based network and vice versa. It highlights several variants which optimize different objectives, like the protocol header overhead or the latency of messages. Moreover, it presents measured results for different network utilizations and a currently deployed automotive CAN subnetwork. © 2011 Springer-Verlag.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.gatewa
Keywords: automotive; CAN; CAN/Ethernet-Gateway; embedded; Ethernet; gateway; IP; transformation; UDP

General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems - Teich, Jürgen; Angermeier, Josef; Amouri, Abdulazim (Proc. 19th International Conference on Field-Programmable Logic and Applications, 2009)
This paper presents a general methodology for mapping a class of algorithms known as iterative algorithms to FPGA-based dynamically partially reconfigurable architectures in an adaptive and efficient manner. Hereby, each iteration step is mapped to a partial module on the FPGA, and modules can be added or removed to these connected modules on the FPGA dynamically using partial reconfiguration. The more modules and iteration steps, respectively, are concurrently executed on the FPGA, the higher the achieved through-put due to exploitation of pipelining in the design. Especially, numerical approximation algorithms allow a trade-off between precision of the final result and the execution time, and benefit by the proposed mapping methodology: When mapping an element of that class of algorithms to a partially dynamically reconfigurable platform, the number of modules can be increased or decreased at runtime depending on the desired quality of the results and the available area. Thus, the proposed general mapping methodology provides an acceleration of an important class of algorithms due to the execution in hardware, and allows at run-time a trade-off decision between execution time and quality of the results. Furthermore, a detailed description of an experimental implementation of a square root calculation on a reconfigurable platform is given as a prototype example to explain and show the benefits of the proposed approach. ©2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.genera
Keywords: Approximation algorithms; Dynamic partial reconfiguration; Hardware acceleration; Iterative algorithms; Mapping methodology

Generating Device-specific GPU Code for Local Operators in Medical Imaging - Membarth, Richard; Hannig, Frank; Teich, Jürgen; Körner, Mario; Eckert, Wieland (Proc. of the 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2012)
To cope with the complexity of programming GPU accelerators for medical imaging computations, we developed a framework to describe image processing kernels in a domain-specific language, which is embedded into C++. The description uses decoupled access/execute metadata, which allow the programmer to specify both execution constraints and memory access patterns of kernels. A source-to-source compiler translates this high-level description into low-level CUDA and Open CL code with automatic support for boundary handling and filter masks. Taking the annotated metadata and the characteristics of the parallel GPU execution model into account, two-layered parallel implementations - utilizing SPMD and MPMD parallelism - are generated. An abstract hardware model of graphics card architectures allows to model GPUs of multiple vendors like AMD and NVIDIA, and to generate device-specific code for multiple targets. It is shown that the generated code is faster than manual implementations and those relying on hardware support for boundary handling. Implementations from Rapid Mind, a commercial framework for GPU programming, are outperformed and similar results achieved compared to the GPU backend of the widely used image processing library Open CV. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.genera
Keywords: code generation; CUDA; domain-specific language; GPU; local operators; medical imaging; OpenCL

Generating FPGA-based Image Processing Accelerators with Hipacc - Reiche, Oliver; Özkan, Mehmet Akif; Membarth, Richard; Teich, Jürgen; Hannig, Frank (Proceedings of the International Conference on Computer Aided Design (ICCAD), 2017)
Domain-Specific Languages (DSLs) provide a high-level and domain-specific abstraction to describe algorithms within a certain domain concisely. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs are becoming another attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGAs have been proven to be among the most suitable architectures. In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.
Keywords: Domain-Specific Languages; High-Level Synthesis; Image Processing

Generating GPU Code from a High-level Representation for Image Processing Kernels - Membarth, Richard; Lokhmotov, Anton; Teich, Jürgen (Proceedings of the 5th Workshop on Highly Parallel Processing on a Chip (HPPC), 2011)
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.genera

Generating Highly Parallel Geometric Multigrid Solvers with the ExaStencils Apporach - Kuckuk, Sebastian; Schmitt, Christian; Köstler, Harald; Hannig, Frank; Teich, Jürgen (3rd Workshop on Extreme-scale Programming Tools, 2014)

Generation of Distributed Arithmetic Designs for Reconfigurable Applications - Ahmadinia, Ali; Bobda, Christophe; Danne, Klaus; Teich, Jürgen (GI/ITG Dynamically Reconfigurable Systems Workshop at the 17th International Conference on Architecture of Computing Systems Organic and Pervasive Computing, 2004)
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.genera

Generation of Distributed Loop Control - Hannig, Frank; Teich, Jürgen; Bednara, Marcus (Embedded Processor Design Challenges, Lecture Notes in Computer Science (LNCS), 2002)
UnivIS-Import:2015-04-20:Pub.2002.tech.IMMD.inform.genera

Generation of Multigrid-based Numerical Solvers for FPGA Accelerators - Schmitt, Christian; Schmid, Moritz; Hannig, Frank; Teich, Jürgen; Kuckuk, Sebastian; Köstler, Harald (Proceedings of the 2nd International Workshop on High-Performance Stencil Computations (HiStencils), 2015)
Not only in the field of high-performance computering, field-programmable gate arrays (FPGAs) are a soaringly popular accelerator technology. However, they increase the heterogeneity of clusters, which might be equipped already today with accelerators, such as GPUs. This results in having to combine expertise from different fields, e. g., mathematical, algorithmic and technical experts are needed to create numerical solvers for such systems. To bridge this programmability gap, domain-specific languages are a popular choice to generate low-level implementations from an abstract algorithm description. In this work, we demonstrate the generation of implementations of numerical solvers based on the multigrid method  for FPGAs from the same codebase that is also used to generate code for CPUs using a hybrid parallelization of MPI and OpenMP. Our approach yields in a hardware design that can compute up to 12 V-cycles per second with an input grid size of 4096x4096 on a mid-range FPGA, beating vectorized, single-threaded execution on an Intel i7 by a factor of almost three.

Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout - Lukac, Martin; Nursultan, Saadat; Krylov, Gerogiy; Keszöcze, Oliver (Euromicro Conference on Digital System Design, 2020)

Gradient-Free Adversarial Attacks on 3D Point Clouds from LiDAR Sensors - Urfei, Jan; Smirnov, Fedor; Weichslgartner, Andreas; Wildermann, Stefan (Machine Learning and Optimization Techniques for Automotive Cyber-Physical Systems, 2023)
Light Detection and Ranging (LiDAR) plays a key role in the perception stacks of modern advanced driver assistance and autonomous driving systems. Neural networks are the state-of-the-art technique to classify 3D points from LiDAR sensors. However, neural networks have shown to be susceptible to adversarial attacks. In this article, we formalize these adversarial attacks on LiDAR semantic segmentation as generic multi-objective optimization and solve the resulting minimization problem with an Evolutionary Algorithms. Therefore, we can treat the neural network as a black box and do not rely on any intrinsic knowledge as estimating the gradients, etc. We present two ways to encode the problem for Evolutionary Algorithms. Our experiments with the real-world KITTI dataset and a state-of-the-art semantic segmentation neural network for LiDAR data show that Evolutionary Algorithms are suitable for solving the optimization problem. Further, our results confirm that targeting the attack by constraining the volume for manipulated LiDAR points leads to more effective attack patterns with lower perturbations than attack a set of arbitrary points from the scan.<br
Keywords: ADAS; Autonomous driving; Evolutionary algorithm; LiDAR; Adversarial attack

Grant Prediction-based Dynamic Power Management for 5G to Reduce Mobile Device Energy Consumption - Brand, Peter; Hackenberg, Benjamin; Falk, Joachim; Teich, Jürgen (International Wireless Communications and Mobile Computing Conference (IWCMC 2022), 2022)

GRES: Guaranteed Remaining Energy Scheduling of Energy-harvesting Sensors by Quality Adaptation - Sixdenier, Pierre-Louis André Edouard; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 13th Mediterranean Conference on Embedded Computing (MECO), 2024)
Many battery-powered IoT sensor nodes rely on harvesting energy which must be assumed an unreliable source. Previous works have shown that a sensor node can adapt its power consumption to keep its battery’s state of charge at a sufficient level to achieve perpetual operation by, e.g., dynamically adapting its duty cycle. In this paper, we show that it is also possible to reduce the energy consumed by the operation of a sensor node by controlling the quality of the processed and transmitted data. Moreover, whereas most state-of-the-art methods rely on forecasting energy harvesting, risking loss of service in case of wrong predictions, this paper presents an algorithm called Guaranteed Remaining Energy Scheduling (GRES) which dynamically controls the quality of processed and transmitted data of a sensor node at runtime based on the state of charge of the battery, and providing a guarantee of safe continuous operation at the expense of data quality despite fluctuations in expected harvested energy. In experiments, GRES is evaluated and compared to an approach computing ILP-generated quality schedules for one full day ahead based on the assumption of a perfect harvested energy prediction. It is shown that the latter approach is not only computationally and energy-wise expensive, but also can lead to power shutdowns in case of wrongly predicted harvesting profiles.<br

Guest Editors’ Introduction: Special Issue on Time-Critical Systems Design - Mitra, Tulika; Teich, Jürgen; Thiele, Lothar (IEEE Design and Test of Computers, 2018)

Guest Editors’ Introduction: Special Issue on Time-Critical Systems Design Part II - Mitra, Tulika; Teich, Jürgen; Thiele, Lothar (IEEE Design and Test of Computers, 2018)
It is our pleasure to present Part II of the Special Issue on Time-Critical Systems Design that introduces, explores, and investigates the challenges and opportunities in supporting time criticality in computing systems. As mentioned in Part I of the special issue, we had received a total of 28 submissions, which was an overwhelmingly positive response illustrating the importance and the timely nature of the topic. We selected 12 articles from these submissions for publications in the special issue following rigorous peer review process. Six of these articles already appeared in Part I of the special issue in the March/April 2018 issue, and the remaining six appear in this issue.

Guiding Genetic Algorithms Using Importance Measures for Reliable Design of Embedded Systems - Aliee, Hananeh; Vitzethum, Stefan; Glaß, Michael; Teich, Jürgen; Borgonovo, Emanuele (Proceedings of 29th IEEE Symposium on Defect and Fault Tolerance in VLSI and, 2016)

Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays - Heidorn, Christian; Walter, Dominik; Candir, Yunus Emre; Hannig, Frank; Teich, Jürgen (Proceedings of the 31st International Conference on Field Programmable Logic and Applications (FPL), 2021)
The advent of deep learning has revolutionized the domain of computer vision. Convolutional neural networks (CNNs) became state-of-the-art for solving complex tasks thanks to technological advances of high-end accelerators, such as GPUs and FPGAs, combined in clusters or cloud solutions. In embedded systems, CNNs are also of great interest. However, often these devices cannot afford to offload computational-intensive workloads to the cloud due to strict energy or real-time constraints. Tightly Coupled Processor Arrays (TCPAs) are ideal architectures for accelerating nested loop programs at high energy efficiency. In this demonstrator, we show how TCPAs can meet these requirements at the edge of computing. For illustration, we designed a CNN-based hand sign recognition which is accelerated on a TCPA, implemented the TCPA prototypically as an overlay on a Xilinx Zynq System-on-a-Chip (SoC), and showcase tremendous speedups compared with the integrated ARM Cortex-A9 processor.
Keywords: Convolutional Neural Networks; Hardware Acceleration; Coarse-Grained Reconfigurable Array

Hard Real-Time Application Mapping Reconfiguration for NoC-Based Many-Core Systems - Pourmohseni, Behnaz; Wildermann, Stefan; Glaß, Michael; Teich, Jürgen (Real-Time Systems, 2019)
Real-time applications are increasingly targeting many-core platforms, demanding predictability in a highly dynamic environment. To enable this shift, for each application, a set of mapping candidates with diverse resource requirements and performance qualities (latency, energy, etc.) may be computed at design time, and subsequently, exploited at run time to launch the application on a mapping that adheres to the on-line quality and resource constraints. These constraints, however, may also change during execution such that the mapping in use fails to satisfy them, necessitating a switch to another mapping. This process, namely, mapping reconfiguration, involves the migration of several tasks and may harm timing predictability if the reconfiguration overhead is not accounted for. This paper presents a deterministic mapping reconfiguration methodology to enable predictable reconfigurations among a given set of mappings. To this end, first in an off-line analysis, we (a) identify low-latency migration routes with minimal allocation overhead for each pair of source/target mappings and (b) bound the worst-case reconfiguration latency using an off-line timing analysis. This information is then used at run time to perform timely reconfigurations. We further investigate a (c) hybrid timing analysis which regards the actual availability of communication resources at run time to derive tighter latency bounds. Experimental results for a variety of applications show that the proposed methodology enables reconfigurations with low allocation overhead and affordable latency. To demonstrates the practicality of the proposed methodology and the advantages of the hybrid latency analysis over its off-line counterpart, we present a case study on thermal management of many-core systems using mapping reconfiguration.<br
Keywords: Mapping reconfiguration; Real-time task migration; Run-time predictability; Worst-case timing analysis; Hybrid timing analysis

Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning - Letras, Martin; Hernández-León, Raudel; Cumplido, René (2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016)
Frequent item set mining algorithms have been found to be the most effective way to achieve this goal. For this reason, FPGA-based hardware architectures for frequent item set. Most of the reported architectures are FPGA devices. This study was conducted by the Federal Ministry of Economics and Technology. The proposed architectural design implements a partitioning strategy based on equivalence classes. The partition on equivalence classes allows dividing the search space into disjoint sets that can be processed in parallel. Accordingly, a parallel architecture is proposed to exploit the benefits of the proposed search strategy.
Keywords: Frequent Itemset Mining; Hardware Architecture; FPGA

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS - Heisswolf, Jan; Zaib, Aurang; Weichslgartner, Andreas; König, Ralf; Wild, Thomas; Teich, Jürgen; Herkersdorf, Andreas; Becker, Jürgen (Proc. of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012)
Networks-on-Chip have shown their scalability for future many-core systems on chip. In real world scenarios, concurrent applications with different QoS requirements affect each other through overlapping communication. Therefore computation resources may not be efficiently utilized because the required communication resources are already occupied. Hence, an efficient resource management strategy is required that ensures fair sharing of communication resources between applications. Decentralized strategies provide better scalability in many-core systems. In this paper, we propose a hardware supported decentralized NoC resource management strategy. Our concept enables to define NoC regions through decentralized reconfigurable resource management policies. It offers improved performance and communication resource allocation within the regions. The proposed concept is investigated through simulation of real world application scenarios. The simulation results highlight the performance benefit within the region and the increased probability for successful reservation of communication resources. Implementation results show the low area overhead of the proposed hardware support. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.hardwa_3
Keywords: Best Effort; Guaranteed Service; Networks-on-Chip; Policy; QoS; Quality of Service; Resource Management

Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks - Heidorn, Christian; Sabih, Muhammad; Meyerhöfer, Nicolai; Schinabeck, Christian; Teich, Jürgen; Hannig, Frank (International Journal of Parallel Programming, 2024)
Filter pruning of convolutional neural networks (CNNs) is a common technique to effectively reduce the memory footprint, the number of arithmetic operations, and, consequently, inference time. Recent pruning approaches also consider the targeted device (i.e., graphics processing units) for CNN deployment to reduce the actual inference time. However, simple metrics, such as the L1-norm, are used for deciding which filters to prune. In this work, we propose a hardware-aware technique to explore the vast multi-objective design space of possible filter pruning configurations. Our approach incorporates not only the targeted device but also techniques from explainable artificial intelligence for ranking and deciding which filters to prune. For each layer, the number of filters to be pruned is optimized with the objective of minimizing the inference time and the error rate of the CNN. Experimental results show that our approach can speed up inference time by 1.40× and 1.30× for VGG-16 on the CIFAR-10 dataset and ResNet-18 on the ILSVRC-2012 dataset, respectively, compared to the state-of-the-art ABCPruner.<br
Keywords: Filter pruning; Evolutionary algorithm; Explainable AI

Hardware-Aware Evolutionary Filter Pruning - Heidorn, Christian; Meyerhöfer, Nicolai; Schinabeck, Christian; Hannig, Frank; Teich, Jürgen (International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII), 2022)
Compression techniques for Convolutional Neural Networks (CNNs) are key to performance. One common technique is filter pruning, which can effectively reduce the memory footprint, number of arithmetic operations, and consequently inference time. Recently, several approaches have been presented for automatic CNN compression using filter pruning, where the number of pruned filters is optimized by nature-inspired metaheuristics (e.g., artificial bee colony algorithms). However, these approaches focus on finding an optimal pruned network structure without considering the targeted device for CNN deployment. In this work, we show that the typical objective of reducing the number of operations does not necessarily lead to a maximum reduction in inference time, which is usually the main goal for compressing CNNs besides reducing the memory footprint. We then propose a hardware-aware multi-objective Design Space Exploration (DSE) technique for filter pruning that involves the targeted device (i.e., Graphics Processing Units (GPUs)). For each layer, the number of filters to be pruned is optimized with the objectives of minimizing the inference time and the error rate of the CNN. Experimental results show that our approach can further speed up inference time by 1.24× and 1.09× for VGG-16 on the CIFAR-10 dataset and ResNet-101 on the ILSVRC-2012 dataset, respectively, compared to the state-of-the-art ABCPruner.<br

Hardware cost analysis for weakly programmable processor arrays - Kissler, Dmitrij; Hannig, Frank; Kupriyanov, Olexiy; Teich, Jürgen (Proceedings of the International Symposium on System-on-Chip (SoC), 2006)
Growing complexity and speed requirements in modern application areas such as wireless communication and multimedia in embedded devices demand for flexible and efficient parallel hardware architectures. The inherent parallelism in these application fields has to be reflected at the hardware level to achieve high performance. Coarse-grained reconfigurable architectures support a high degree of parallelism at multiple levels. In this paper technology-independent hardware cost analysis for a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is performed. © 2006 IEEE.

Hardware decompression techniques for FPGA-based embedded systems - Teich, Jürgen; Beckhoff, Christian; Koch, Dirk (ACM Transactions on Reconfigurable Technology and Systems, 2009)
In this work, we present hardware decompression accelerators for widening the bottleneck between slow nonvolatile memories on the one side and high-speed FPGA configuration interfaces and fast softcore CPUs on the other side. We discuss different compression algorithms suitable for a hardware accelerated decompression on FPGAs as well as on CPLDs. The algorithms will be investigated with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations with one capable to decompress at high data rates of up to 400 megabytes per second under optimal conditions while only requiring slightly more than a hundred lookup tables. We will evaluate how these decompressors perform on configuration bitstreams for different FPGAs as well as for softcore CPU binaries © 2009 ACM.
Keywords: Algorithms; Experimentation

Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing - Özkan, Mehmet Akif; Reiche, Oliver; Hannig, Frank; Teich, Jürgen (28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2017)
Field Programmable Gate Arrays (FPGAs) excel at the implementation of local operators in terms of throughput per energy since the off-chip communication can be reduced with an application-specific on-chip memory configuration. Furthermore, data-level parallelism can efficiently be exploited through so-called loop coarsening, which processes multiple horizontal pixels simultaneously. Moreover, existing solutions for proper border handling in hardware show considerable resource overheads. In this paper, we first propose novel architectures for image border handling and loop coarsening, which can significantly reduce area. Second, we present a systematic analysis of these architectures including the formulation of analytical models for their area usage. Based on these models, we provide an algorithm for suggesting the most efficient hardware architecture for a given specification. Finally, we evaluate several implementations of our proposed architectures obtained through Vivado High-Level Synthesis (HLS). The synthesis results show that the proposed coarsening architecture uses 32% less registers for a 5-by-5 convolution with a 64 coarsening factor compared to previous works, whereas the proposed border handling architectures facilitate a decrease in the Look-up Table (LUT) usage by 36%.
Keywords: FPGA; High Level Synthesis; Image Processing; Loop Coarsening; Border Handling

Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats - Arvind, T. K. R.; Brand, Marcel; Heidorn, Christian; Boppu, Srinivas; Hannig, Frank; Teich, Jürgen (Proceedings of the 24th International Symposium on VLSI Design and Test (VDAT), 2020)
In this paper, we present the efficient hardware implementation of hyperbolic tangent activation function, which is most widely used in artificial neural networks for accelerating machine learning applications. The proposed design considers the floating point representation of numbers for the first time, the nonlinear nature of the activation function while sampling, and uses a lookup table for implementation. The unique way of dividing the input range into bins which follows the binary pattern reduces the hardware implementation cost. Furthermore, the input data itself is used as the address for lookup table; thus, no extra cost involved in hashing the lookup table and involves only one memory access time resulting in faster and efficient hardware implementation. Our design proves to be 3x faster when compared to similar hardware implementations using CMOS 90nm proces

Hardware/Software-Codesign: Massgeschneiderte elektronische Systeme.Teil I: HW/SW-Architekturen und Spezifikation - Teich, Jürgen (Bulletin SEV/VSE, 1996)
UnivIS-Import:2015-03-05:Pub.1996.tech.IMMD.inform.hardwa

Hardware/Software-Codesign: Massgeschneiderte elektronische Systeme. Teil II: HW/SW-Synthese - Teich, Jürgen (Bulletin SEV/VSE, 1997)
UnivIS-Import:2015-03-05:Pub.1997.tech.IMMD.inform.hardwa

Hardware/Software Codesign of Embedded Systems - The SPI Workbench - Ernst, Rolf; Richter, Kai; Teich, Jürgen; Thiele, Lothar; Ziegenbein, Dirk (Proc. Int. Workshop on VLSI, 1999)
UnivIS-Import:2015-04-16:Pub.1999.tech.IMMD.inform.hardwa

Hardware/Software Co-Design: Past, Present, and Predicting the Future - Teich, Jürgen (Proceedings of the IEEE, 2012)
UnivIS-Import:2015-03-09:Pub.2012.tech.IMMD.inform.hardwa

Hardware Supported Adaptive Data Collection for Networks on Chip - Heisswolf, Jan; Weichslgartner, Andreas; Zaib, Aurang; König, Ralf; Wild, Thomas; Herkersdorf, Andreas; Teich, Jürgen; Becker, Jürgen (Proc. IEEE 27th International Parallel and Distributed Processing Symposium Workshops PhD Forum, 2013)
Managing future many-core architectures with hundreds of cores, running multiple applications in parallel, is very challenging. One of the major reasons is the communication overhead required to handle such a large system. Distributed management is proposed to reduce this overhead. The architecture is divided into regions which are managed separately. The instance managing the region and the applications running within the regions need to collect data for various reasons from time to time, e.g., to collect data for proper mapping decision, to synchronize tasks or to aggregate computation results. In this work, we propose and investigate different strategies for adaptive data collection in meshed Networks on Chip. The mechanisms can be used to collect data within regions, which are defined during run-time in respect of size and position. The mechanisms are investigated while considering delay, NoC utilization and implementation costs. The results show that the selection of the used mechanism depends on the requirements. Synthesis results compare area overhead, timing impact and energy consumption. © 2013 IEEE.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.hardwa
Keywords: 1000 cores; Adaptive data collection; aggregation; Hamilton cycle; Networks on Chip; region-based management

Hardware-Supported Sorting: Design and Tradeoff Analysis - Bednara, Marcus; Beyer, O.; Teich, Jürgen; Wanka, Rolf (Workshop on System Design Automation - SDA 2000, 2000)
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.hardwa

Hardware Supported Sorting: Design and Tradeoff Analysis - Bednara, Marcus; Beyer, O.; Teich, Jürgen; Wanka, Rolf (In System Design Automation, 2001)
UnivIS-Import:2015-04-20:Pub.2001.tech.IMMD.inform.hardwa

Heterogeneous Constraint Handling for Particle Swarm Optimization - Omeltschuk, Ludmila; Helwig, Sabine; Mühlenthaler, Moritz; Wanka, Rolf (Proc. IEEE Swarm Intelligence Symposium (SIS), 2011)
We propose a generic, hybrid constraint handling scheme for particle swarm optimization called Heterogeneous Constraint Handling. Inspired by the notion of social roles, we assign different constraint handling methods to the particles, one for each social role. In this paper, we investigate two social roles for particles, 'self' and 'neighbor'. Due to the usual particle dynamics, a powerful mixture of the two corresponding constraint handling methods emerges. We evaluate this heterogeneous constraint handling approach with respect to the complete set of the CEC 2006 benchmark instances. Our results indicate that a such a heterogeneous combination of two constraint handling methods often leads to significantly better results than running each individual constraint handling method separately and returning the best solution obtained. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.infalg._heter

Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads - Angermeier, Josef; Teich, Jürgen (Proceedings 15th Reconfigurable Architectures Workshop, 2008)
When using dynamically and partially reconfigurable FPGAs in embedded systems, the scheduler needs to fulfill area and time requirements for each task. While those demands are already well studied in literature, another characteristic peculiarity of reconfigurable systems has been rather neglected: the reconfiguration overhead. However, scheduling algorithms considering the exclusive access to the reconfiguration port can improve the latency of obtained schedules considerably. In this paper, we present new scheduling heuristics and a methodology to compare approaches which take into consideration the reconfiguration overheads with those which disregard them. Furthermore, our experimental results give insight into possible performance increases and present problem instances for which the reconfiguration latency is negligible. ©2008 IEEE.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.heuris

Heuristische Algorithmen zur automatischen Generierung von prozesszeitoptimierten Roboterprogrammen im Bereich von Multi-Robotersystemen - Muradi, Murad (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2021)

Hierachical Synthesis of Embedded Systems Using Evolutionary Algorithms - Haubelt, Christian; Mostaghim, Sanaz; Slomka, Frank; Teich, Jürgen; Tyagi, Ambrish (Evolutionary Algorithms in System Design, 2003)

Hierarchical concepts in the design of processor arrays - Arzt, Ulrich; Teich, Jürgen; Schumacher, M; Thiele, Lothar (Proc. CompEuro 1992, 1992)
UnivIS-Import:2015-04-16:Pub.1992.tech.IMMD.inform.hierar

Hierarchical Microprocessor Design Using XASM - Anlauff, Matthias; Fischer, Dirk; Kutter, Philipp; Teich, Jürgen; Weper, Ralph (Proc. EUROCAST 2001, 2001)
UnivIS-Import:2015-04-16:Pub.2001.tech.IMMD.inform.hierar_6

Hierarchical Modeling and Simulation of Embedded Processors Using ASMs - Fischer, Dirk; Teich, Jürgen; Weper, Ralph (International Workshop on Software and Compilers for Embedded Systems, 2001)
UnivIS-Import:2015-04-16:Pub.2001.tech.IMMD.inform.hierar

Hierarchical Partitioning for Piecewise Linear Algorithms - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering, 2006)
Processor arrays are used as accelerators for plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor array architectures has lead to demand for mapping tools to realize the full potential of these architectures. Such architectures are characterized by hierarchies of parallelism and memory structures, i.e. processor array apart from different levels of cache arrays have a number of processing elements (PE) where each PE can further contain sub-word parallelism. In order to handle large scale problems, balance local memory requirements with I/O-bandwidth, and use different hierarchies of parallelism and memory, one needs a sophisticated transformation called hierarchical partitioning. In this paper, we introduce for the first time a detailed methodology encompassing hierarchical partitioning. © 2006 IEEE.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.hierar

Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays - Lari, Vahid; Muddasani, Shravan; Boppu, Srinivas; Hannig, Frank; Schmid, Moritz; Teich, Jürgen (ACM Transactions on Design Automation of Electronic Systems, 2012)
We present a self-adaptive hierarchical power management technique for massively parallel processor architectures, supporting a new resource-aware parallel computing paradigm called invasive computing. Here, an application can dynamically claim, execute, and release the resources in three phases: resource acquisition (invade), program loading/configuration and execution (infect), and release (retreat). Resource invasion is governed by dedicated decentralized hardware controllers, called invasion controllers (iCtrls), which are integrated into each processing element (PE). Several invasion strategies for claiming linearly connected or rectangular regions of processing resources are implemented. The key idea is to exploit the decentralized resource management inherent to invasive computing for power savings by enabling applications themselves to control the power for processing resources and invasion controllers using a hierarchical power-gating approach. We propose analytical models for estimating various components of energy consumption for faster design space exploration and compare them with the results obtained from a cycle-accurate C++ simulator of the processor array. In order to find optimal design trade-offs, various parameters like (a) energy consumption, (b) hardware cost, and (c) timing overheads are compared for different sizes of power domains. Experimental results show significant energy savings (up to 73%) for selected characteristical algorithms and different resource utilizations. In addition, we demonstrate the accuracy of our proposed analytical model. Here, estimation errors less than 3.6% can be reported. © 2012 ACM.
UnivIS-Import:2015-03-09:Pub.2012.tech.IMMD.inform.hierar
Keywords: Adaptive power optimization; Parallel computing; Resource awareness; Runtime resource management; Timing overhead minimization

Hierarchical Statistical Leakage Analysis and its Application - Xu, Yang; Teich, Jürgen (ACM Transactions on Design Automation of Electronic Systems, 2016)

Higher-Dimensional Packing with Order Constraints - Fekete, Sandor P.; Köhler, Ekkehard; Teich, Jürgen (Proc. 7th Workshop on Algorithms and Data Structures, Lecture Notes in Computer Science (LNCS), Vol. 2125, 2001)
UnivIS-Import:2015-04-16:Pub.2001.tech.IMMD.inform.higher

Higher-dimensional packing with order constraints - Teich, Jürgen; Fekete, Sandor P.; Köhler, Ekkehard (SIAM Journal on Discrete Mathematics, 2006)
UnivIS-Import:2015-03-09:Pub.2006.tech.IMMD.inform.higher

High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems - Streit, Franz-Josef; Letras, Martin; Schid, Matthias; Falk, Joachim; Wildermann, Stefan; Teich, Jürgen (ACM Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017)
In this paper, we present a holistic design methodology for em- bedded smart camera networks consisting of FPGA-based Pro- grammable System-on-Chips (PSoCs). Beginning with a high-level model of a distributed smart camera application specified in Mat- lab/Simulink, a behavioral data-flow-based SystemC model is auto- matically generated. In turn, every vertex of the data-flow graph rep- resents a functional task of the application and can be implemented either as a software or a hardware component on PSoC nodes within the smart camera network. Also, such hardware/software designs for data-intensive camera applications require a sophisticated hard- ware/software interconnect. These design decisions on mapping tasks and communication influence throughput but also the costs of the distributed smart camera network. Our methodology varies communication routing and task map- ping within a camera network to optimize several objectives si- multaneously. Particularly, we use Design Space Exploration (DSE) to explore the trade-off between resource costs and throughput in a smart camera application realized as a heterogeneous hard- ware/software system. In this context, High-Level Synthesis (HLS) constitutes an important mechanism to estimate the functional properties of different hardware design candidates automatically. Furthermore, it enables a semi-automatic synthesis of the smart camera implementation candidate. As a case study, we apply our methodology to a high-bandwidth multi-camera system consist- ing of PSoC nodes, which apply feature-based image registration techniques to combine multiple images with an overlapping field- of-view to produce a panoramic vie
Keywords: High-Level Synthesis; Camera Network; Design Space Exploration

High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model - Schmid, Moritz; Hannig, Frank; Tanase, Alexandru-Petru; Teich, Jürgen (Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2014)
The continuous progress in semiconductor technology allows for more and more complex processor architectures. The downside of these technological advances is that computing has already hit a power wall and clock frequencies can barely be increased. In order to scale computing performance in the future, systems' energy efficiency and the degree of parallelism have to be significantly improved. The design of heterogeneous hardware with different specialized resources seems to be a promising solution. When highest performance (throughput, short latencies) and energy efficiency are important, as a remedy, we consider the generation of dedicated FPGA accelerators to address these stringent requirements. In this work, we present the PARO high-level synthesis framework for the automated generation of massively parallel FPGA accelerators. The framework is tailored for compute-intensive applications from the domains of image, video, and other digital signal processing, as well as algorithms from linear algebra. Unique features of PARO include: (1) The design entry in form of a compact and intuitive domain-specific language that is closely related to a mathematical problem description, (2) support for integer, fixed point, floating point, and custom arithmetic, (3) advanced loop transformations (e.g., partitioning) and scheduling techniques in the polyhedron model, (4)generation of accelerator IP cores (VHDL code) that can be easily integrated into a system design such as an SoC or in a networked scenario. Finally, we showcase the capabilities of our framework for the development of a range image conditioning pipeline for smart cameras for range sensing. © 2014 The authors and IOS Press.
UnivIS-Import:2015-04-20:Pub.2014.tech.IMMD.inform.highle
Keywords: Accelerators; Domain-specific language; FPGAs; High-level synthesis; Polyhedron model

High Performance Network-on-Chip Simulation by Interval-based Timing Predictions - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), 2017)
Current multi- and many-core computer architectures heavily use NoC communication in order to meet the increased bandwidth demands between the processors and for reasons of scalability. For the proper analysis of concurrency, utilization, and workload distribution of parallel multi-media applications running on such NoC-based architectures, high-speed simulation techniques are required. Apart from accurate timing simulation of compute resources, it is of utmost importance also to accurately model the delays caused by the packet-based network communication in order to reliably verify performance numbers, or to identify any bottlenecks of the underlying architecture, or to study workload distribution techniques or routing algorithms. In this paper, we present a novel simulation approach for NoCs that allows to simulate such communication delays equally accurate but much faster in average than on a flit-by-flit basis. We propose novel algorithmic and analytical techniques that predict the transmission intervals dynamically based on the arrival of communication requests, actual congestion in the NoC, routing information, packet lengths, and other parameters. According to such predictions, the simulation time may in many cases be automatically advanced, thus reducing the number of events to process in the simulator to a large extent. The presented NoC simulation technique has been integrated into a system-level multi-core architecture simulator. Experiments in running parallel real-world and multi-media applications on a simulated scalable NoC architecture show that we are able to achieve speedups of three orders of magnitude compared to cycle-accurate NoC simulators, while preserving a timing accuracy of above 95
Keywords: Network-on-Chip; Modeling; Simulation; Parallel Programming

HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids - Alhaddad, Samer; Förstner, Jens; Groth, Stefan; Grünewald, Daniel; Grynko, Yevgen; Hannig, Frank; Kenter, Tobias; Pfreundt, Franz-Josef; Plessl, Christian; Schotte, Merlind; Steinke, Thomas; Teich, Jürgen; et al. (Proceedings of the 18th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar) in Euro-Par 2020: Parallel Processing Workshops, 2021)

High Precision Particle Swarm Optimization Algorithm (HiPPSO) - Raß, Alexander (Journal of Open Research Software, 2020)
Particle Swarm Optimization (PSO) is a nature-inspired meta-heuristic adaptable to continuous optimization problems. To avoid numerical instabilities or artifacts it is necessary to evaluate floating point calculations with high precision. Our High Precision Particle Swarm Optimization (HiPPSO) software realizes this demand. Additionally our software provides an automatic procedure to adjust precision if it is necessary for accurate evaluations. This enables a fast execution time because the software always evaluates the calculations with suitable precision and does not use too much precision if it is not necessary. HiPPSO is implemented in C++ and has a very flexible class hierarchy to replace subroutines on purpose or extend functionality by simply implementing abstract classes. The software is available on a GitHub repository at https://github.com/alexander-rass/HiPPSO</a
Keywords: particle swarm optimization; arbitrary precision; convergence analysis

High-speed event-driven RTL compiled simulation - Kupriyanov, Olexiy; Hannig, Frank; Teich, Jürgen (Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), 2004)
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part of our BUILDABONG [7] framework, which aims at architecture and compiler co-generation for special purpose processors. The main focus of the paper is on the transformation of a given architecture's circuit into a graph and applying on it an essential graph decomposition algorithm to transform the graph into subgraphs denoting the minimal subsets of sequential elements which have to be reevaluated during each simulation cycle. As a second optimization, we present a partitioning algorithm, which introduces intermediate registers to minimize the number of evaluations of combinational nodes during a simulation cycle. The simulator's superior performance compared to an existing commercial simulator is shown. Finally, we demonstrate the pertinence of our approach by simulating a MIPS processor. © Springer-Verlag Berlin Heidelberg 2004.

HIPAcc: A Domain-Specific Language and Compiler for Image Processing - Membarth, Richard; Reiche, Oliver; Hannig, Frank; Teich, Jürgen; Körner, Mario; Eckert, Wieland (IEEE Transactions on Parallel and Distributed Systems, 2016)
Domain-Specific Languages (DSLs) provide high-level and domain-specific abstractions that allow expressive and concise algorithm descriptions. Since the description in a DSL hides also the properties of the target hardware, DSLs are a promising path to target different parallel and heterogeneous hardware from the same algorithm description. In theory, the DSL description can capture all characteristics of the algorithm that are required to generate highly efficient parallel implementations. However, most frameworks do not make use of this knowledge and the performance cannot reach that of optimized library implementations. In this article, we present the HIPAcc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured in the language and that this knowledge enables us to generate tailored implementations for a given target architecture. Back ends for CUDA, OpenCL, and Renderscript allow us to target discrete Graphics Processing Units (GPUs) as well as mobile, embedded GPUs. Exploiting the captured domain knowledge, we can generate specialized algorithm variants that reach the maximal achievable performance due to the peak memory bandwidth. These implementations outperform state-of-the-art domain-specific languages and libraries significantl
UnivIS-Import:2015-03-09:Pub.2015.tech.IMMD.inform.hipacc
Keywords: Domain-specific language; Image processing; Code generation; Source-to-source translation; GPU; CUDA; OpenCL; Renderscript

HIPAcc - Schmid, Moritz; Reiche, Oliver; Hannig, Frank; Teich, Jürgen (FPGAs for Software Programmers, 2016)

HipaccVX: Wedding of OpenVX and DSL-based Code Generation - Özkan, Mehmet Akif; Ok, Burak; Qiao, Bo; Teich, Jürgen; Hannig, Frank (Journal of Real-Time Image Processing, 2021)
Writing programs for heterogeneous platforms optimized for high performance is hard since this requires the code to be tuned at a low level with architecture-specific optimizations that are most times based on fundamentally differing programming paradigms and languages. OpenVX promises to solve this issue for computer vision applications with a royalty-free industry standard that is based on a graph-execution model. Yet, the OpenVX' algorithm space is constrained to a small set of vision functions. This hinders accelerating computations that are not included in the standard. In this paper, we analyze OpenVX vision functions to find an orthogonal set of computational abstractions. Based on these abstractions, we couple an existing domain-specific language (DSL) back end to the OpenVX environment and provide language constructs to the programmer for the definition of user-defined nodes. In this way, we enable optimizations that are not possible to detect with OpenVX graph implementations using the standard computer vision functions. These optimizations can double the throughput on an Nvidia GTX GPU and decrease the resource usage of a Xilinx Zynq FPGA by 50% for our benchmarks. Finally, we show that our proposed compiler framework, called HipaccVX, can achieve better results than the state-of-the-art approaches Nvidia VisionWorks and Halide-HLS.<br

History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs - Esper, Khalil; Teich, Jürgen (Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024), 2024)
Embedded system applications usually have requirements regarding non-functional properties of their execution like latency or power consumption. Enforcement of such requirements can be implemented by a reactive control loop, where an enforcer determines based on a system response (feedback) how to control the system, e.g., by selecting the number of active cores allocated to a program or by scaling their voltage/frequency mode. It is of a particular interest to design enforcement strategies for which it is possible to provide formal guarantees with respect to requirement violations, especially under a largely varying environmental input (workload) per execution. In this paper, we consider enforcement strategies that are modeled by a finite state machine (FSM) and the environment by a discrete-time Markov chain. Such a formalization enables the formal verification of temporal properties (verification goals) regarding the satisfaction of requirements of a given enforcement strategy. In this paper, we propose history-based enforcement FSMs which compute a reaction not just on the current, but on a fixed history of K previously observed system responses. We then analyze the quality of such enforcement FSMs in terms of the probability of satisfying a given set of verification goals and compare them to enforcement FSMs that react solely on the current system response. As experimental results, we present three use cases while considering requirements on latency and power consumption. The results show that history-based enforcement FSMs outperform enforcement FSMs that only consider the current system response regarding the probability of satisfying a given set of verification goals.<br
Keywords: Verification; Runtime Requirement Enforcement; History; Latency

Holistic Actor-Oriented Modeling of Embedded Systems for ESL Power Consumption Evaluation - Rosales, Rafael (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2017)

How Much Forcing is Necessary to Let the Results of Particle Swarms Converge? - Bassimir, Bernd; Schmitt, Manuel; Wanka, Rolf (Proc. Int. Conf. on Swarm Intelligence Based Optimization (ICSIBO), 2014)
In order to improve the behavior of Particle Swarm Optimization (PSO), the classical method is often extended by additional operations. Here, we are interested in how much ``PSO" remains in this case, and how often the extension takes over the computation. We study the variant of PSO that applies random velocities (then called forced moves) as soon as the so-called potential of the swarm falls below a certain bound. We show experimentally that the number of iterations the swarm actually deviates from the classical PSO behavior is small as long as the particles are sufficiently far away from any local optimum. As soon as the swarm comes close to a local optimum, the number of forced moves increases significantly and approaches a value that depends on the swarm size and the problem dimension, but not on the actual fitness function, an observation that can be used as a stopping criterion. Additionally, we provide an explanation for the observed phenomenon in terms of the swarms potential.

HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN) - Ziermann, Tobias; Salcic, Zoran; Teich, Jürgen (Proc. 26th International Conference on Architecture of Computing Systems, 2013)
Designers of distributed embedded control systems face many design challenges related to change of system configuration, functionality and number of participating computing nodes, which affect the usage of the communication bus. The concept of self-adaptivity of participating nodes plays an important role in reducing design effort while guaranteeing high system performance. The dynamic offset adaptation algorithm (DynOAA) for adaptive message scheduling reduces average message response times in CAN-based systems with high bus loads. This technique has in previous work proven its benefit in simulation. However, it is still necessary to test the algorithm in a real physical environment. In this paper, we use FPGAs with their capability of performing rapid system prototyping. Our design space exploration shows that both pure software and pure hardware implementations are possible. However, parts of the software implementation require a significant amount of computation. As a result a mixed HW/SW implementation is proposed. © 2013 Springer-Verlag.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.hwswtr

Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective - Pourmohseni, Behnaz; Glaß, Michael; Henkel, Jörg; Khdr, Heba; Rapp, Martin; Richthammer, Valentina; Schwarzer, Tobias; Smirnov, Fedor; Spieck, Jan; Teich, Jürgen; Weichslgartner, Andreas; Wildermann, Stefan (Journal of Low Power Electronics and Applications, 2020)

Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures - Häublein, Konrad; Reichenbach, Marc; Reiche, Oliver; Özkan, Mehmet Akif; Fey, Dietmar; Hannig, Frank; Teich, Jürgen (Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016)
Image processing algorithms applied on programmable embedded systems very often do not meet the given constraints in terms of real time capability. Mapping these algorithms to reconfigurable hardware solves this issue, but demands further specific knowledge in hardware development. The design process can be accelerated by code generation through high-level synthesis, which is very flexible. However, the quality of synthesis depends on many factors like the provided constraints, code description, and algorithmic complexity. Hence, optimizing these parameters may improve the generated results in terms of logic and memory utilization, as well as data throughput and synthesis duration. In this work, we aim to exploit domain-specific knowledge for a hybrid code description in order to benefit from rapid development through high-level synthesis in combination with throughput optimized generic hardware descriptions. By utilizing code generation techniques, the entire design flow gets accelerated. Our synthesis results show a similar resource utilization and achievable throughput to a pure HDL described hardware
Keywords: Image Processing; High-Level Synthesis; Code Transformation; Hybrid Code Description

Hybrid Energy-Aware Reconfiguration Management on Xilinx Zynq SoCs - Becher, Andreas; Pirkl, Jutta; Herrmann, Achim; Teich, Jürgen; Wildermann, Stefan (Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2016)

Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers - Spieck, Jan; Sixdenier, Pierre-Louis André Edouard; Esper, Khalil; Wildermann, Stefan; Teich, Jürgen (2023 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE), 2023)

Hybrid Global/Local Search Strategies for Dynamic Voltage Scaling in Embedded Multiprocessors - Bhattacharyya, Shuvra S.; Teich, Jürgen; Zitzler, Eckart; Bambha, Neil (Proc. 9th Int. Workshop on Hardware/Software Co-Design, 2001)
In this paper, we explore a hybrid global/local search optimization framework for dynamic voltage scaling in embedded multiprocessor systems. The problem is to find, for a multiprocessor system in which the processors are capable of dynamically varying their core voltages, the optimum voltage levels for all the tasks in order to minimize the average power consumption under a given performance constraint. An effective local search approach for static voltage scaling based on the concept of a period graph has been demonstrated in [1]. To make use of it in an optimization problem, the period graph must be integrated into a global search algorithm. Simulated heating, a general optimization framework developed in [19], is an efficient method for precisely this purpose of integrating local search into global search algorithms. However, little is known about the management of computational (compile-time) resources between global search and local search in hybrid algorithms, such as those coordinated by simulate d heating. In this paper, we explore various hybrid search management strategies for power optimization under the framework of simulated heating. We demonstrate that careful search management leads to significant power consumption improvement over add-hoc global search/local search integration, and explore alternative approaches to performing hybrid search management for dynamic voltage scaling.
UnivIS-Import:2015-04-16:Pub.2001.tech.IMMD.inform.hybrid
Keywords: Dynamic voltage scaling; Simulated heating

Hybrid Network-on-Chip Simulation - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Modeling and Simulation of Invasive Applications and Architectures, 2019)
CRIS-Team WoS Importer:2019-11-08

Hybrid Optimization Techniques for System-Level Design Space Exploration - Glaß, Michael; Teich, Jürgen; Lukasiewycz, Martin; Reimann, Felix (Handbook of Hardware/Software Codesign, 2017)
Keywords: dataflow; SysteMoC; SystemCoDesigner

Identifying FPGA IP-Cores based on Lookup Table Content Analysis - Ziener, Daniel; Aßmus Stefan, Aßmus Stefan; Teich, Jürgen (Proceedings of 16th International Conference on Field Programmable Logic and Applications, 2006)
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP protection against unlicensed usage. We show methods to extract the content of the lookup tables in a design from a binary bitfile of Xilinx Virtex-II and Virtex-II Pro FPGAs. To identify a core, we compare the number of unique functions from lookup tables of the core with the lookup tables extracted from a product with an FPGA from an accused company. Also placement information can be used for increasing the reliability of the result. With these methods, no additional sources or information must be inquired from the accused company. These techniques can be used for netlist and bitfile cores, so a wide spectrum of cores can be identified. © 2006 IEEE.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.identi

IGOR, get me the Optimum! Prioritizing Important Design Decisions During the DSE of Embedded Systems - Smirnov, Fedor; Pourmohseni, Behnaz; Glaß, Michael; Teich, Jürgen (CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis, 2019)
Design Space Exploration (DSE) techniques for complex embedded systems must cope with a huge variety of applications and target architectures, as well as a wide spectrum of objectives and constraints. In particular, existing design automation approaches are either problem-independent, in that they do not exploit any knowledge about the optimization problem at hand, or are tailored to specific a priori assumptions about the problem and/or a specific set of design objectives. While the latter are only applicable within a very limited scope of design problems, the former may struggle to deliver high-quality solutions for problems with large design spaces and complex design objectives. As a remedy, we propose Importance-Guided Order Rearrangement (IGOR) as a novel approach for DSE of embedded systems. Instead of relying on a priori problem knowledge, IGOR uses a machine-learning-inspired technique to dynamically analyze the importance of design decisions, i.e., the impact that these decisions—within the specific problem that is being optimized—have on the quality of explored problem solutions w.r.t. the given design objectives. Throughout the DSE, IGOR uses this information to guide the optimization towards the most promising regions of the design space. Experimental results for a variety of applications from different domains of embedded computing and for different optimization scenarios give evidence that the proposed approach is both scalable and adaptable, as it can be used for the optimization of systems described by several thousands constraints, where it outperforms both problem-specific and problem-independent optimization approaches and achieves ε-dominance improvements of up to 95%.<br
Keywords: DSE; Multi-Objective Optimization; System Synthesis

Igor, get me the optimum! Prioritizing important design decisions during the DSE of embedded systems - Smirnov, Fedor; Pourmohseni, Behnaz; GLAß, Michael; Teich, Jürgen (Transactions on Embedded Computing Systems, 2019)
Design Space Exploration (DSE) techniques for complex embedded systems must cope with a huge variety of applications and target architectures as well as a wide spectrum of objectives and constraints. In particular, existing design automation approaches are either problem-independent, in that they do not exploit any knowledge about the optimization problem at hand, or are tailored to specific a priori assumptions about the problem and/or a specific set of design objectives. While the latter are only applicable within a very limited scope of design problems, the former may struggle to deliver high-quality solutions for problems with large design spaces and/or complex design objectives. As a remedy, we propose Importance-Guided Order Rearrangement (IGOR) as a novel approach for DSE of embedded systems. Instead of relying on an a priori problem knowledge, IGOR uses a machine-learning-inspired technique to dynamically analyze the importance of design decisions, i.e., the impact that these decisions-within the specific problem that is being optimized-have on the quality of explored problem solutions w.r.t. the given design objectives. Throughout the DSE, IGOR uses this information to guide the optimization towards the most promising regions of the design space. Experimental results for a variety of applications from different domains of embedded computing and for different optimization scenarios give evidence that the proposed approach is both scalable and adaptable, as it can be used for the optimization of systems described by several thousands constraints, where it outperforms both problem-specific and problem-independent optimization approaches and achieves ε-dominance improvements of up to 95%.
CRIS-Team Scopus Importer:2019-10-22
Keywords: Constrained combinatorial problems; Design space exploration; Embedded systems; Multiobjective optimization

Impact of loop tiling on the controller logic of acceleration engines - Dutta, Hritam; Zhai, Jiali; Hannig, Frank; Teich, Jürgen (Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), 2009)
High computational effort in modern signal and image processing applications often demands for special purpose accelerators in a system on chip (SoC). New high level synthesis methodologies enable the automated design of such programmable or non-programmable accelerators. Loop tiling is a widely used transformation in such methodologies for dimensioning of such accelerators in order to match inherent massive parallelism of considered algorithms with available functional units and processor elements. Innately, the applications are data-flow dominant and have almost no control flow, but the application of tiling techniques has the disadvantage of a more complex control and communication flow. In this paper, we present a methodology for the automatic generation of the control engines of such accelerators. The controller orchestrates the data transfer and computation. The effect of tiling on area, latency, and power overhead of the controller is studied in detail. It is shown that the controller has a substantial overhead of up to 50% in for different tiling and throughput parameters. The energy-delay product is also used as a metric for identifying optimal accelerator designs. © 2009 IEEE.

Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines - Dutta, Hritam; Zhai, Jiali; Hannig, Frank; Teich, Jürgen (Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.impact

Importance measures in time-dependent reliability analysis and system design - Aliee, Hananeh; Borgonovo, Emanuele; Glaß, Michael; Teich, Jürgen (Proceedings of the Annual European Safety and Reliability Conference (ESREL '15), 2015)
This paper is an extended summary of findings of an on-going research project on the use of importance measures to improve the design and reliability of digital systems. Continued shrinking in the size of transistors makes the reliability of digital systems an important aspect to be contemplated at design time. In this paper, we propose to use reliability importance measures to complement existing reliability analysis and optimization techniques. In fact, reliability importance measures can be used within such analysis techniques as indicators of how a given component contributes to the reliability of a system. Hence, to increase reliability, one selects the most important components as candidates for the optimization or improvement of system reliability (using, e. g., hardware/software redundancy). However, in the design of digital systems, additional attributes (e.g., power consumption, timing delay, and/or cost) are important as well and, thus, require for a multi-objective optimization to investigate the available trade-offs. Our goal is to introduce a Boolean-based importance measure analysis to integrate and assist the optimization process. In doing so, we look for importance measures which are time independent, as a time-dependent approach would not be as informative as a time-independent approach for the type of problems dealt with in the research. We then illustrate a new time-independent importance measure, based on the findings in (Borgonovo, Aliee, Glaß, & Teich 2015). Also, for the purpose of investigating the cost impact of components, we illustrate a cost-aware importance measure under investigation in (Aliee, Borgonovo, Glaß, & Teich 2015b).

Improved time domain simulation of optical multimode intrasystem interconnects - Gerling, Jens; Mrozynski, Gerd; Schrage, Jürgen; Stübbe, Oliver; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe, 2003)
To increase the bandwidth of high-performance intrasystem interconnections, optical multimode waveguides can be used. Since the design procedure of optical interconnections has to be widely compatible with conventional design processes, adequate simulation methods are required. This paper presents an improved time domain method for simulating the signal transmission along optical multimode interconnections. The improvements mainly result from the more efficient method for the piecewise approximation of the waveguides step responses by a few exponential functions. The adapted semi-analytical recursive convolution method decreases the computation times. © 2003 IEEE.
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.improv

Improvements in LTE-Advanced Time Series Prediction with Dimensionality Reduction Algorithms - Mercader, Alexandra; Ah Sue, Jonathan; Hasholzner, Ralph; Brendel, Johannes (Proc. of the IEEE 5G World Forum, 2018)
Prediction of control channel signaling messages during an active Long Term Evolution-Advanced (LTE-A) connection with the network is a promising technique to reduce power consumption of mobile devices. In order to reduce the prediction’s computational complexity and thus, the power consumed by the predictor itself, various dimensionality reduction algorithms are evaluated in this paper. Moreover, specific windowing and normalization pre-processing steps are proposed to support the heterogeneous binary and integer time series data of LTE control channel messages. Using a simple Feed Forward Neural Network (FFNN) predictor, four dimensionality reduction algorithms, Principal Component Analysis (PCA), Independent Component Analysis (ICA), Autoencoder (AE), and Deep AE, are compared with respect to the prediction accuracy. Experiments based on live network data show that PCA achieves the best performance and allows to successfully reduce LTE-A control channel time series data from 450 to 45 dimensions without degrading the prediction accuracy compared to a FFNN predictor without dimensionality reduction.

Improving Automatic Design Space Exploration by Integrating Symbolic Techniques into Multi-Objective Evolutionary Algorithms - Haubelt, Christian; Schlichter, Thomas; Teich, Jürgen (International Journal of Computational Intelligence Research, 2006)
UnivIS-Import:2015-04-14:Pub.2006.tech.IMMD.inform.improv_1

Improving Bitonic Sorting by Wire Elimination - Mühlenthaler, Moritz; Wanka, Rolf (Proc. 23rd PARS-Workshop on Parallel Systems and Architectures of the 23rd Int. Conf. on Architecture of Computing Systems (ARCS), 2010)
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.infalg._impro

Improving EA-based design space exploration by utilizing symbolic feasibility tests - Schlichter, Thomas; Haubelt, Christian; Teich, Jürgen (Proceedings of Genetic and Evolutionary Computation Conference (GECCO), 2005)
This paper will propose a novel approach in combining Evolutionary Algorithms with symbolic techniques in order to improve the convergence of the algorithm in the presence of large search spaces containing only few feasible solutions. Such problems can be encountered in many real-world applications. Here, we will use the example of design space exploration of embedded systems to illustrate the benefits of our approach. The main idea is to integrate symbolic techniques into the Evolutionary Algorithm to guide the search towards the feasible region. We will present experimental results showing the advantages of our novel approach. Copyright 2005 ACM.
Keywords: Application; Multi-objective optimization; Speedup technique

Improving Performance of Controller Area Network (CAN) by Adaptive Message Scheduling - Ziermann, Tobias; Salcic, Zoran; Teich, Jürgen (Self-Organization in Embedded Real-Time Systems, 2012)
UnivIS-Import:2015-04-20:Pub.2012.tech.IMMD.inform.improv

Improving platform-based system synthesis by satisfiability Modulo theories solving - Teich, Jürgen; Haubelt, Christian; Eberl, Michael; Reimann, Felix; Glaß, Michael (Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010)
Due to the ever increasing system complexity, deciding whether a given platform is sufficient to implement a set of applications under given constraints becomes a serious bottleneck in platform-based design. As a remedy, the work at hand proposes a novel automatic platform-based system synthesis procedure, inspired by techniques developed in the context of automatic system verification known as Satisfiability Modulo Theories. It tightly couples the computation of a feasible allocation and binding with nonfunctional constraint checking where, in contrast to existing approaches, not only linear constraints but even nonlinear constraints are supported. This allows to efficiently prove whether there exists a feasible implementation of a set of applications on the given platform with respect to both, functional and nonfunctional constraints. Moreover, an approach for early learning based on feasibility checking of partial implementations is proposed that can signifiantly improve the synthesis runtime, especially in case the selected platform imposes stringent constraints on the implementation. The effectiveness of this approach is shown for an automotive ECU network design that requires Modular Performance Analysis to ensure non-functional nonlinear timing constraints.

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems - Ziener, Daniel (2017)
In this treatise,  my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration is outlined. The efficiency of reconfigurable systems can be improved by loading optimized data paths on-the-fly on an FPGA fabric. This technique was applied to the acceleration of SQL queries  for large database applications as well as for image and signal processing applications. The focus was not only on performance improvements and resource efficiency, but also the energy efficiency has been significantly improved. In the area of reliability, countermeasures against radiation-induced faults and  aging effects for long mission times were investigated and applied to SRAM-FPGA-based satellite systems. Finally, to increase the security of cryptographic FPGA-based implementations against physical attacks, i.e., side-channel and fault injection analysis as well as reverse engineering, it is proposed to transform static circuit structures into dynamic ones by applying dynamic partial reconfiguration.
Keywords: RC

Improving SAT Solving Using Monte Carlo Tree Search-based Clause Learning - Keszöcze, Oliver; Schmitz, Kenneth; Schloeter, Jens; Drechsler, Rolf (Advanced Boolean Techniques - Selected Papers from the 13th International Workshop on Boolean Problems, 2020)
Most modern state-of-the-art Boolean Satisfiability (SAT) solvers are based on the Davis-Putnam-Logemann-Loveland algorithm and exploit techniques like unit propagation and Conflict-Driven Clause Learning (CDCL). Even though this approach proved to be successful in practice, the success of the Monte Carlo Tree Search (MCTS) algorithm in other domains led to research in using it to solve SAT problems. A recent approach extended the attempt to solve SAT using a MCTS-based algorithm by adding CDCL. We further analyzed the behavior of that approach by using visualizations of the produced search trees and based on the analysis introduced multiple heuristics improving different aspects of the quality of the learned clauses. While the resulting solver can be used to solve SAT on its own, the real strength lies in the learned clauses. By using the MCTS solver as a preprocessor, the learned clauses can be used to improve the performance of existing SAT solvers.<br
Keywords: SAT; Satisfiability; SAT Solver; Monte Carlo Tree Search; Heuristic; SAT Preprocessing

Improving system level design space exploration by incorporating SAT-solvers into multi-objective evolutionary algorithms - Schlichter, Thomas; Lukasiewycz, Martin; Haubelt, Christian; Teich, Jürgen (Proceedings of IEEE Computer Society Annual Symposium on VLSI. Karlsruhe, 2006)
Automatic design space exploration at the system level is the task of finding optimal or close to optimal mappings for a set of applications onto an optimized architecture. Especially, finding a feasible binding of processes onto resources that permit the communications imposed by data dependencies is known to be a NP-complete task which demands the use of heuristic optimization approaches. Nearly all optimization approaches known from literature will fail in design spaces containing only a few feasible solutions. In this paper, we propose a novel approach based on the combination of Multi-Objective Evolutionary Algorithms and SAT-solvers to overcome these drawbacks. We will provide experimental results showing the efficiency of our novel methodology for synthetic and real life test cases. © 2006 IEEE.

Incorporating graceful degradation into embedded system design - Glaß, Michael; Haubelt, Christian; Lukasiewycz, Martin; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE 2009), 2009)
In this work, the focus is put on the behavior of a system in case a fault occurs that disables the system from executing its applications. Instead of executing a random subset of the applications depending on the fault, an approach is presented that optimizes the systems structure and behavior with respect to a possible graceful degradation. It includes a degradation-aware reliability analysis that guides the optimization of the resource allocation and function distribution, and provides data-structures for an efficient online degradation algorithm. Thus, the proposed methodology covers both, the design phase with a structural optimization and the online phase with a behavioral optimization of the system. A case study shows the effectiveness of the proposed approach. © 2009 EDAA.

Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System - Bobda, Christophe; et al. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), 2003)
Static FPGA (Field Programmable Gate Arrays) designs are efficient for data flow oriented applications while they are inefficient for control flow. We show that partial dynamic reconfigured designs can be more efficient than static designs, if the application contains exclusive coarse grain sections. Our case study is a multi-controller system, where various controller modules are exchanged during runtime depending on the operating regime of the controlled system. We present a multi-controller architecture as embedded system based on reconfigurable hardware. Portions of the FPGA design are exchanged during runtime to load new controller modules while other portions containing basic operational functions are static. We implemented a proto-type to proof the concept and discuss the results.
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.increa

Increasing the Flexibility in FPGA-Based Reconfigurable Platforms: The Erlangen Slot Machine - Ahmadinia, Ali; Bobda, Christophe; Haller, Thomas; Linarth, Andre Guilherme; Majer, Mateusz; Teich, Jürgen (IEEE 2005 Conference on Field-Programmable Technology, 2005)
We present a new concept as well as the implementation of an FPGA-based reconfigurable platform, the Erlangen Slot Machine (ESM). One main advantage of this platform is the possibility for each module to access its periphery independent from its location through a programmable crossbar, allowing an unrestricted relocation of modules on the device. Furthermore, we propose different intermodule communication structures. © 2005 IEEE.
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.increa

Initial Population Construction for Convergence Improvement of MOEAs - Haubelt, Christian; Gamenik, Jürgen; Teich, Jürgen (Evolutionary Multi-Criterion Optimization, 2005)

Insights on the Configuration and Performances of SOME/IP Service Discovery - Seyler, Jan; Navet, Nicolas; Fejoz, Loïc; Teich, Jürgen (SAE International Journal of Passenger Cars - Electronic and Electrical Systems, 2015)

In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing - Becher, Andreas; Teich, Jürgen (15th International Workshop on Data Management on New Hardware (DaMoN) Held with ACM SIGMOD/PODS 2019, 2019)
Hardware Accelerators for Query Processing are often optimized to filter as much data as possible before the results are stored to memory or sent to the user. However, the static nature of such optimized accelerators limits the amount of operators they can implement to a fixed amount configured at synthesis time. If not all operators can be pushed down to the accelerator, the decision which operators should be pushed down has therefore a big impact on the resulting data size and overall query execution time. Statistics are therefore used to determine which operators to push onto the hardware accelerators. Gathering these statistics is therefore of utmost importance. In this paper we present multiple possibilities to gather statistics within an accelerator while executing a partial query. These statistics can be gradually improved with every execution of the accelerator be of use in future queries during the query planning phase.<br

Integrated Modeling Using Finite State Machines and Dataflow Graphs - Falk, Joachim; Haubelt, Christian; Teich, Jürgen (Handbook of Signal Processing Systems, 2013)

Integrated Modeling Using Finite State Machines and Dataflow Graphs - Falk, Joachim; Haubelt, Christian; Zebelein, Christian; Teich, Jürgen (Handbook of Signal Processing Systems, 2013)
In this chapter, different application modeling approaches based on the integration of finite state machines with dataflow models are reviewed. Restricted Models of Computation (MoC) may be exploited in design methodologies to generate optimized hardware/software implementations from a given application model. A particular focus is put on the analyzability of these models with respect to schedulability and the generation of efficient schedule implementations. In this purpose, clustering methods for model refinement and schedule optimization are of particular interes

Integrated Modeling Using Finite State Machines and Dataflow Graphs - Falk, Joachim; Keinert, Joachim; Haubelt, Christian; Teich, Jürgen; Zebelein, Christian (Handbook of Signal Processing Systems, 2010)
In this chapter, different application modeling approaches based on the integration of finite state machines with dataflow models are reviewed. A particular focus is put on the analyzability of these models and the way how restricted Models of Computation are exploited in design methodologies to optimize the hardware/- software implementation of a given application mode

Integrated Modeling Using Finite State Machines and Dataflow Graphs - Falk, Joachim; Neubauer, Kai; Haubelt, Christian; Zebelein, Christian; Teich, Jürgen (Handbook of Signal Processing Systems, 2018)
In this chapter, different application modeling approaches based on the integration of finite state machines with dataflow models are reviewed. Many well-known Models of Computation (MoC) that are used in design methodologies to generate optimized hardware/software implementations from a model-based specification turn out to be special cases thereof. A particular focus is put on the analyzability of these models with respect to schedulability and the generation of efficient schedule implementations. Here, newest results on clustering methods for model refinement and schedule optimization by means of quasi-static scheduling are presente
Keywords: data flow; dataflow; clustering; scheduling; quasi-static scheduling

Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models - Falk, Joachim; Zebelein, Christian; Haubelt, Christian; Teich, Jürgen; Dorsch, Rainer (3. ITG/GI/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2010)

Integration of FPGAs in Database Management Systems: Challenges and Opportunities - Becher, Andreas; Beena Gopalakrishnan Nair, Lekshmi; Broneske, David; Drewes, Tobias; Gurumurthy, Bala; Meyer-Wegener, Klaus; Pionteck, Thilo; Saake, Gunter; Teich, Jürgen; Wildermann, Stefan (Datenbank-Spektrum, 2018)

Interface Synthesis for FPGA Based VLSI Processor Arrays - Bednara, Marcus; Teich, Jürgen (Proc. of The International Conference on Engineering of Reconfigurable Sytsems and Algorithms, 2002)
UnivIS-Import:2015-04-16:Pub.2002.tech.IMMD.inform.interf

Interfacing Hardware and Software - Eisenring, Michael; Teich, Jürgen (Proc. of FPL'98, the Conf. on Field-Programmable Logic and Applications, Tallin, Estonia, Springer Lecture Notes in Computer Science (LNCS) 1482, 1998)

Interprocedural Placement-Aware Configuration Prefetching for FPGA-based Systems - Sim, Joon Edward; Wong, Weng Fai; Walla, Gregor; Ziermann, Tobias; Teich, Jürgen (Proc. 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, 2010)
One of the major impediments to deploying partially run-time reconfigurable FPGAs as hardware accelerators is the time overhead involved in loading the hardware modules. While configuration prefetching is an effective method that can be employed to reduce this overhead, mispredicted prefetches may worsen the situation by increasing the number of reconfigurations needed. In this paper, we present a static algorithm for configuration prefetching in partially reconfigurable FPGAs that minimizes the reconfiguration overhead. By making use of profiling, the interprocedural control flow graph, and the placement information of hardware modules, our algorithm predicts hardware execution and tries to prefetch hardware modules as early as possible while minimizing the risk of mis-predictions. Our experiments show that our algorithm performs significantly better than current-state-of-the- art prefetching algorthms for control-bound applications. © 2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.interp

Introduction - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Modeling and Simulation of Invasive Applications and Architectures, 2019)
CRIS-Team WoS Importer:2019-11-08

Introduction to Hardware/Software Codesign - Ha, Soonhoi; Teich, Jürgen; Haubelt, Christian; Glaß, Michael; Mitra, Tulika; Dömer, Rainer; Eles, Petru; Shrivastava, Aviral; Gerstlauer, Andreas; Bhattacharyya, Shuvra S. (Handbook of Hardware/Software Codesign, 2017)
Keywords: dataflow; SysteMoC; SystemCoDesigner

Introduction to Invasive Computing - Teich, Jürgen; Henkel, Jörg; Herkersdorf, Andreas (Invasive Computing, 2022)

Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors - Hannig, Frank; Koch, Dirk (Journal of Signal Processing Systems, 2021)
CRIS-Team WoS Importer:2021-10-08

Introduction to the special issue on domain-specific multicore computing - Narayanan, Vijaykrishnan; Teich, Jürgen (Transactions on Embedded Computing Systems, 2014)

Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures - Hannig, Frank; Herkersdorf, Andreas (Journal of Systems Architecture, 2015)

InvadeSIM-A Simulation Framework for Invasive Parallel Programs and Architectures - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Modeling and Simulation of Invasive Applications and Architectures, 2019)
CRIS-Team WoS Importer:2019-11-08

InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Tool presentation at the University Booth, 2016)

Invasive Algorithms and Architectures - Teich, Jürgen (it - Information Technology, 2008)
UnivIS-Import:2015-03-09:Pub.2008.tech.IMMD.inform.invasi_2

Invasive Computing: An Overview - Teich, Jürgen; Henkel, Jörg; Herkersdorf, Andreas; Schmitt-Landsiedel, Doris; Schröder-Preikschat, Wolfgang; Snelting, Gregor (Multiprocessor System-on-Chip - Hardware Design and Tool Integration, 2011)
A novel paradigm for designing and programming future parallel computing systems called invasive computing is proposed. The main idea and novelty of invasive computing is to introduce resource-aware programming support in the sense that a given program gets the ability to explore and dynamically spread its computations to neighbour processors in a phase called invasion, then to execute portions of code of high parallelism degree in parallel based on the available invasible region on a given multi-processor architecture. Afterwards, once the program terminates or if the degree of parallelism should be lower again, the program may enter a retreat phase, deallocate resources and resume execution again, for example, sequentially on a single processor. To support this idea of self-adaptive and resource-aware programming, not only new programming concepts, languages, compilers and operating systems are necessary but also revolutionary architectural changes in the design of Multi-Processor Systems-on-a-Chip must be provided so to efficiently support invasion, infection and retreat operations involving concepts for dynamic processor, interconnect and memory reconfiguration. This contribution reveals the main ideas, potential benefits and challenges for supporting invasive computing at the architectural, programming and compiler level in the future. It serves to give an overview of required research topics rather than being able to present mature solutions yet. © 2011 Springer Science+Business Media, LLC.
UnivIS-Import:2015-04-20:Pub.2011.tech.IMMD.IMMD4.invasi
Keywords: B (Hardware); B.7 (Hardware: Integrated Circuits); C (Computer Systems Organisation); C.1 (Computer Systems Organisation; Processor Architectures); C.3 (Computer Systems Organisation: Special-Purpose and Application-Based Systems)

Invasive Computing - Anantharajaiah, Nidhi; Asfour, Tamim; Bader, Michael; Bauer, Lars; Becker, Jürgen; Bischof, Simon; Brand, Marcel; Bungartz, Hans-Joachim; Eichler, Christian; Esper, Khalil; Falk, Joachim; Fasfous, Nael; et al. (FAU University Press, 2022)

Invasive Computing - Common Terms and Granularity of Invasion - Teich, Jürgen; Schröder-Preikschat, Wolfgang; Herkersdorf, Andreas (Cornell University Library, 2013)
UnivIS-Import:2015-04-02:Pub.2013.tech.IMMD.IMMD4.invasi

Invasive Computing - Concepts and Overheads - Teich, Jürgen; Weichslgartner, Andreas; Oechslein, Benjamin; Schröder-Preikschat, Wolfgang (Proc. of the Forum on Specification & Design Languages (FDL), 2012)
In this paper, we present the basic concepts of invasive computing and subsequently analyze the performance overheads of invasive computing applications on several multi- and many-core architectures. The nature of these is to claim and free resources dynamically at run-time to increase resource efficiency of future MPSoC architectures while not sacrificing speedup in comparison to traditional, statically mapped applications. This holds true especially for programs with highly dynamic parallelism profiles. Based on a formal notation of speedup and resource efficiency for invasive parallel programs, we present a real SPARC LEON-based MPSoC system implementation to evaluate achievable resource efficiencies for realistic workload scenarios showing that the real-measured overhead of invasion can be kept very low and resource efficiencies of up to 100% will become possible without a considerable drop in speedup compared to non-invasive programs using statically allocated resources. Also, we present invasion overheads for tightly-coupled processor arrays (TCPAs) that avoid the creation of threads and use hardware-based signaling concepts to invade processing elements. Finally, we present results how expensive invasive computing overheads may be by proposing two implementations on existing MPSoC platforms, namely the Tilera TilePro64 architecture and on Intel's SCC for comparison. © 2012 ECSI.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.invasi_1

Invasive Computing - Editorial - Teich, Jürgen (it - Information Technology, 2016)

Invasive Computing for Mapping Parallel Programs to Many-Core Architectures - Weichslgartner, Andreas; Wildermann, Stefan; Glaß, Michael; Teich, Jürgen (Springer, 2018)