3D Exploration of Software Schedules for DSP Algorithms - Bhattacharyya, Shuvra S.; Teich, Jürgen; Zitzler, Eckart (Proc. CODES'99, the 7th Int. Workshop on Hardware/Software Co-Design, 1999)
This paper addresses the problem of exploring tradeoffs between program memory, data memory and execution time requirements (3D) for DSP algorithms specified by data flow graphs. Such an exploration is of utmost importance for being able to analyze the feasibility and range of possible software solutions as part of a hardware/software codesign methodology where the target processor and the code generation style may lead to complete different solutions of the same specification. For solving this multi-objective optimization problem, an Evolutionary Algorithm approach is applied. In particular, a new Pareto-optimization algorithm is introduced. For different well-known target DSP processors, the Pareto-fronts are analyzed and compared.
UnivIS-Import:2015-04-16:Pub.1999.tech.IMMD.inform.3dexpl

3D Exploration of Uniprocessor Schedules for DSP Algorithms - Teich, Jürgen; Zitzler, Eckart (1998)

3D Person Tracking with a Color-Based Particle Filter - Wildermann, Stefan; Teich, Jürgen (Robot Vision, 2008)
Person tracking is a key requirement for modern service robots. But methods for robot vision have to fulfill several constraints: they have to be robust to errors evoked by noisy sensor data, they have to be able to work under real-world conditions, and they have to be fast and computationally inexpensive. In this paper we present an approach for tracking the position of a person in 3D based on a particle filter. In our framework, each particle represents a hypothesis for the 3D position, velocity and size of the person's head being tracked. Two cameras are used for the evaluation of the particles. The particles are weighted by projecting them onto the camera image and applying a color-based perception model. This model uses skin color cues for face tracking and color histograms for body tracking. In contrast to feature-based approaches, our system even works when the person is temporary or partially occluded. © 2008 Springer-Verlag Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.3dpers

3-SAT on CUDA: Towards a Massively Parallel SAT Solver - Schönfeld, Fabian; Meyer, Quirin; Stamminger, Marc; Wanka, Rolf (Proc. High Performance Computing and Simulation Conference (HPSC), 2010)
This work presents the design and implementation of a massively parallel 3-SAT solver, specifically targeting random problem instances. Our approach is deterministic and features very little communication overhead and basically no load-balancing cost at all. In the context of most current parallel SAT solvers running only on a handful of cores, we implemented our solver on Nvidia's CUDA platform, utilizing more than 200 parallel streaming processors, and employing several millions of threads to work through single problem instances. As most common sequential solver techniques had to be discarded, our approach is additionally supported by a new set of global heuristics, designed specifically to be easily exploited by the underlying thread parallelism. ©2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.IMMD9.3saton
Keywords: GPGPU; Load balancing and sharing; Random 3-SAT; Thread level parallelism

Aarith: An Arbitrary Precision Number Library - Keszöcze, Oliver; Brand, Marcel; Witterauf, Michael; Heidorn, Christian; Teich, Jürgen (ACM/SIGAPP Symposium On Applied Computing, 2021)

ABACUS: ASIP-based Avro Schema-customizable Parser Acceleration on FPGAs - Hahn, Tobias; Schüll, Daniel; Wildermann, Stefan; Teich, Jürgen (IEEE Proceedings of the 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2024)
Big Data applications frequently process data streams encoded in semi-structured data formats such as JSON, Protobuf, or Avro. Parsing these data formats into a representation to then be processed by a CPU frequently takes up a major share of the processing time. As a remedy, JSON and Avro FPGA accelerators have been introduced that can parse the data directly in the data path, offloading this workload from the CPU without requiring any additional data movement. However, these accelerators are schema-specific circuits that require time-consuming resynthesis processes for schema adaptations. This is particularly critical in Big Data applications, where multiple schemas may be in use simultaneously. As a remedy, we present an application-specific instruction set processor (ASIP) architecture for parsing Avro data on FPGAs. An instruction program controls the ASIP to parse a specific schema. Any schema change therefore only requires the loading of a new instruction sequence into an instruction memory. It is also shown that this approach is more resource-efficient than related work, as functional units only need to be instantiated once for each Avro data type. Our experimental evaluation shows that we can achieve a throughput of 707-818 MB/s per kLUT which is about 7 to 14 times higher than the throughput per LUT achieved in related work. <br
Keywords: Avro; parsing; FPGA; semi-structured data; accelerator

A Bibliometric Approach for Detecting the Gender Gap in Computer Science - Mattauch, Sandra; Lohmann, Katja; Hannig, Frank; Lohmann, Daniel; Teich, Jürgen (Communications of the ACM, 2020)
Keywords: Gender gap; Computer science; Frauenanteil; MINT; Informatik

A Binary Time Series Model of LTE Scheduling for Machine Learning Prediction - Ah Sue, Jonathan; Hasholzner, Ralph; Brendel, Johannes; Kleinsteuber, Martin; Teich, Jürgen (1st International Workshops on Foundations and Applications of Self-Adaptive and Self-Organizing Systems (SASO 2016)Self-Organizing Systems (SASO 2016), 2016)

A bus-based SoC architecture for flexible module placement on reconfigurable FPGAs - Oetken, Andreas; Wildermann, Stefan; Teich, Jürgen; Koch, Dirk (Proceedings of International Conference on Field-Programmable Logic and Applications (FPL'10), 2010)
This paper proposes an FPGA-based System-on-Chip (SoC) architecture with support for dynamic runtime reconfiguration. The SoC is divided into two parts, the static embedded CPU sub-system and the dynamically reconfigurable part. An additional bus system connects the embedded CPU subsystem with modules within the dynamic area, offering a flexible way to communicate among all SoC components. This makes it possible to implement a reconfigurable design with support for free module placement. An enhanced memory access method is included for high-speed access to an external memory. The dynamic part includes a streaming technology which implements a direct connection between reconfigurable modules. The paper describes the architecture and shows the advantages in a smart camera case study. © 2010 IEEE.

Accelerating Design Space Exploration - Haubelt, Christian; Teich, Jürgen (Proceedings of 5th International Conference on ASIC (ASICON 2003), 2003)

Accelerating design space exploration using Pareto-front arithmetics [SoC design] - Haubelt, Christian; Teich, Jürgen (Proceedings ASP-DAC 2003, Asia and South Pacific Design Automation Conference, 2003)
In this paper, we propose an approach for the synthesis of heterogeneous (embedded) systems, while exploiting a hierarchical problem structure. Particular to our approach is that we explore the set of so-called Pareto-optimal solutions, i.e., optimizing multiple objectives simultaneously. Since system complexity grows steadily, leading to giant search spaces which demand new strategies in design space exploration, we propose Pareto-front arithmetics (PFA), using results of subsystems to construct implementations of the top-level system. This way, we are able to reduce the exploration time dramatically. An example of an MPEG4 coder is used to show the benefit of this approach in real-life applications.

Accelerating DNNs using Weight Clustering on RISC-V Custom Functional Units - Sabih, Muhammad; Sesli, Batuhan; Hannig, Frank; Teich, Jürgen (Proceedings of the Conference on Design, Automation and Test in Europe (DATE), 2024)

Acceleration of a Relative Positioning Framework - Gnezdilov, Alexandr; Wittmann, Stefan; Helwig, Sabine; Kókai, Gabriella (International Journal of Computational Intelligence Research, 2009)
UnivIS-Import:2015-03-09:Pub.2009.tech.FT.FT-KLMEFK.accele

Acceleration of multiresolution imaging algorithms: A comparative study - Membarth, Richard; Kutzer, Philip; Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2009)
In this paper we consider a multiresolution filter and its realization on the Cell BE and GPUs. We not only present common and specific optimization strategies undertaken for obtaining maximum performance on these architectures, but also how to obtain a speedup of 6.57x and 33.24x compared to an optimized OpenMP baseline implementation. Furthermore, we also undertake automated configuration space exploration of different partitioning possibilities for selection of best tiling parameters. © 2009 IEEE.

Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays - Sousa, Éricles; Tanase, Alexandru-Petru; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Paul, Johny; Stechele, Walter; Kröhnert, Manfred; Asfour, Tamim (Proc. 25th Workshop on Parallel Systems and Algorithms, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.accele_6

Acceleration of SQL Restrictions and Aggregations through FPGA-based Dynamic Partial Reconfiguration - Dennl, Christopher; Ziener, Daniel; Teich, Jürgen (Proc. IEEE International Field-Programmable Custom Computing Machines Symposium, 2013)
SQL query processing on large database systems is recognized as one of the most important emerging disciplines of computing nowadays. However, current approaches do not provide a substantial coverage of typical query operators in hardware. In this paper, we provide an important step to higher operator coverage by proposing a) full dynamic data path generation for support also complex operators such as restrictions and aggregations. b) Also, an analysis of the computation times of a real database queries when running on a normal desktop computer is proposed to show that c) speedups ranging between 4 and 50 are obtainable by providing generative support also for the important restrict and aggregate operators using FPGAs. © 2013 IEEE.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.accele

Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays - Sousa, Éricles; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, 2013)
Nowadays, computer vision algorithms have countless application domains. On the one hand, these algorithms are typically computationally demanding, on the other hand, they are often used in embedded systems, which have stringent constraints on, e. g., size or power. In this work, we present the benefits of mapping compute-intensive imaging algorithms on programmable massively parallel processor arrays. More specific, we propose different variants of a combined corner and edge detection algorithm, the Harris Corner Detector (HCD), map these variants onto tightly-coupled processor arrays (TCPAs), and prototype the TCPA architecture, executing the different HCD implementations, in FPGA technology. Because floating-point operations are very costly in FPGAs, we use fixed-point arithmetic in our design, and evaluate our implementation by means of accuracy and performance against two state-of-the-art implementations: (a) the OpenCV library of programming functions for real-time computer vision, using 64-bit floating-point precision, and (b) a 32-bit fixed-point DSP-based embedded system. The accuracy of our work is evaluated by considering the number of corners detected. Here, our approach achieves an average error of less than 1.5% when compared with a reference implementation. Our different variants, trading accuracy for performance, are mapped to the programmable processor elements of a TCPA. Here, the fastest TCPA implementation achieves a 55 times higher frame rate than a state-of-the-art implementation of the HCD on a digital signal processor. Finally, we show how our implementation can be used in the context of a new resource-aware parallel computing paradigm, called invasive computing. Here, an application can adapt itself at run-time in order to satisfy different quality and throughput requirements.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.accura

Accuracy of Ethernet AVB Time Synchronization Under Varying Temperature Conditions for Automotive Networks - Kern, Andreas; Zinner, Helge; Streichert, Thilo; Nöbauer, Josef; Teich, Jürgen (Proceedings of the 2011 ACM/EDAC/IEEE Design Automation Conference (DAC'11), 2011)
Today's premium vehicles are equipped with a multitude of Advanced Driver Assistance Systems (ADAS) which present additional driving information or even actively influence the vehicle behavior. These are normally highly distributed real-time systems which process information from distributed sensors like cameras or radar sensors. To fulfiill the high data rates and real-time requirements of these and future systems, it is necessary to provide a suitable underlying network architecture which can handle the communication requirements. Ethernet with its high data rates and Audio Video Bridging (AVB) with its mechanisms for time synchronization as well as traffic shaping could be one solution to interconnect such systems. An essential prerequisite for this is an extensive investigation of Ethernet AVB for automotive applications. This paper concentrates on the evaluation of the accuracy, stability, and robustness of the time synchronization mechanism of AVB under varying temperature conditions and presents measurement results obtained from a test setup with climate chambers. © 2011 ACM.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.accura
Keywords: automotive; AVB; Ethernet; jitter; synchronization; temperature conditions

A Clustering-Based MPSoC Design Flow for Data Flow-Oriented Applications - Falk, Joachim (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2015)
This book presents advances for state-of-the-art design flows tackling the challenging problem of system design for embedded systems to program multiple connected and heterogeneous resources by: (1) introducing a modeling language suited to these systems; (2) contributing a methodology called clustering that fits the concurrency of an application to the degree of concurrency provided by the architecture; and (3) discussing the synthesis of the modeled applications via a synthesis back-end that supports multiple targets such as single core software implementations, virtual prototypes of distributed Multi-Processor System-on-Chip (MPSoC) systems, and dedicated hardware implementations. Some embedded systems like automotive controller networks are naturally heterogeneous distributed systems, while heterogeneous distributed architectures have been chosen for other embedded systems in portable devices. This choice is due to the dichotomy between the power requirements induced by the rising hardware capabilities and the comparatively slow improvements in battery technology. Here, the power-efficient implementations of functionality enabled by heterogeneous implementations using power-efficient dedicated accelerators and multicore processors is exploited to resolve this dichotomy. Problems arise when these embedded systems are implemented via traditional sequential programming languages since these languages are not designed to handle concurrency well. Concurrency, however, is inherently present in distributed systems and must be handled efficiently to exploit their advantages. In contrast, the data flow paradigm is well-suited to express concurrency and, hence, is a natural fit for programming heterogeneous distributed systems. Hence, this book is concerned with a design flow starting from applications specified via this paradigm and targeting multiple architectures such as single- and multicore software implementations, virtual prototypes of distributed MPSoC systems, and dedicated hardware implementations. However, to create an efficient implementation of a data flow-oriented application for a given target architecture, the concurrency of the application must be fitted to the concurrency provided by the architecture. To resolve this problem, a novel clustering methodology is presented in this boo
Keywords: Clustering; SysteMoC; Dataflow; Data flow; Quasi-static scheduling; Quasi-static schedule

A co-design approach for accelerated SQL query processing via FPGA-based data filtering - Becher, Andreas; Ziener, Daniel; Meyer-Wegener, Klaus; Teich, Jürgen (International Conference on Field Programmable Technology, FPT 2015, 2015)
In this paper, we present a novel co-designed architecture for high throughput database query processing. It consists of a highly configurable FPGA-based filter chain with arithmetic operation support and an alignment unit. This feeds the filtered data directly and in a cache-optimized way to embedded processors which are responsible for joining tables and post processing. High throughput interfaces and parallelism of FPGA implementations are thus combined in order to provide reduced and cache-Aligned data for optimized processor access. As a key component, we introduce a new highly configurable bloom filter cascade to relieve a processor of time-consuming hash-value computation and to significantly reduce the data for hash joins. It is shown that this unique approach may reduce the amount of data to be processed by the processors in typical data-warehouse applications by several orders of magnitude. The proposed co-design has been implemented on the embedded low-energy system-on-chip (SoC) platform Xilinx Zynq. Performance results for standard benchmarks show an up to 10 x higher throughput compared to a full featured x86-based processor at only a fraction of energy consumption.

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays - Lari, Vahid; Tanase, Alexandru-Petru; Teich, Jürgen; Witterauf, Michael; Khosravi, Faramarz; Hannig, Frank; Meyer, Brett (Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015)
We present a co-design approach to establish redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) to a whole region of a processor array for a class of Coarse-Grained Reconfigurable Arrays (CGRAs). The approach is applied to applications with mixed-criticality properties and experiencing varying Soft Error Rates (SERs) due to environmental reasons, e. g., changing altitude. The core idea is to adapt the degree of fault protection for loop programs executing in parallel on a CGRA to the level of reliability required as well as SER profiles. This is realized through claiming neighbor regions of processing elements for the execution of replicated loop nests. First, at the source code level, a compiler transformation is proposed that realizes these replication schemes in two steps: (1) replicate given parallel loop program two or three times for DMR or TMR, respectively, and (2) add appropriate error handling functions (voting or comparison) in order to detect respectively correct any single errors. Then, using the opportunities of hardware/software co-design, we propose optimized implementations of the error handling functions in software as well as in hardware. Finally, experimental results are given for the analysis of reliability gains for each proposed scheme of array replication in dependence of different SER
Keywords: Hardware; Parallel processing; Redundancy; Registers; Schedules; Software; Tunneling magnetoresistance

A Combined Mapping and Routing Algorithm for 3D NoCs Based on ASP - Andres, Benjamin; Schaub, Torsten; Gebser, Martin; Haubelt, Christian; Reimann, Felix; Glaß, Michael (Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013)

A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on Spartan-3 FPGAs - Koch, Dirk; Beckhoff, Christian; Teich, Jürgen (Proc. 17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.acommu

A communication architecture for complex runtime systems and its implementation on spartan-3 FPGAs - Teich, Jürgen; Beckhoff, Christian; Koch, Dirk (Proceedings of the 17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2009), 2009)
In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by FPGA reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-cost Spartan-3 devices. It will be demonstrated that modules can be exchanged in a system without disturbing the communication architecture. The paper points out, that the capabilities of Spartan-3 FPGAs are sufficient to build complex reconfigurable systems. Copyright 2009 ACM.
Keywords: Design; Experimentation

A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems - Esper, Khalil; Wildermann, Stefan; Teich, Jürgen (Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES), OASICS Vol. 87, 2021)
Many applications vary a lot in execution time depending on their workload. A prominent example is image processing applications, where the execution time is dependent on the content or the size of the processed input images. An interesting case is when these applications have quality-of-service requirements such as soft deadlines, that they should meet as good as possible. A further complicated case is when such applications have one or even multiple further objectives to optimize like, e.g., energy consumption. Approaches that dynamically adapt the processing resources to application needs under multiple optimization goals and constraints can be characterized into the application-specific and feedback-based techniques. Whereas application-specific approaches typically statically use an offline stage to determine the best configuration for each known workload, feedback-based approaches, using, e.g., control theory, adapt the system without the need of knowing the effect of workload on these goals. In this paper, we evaluate a state-of-the-art approach of each of the two categories and compare them for image processing applications in terms of energy consumption and number of deadline misses on a given many-core architecture. In addition, we propose a second feedback-based approach that is based on finite state machines (FSMs). The obtained results suggest that whereas the state-of-the-art application-specific approach is able to meet a specified latency deadline whenever possible while consuming the least amount of energy, it requires a perfect characterization of the workload on a given many-core system. If such knowledge is not available, the feedback-based approaches have their strengths in achieving comparable energy savings, but missing deadlines more ofte
Keywords: Soft real-time; Energy optimization; Control-theory; Timing analysis; Dynamic voltage and frequency scaling; Finite state machines; Multi-core; Many-core

A comparison of embedded reconfigurable video-processing architectures - Angermeier, Josef; Claus, Christopher; Stechele, Walter; Teich, Jürgen (Proceedings of International Conference on Field-Programmable Logic and Applications, 2008)
Using Field Programmable Gate Arrays (FPGAs) as accelerators for image or video processing operations and algorithms has gained increasing attention over the last few years. One reason for that is FPGAs are able to exploit both temporal and spatial parallelism. In this paper two platforms for FPGA-based real-time image and video processing are presented and compared against each other. With both of these platforms it is possible to update the physical resources during run-time by exploiting the dynamic partial reconfiguration capabilities of Xilinx Virtex FPGAs. The analysis of both platforms with respect to their benefits and drawbacks has led to the concept of an optimal FPGA-based dynamically and partially reconfigurable platform for real-time video and image processing. ©2008 IEEE.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.acompa

A Compiler for Application-Specific Processor Arrays (Zugl. Doktorarbeit) - Teich, Jürgen (Friedrich-Alexander-Universität Erlangen-Nürnberg, 1993)
UnivIS-Import:2015-04-02:Pub.1993.tech.IMMD.inform.acompi_0

A Compiler for Symbolic Code Generation for Tightly Coupled Processor Arrays - Witterauf, Michael (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2021)
Keywords: TCPA; Compiler; Polyhedral Model; Loops; Loop Acceleration

AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Teich, Jürgen (Proceedings of 2018 International Conference on Field Programmable Technology, 2018)
New relaxed quality standards laid down by approximate computing enrich the design pool with architectures dissipating less power, consuming fewer resources or with smaller latencies. In LUTbased FPGA logic approximation, the number of LUTs and latency associated to a design can be optimized by allowing the approximation of circuit results. In this paper, we present techniques for automatic design space exploration (DSE) of Boolean function falsifications and the ability and impact to reduce resources usage as well as the length of critical paths on LUT-based FPGAs. Our experiments give evidence that resource reductions of about 20% are easily achievable for error rates amounting to less than 0.05% w.r.t. accurate design
Keywords: Approximate Computing; Logic Simplification; Design Space Exploration; FPGAs.

A Co-Simulation Approach for Control Performance Analysis during Design Space Exploration of Cyber-Physical Systems - Mühleis, Nina; Glaß, Michael; Zhang, Liyuan; Teich, Jürgen (ACM SIGBED Review - Work-in-Progress (WiP) Session of the 2nd International Conference on Cyber Physical Systems (ICCPS 2011), 2011)
UnivIS-Import:2015-04-14:Pub.2011.tech.IMMD.inform.acosim

A Co-simulation Approach for System-Level Analysis of Embedded Control Systems - Glaß, Michael; Teich, Jürgen; Zhang, Liyuan (Proc. of the 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2012)
Control applications have become an integral part of modern networked embedded systems. However, there often exists a gap between control engineering and system design. The control engineer has detailed knowledge about the algorithms but is abstracting from the system architecture and implementation. On the other hand, the system designer aims at achieving high-quality implementations based on quality constraints specified by the control engineer. This may result in either an overdesigned system in case the specifications are pessimistic or an unsafe system behavior when specifications are too optimistic. Thus, future design automation approaches have to consider the quality of control applications both as design objectives and design constraints to achieve safe yet highly optimized system implementations. The work at hand introduces an automatic tool flow at the Electronic System Level (ESL) that enables the optimization of a system implementation with quality of control being introduced as a principal design objective, like the maximum braking distance, while respecting constraints like maximum slip to ensure maneuverability of a car. The gap between mathematically well-defined models for system synthesis and common analysis techniques for control quality is bridged by co-simulation: A SystemC-based virtual prototype of a distributed controller implementation is combined with high-level models of the plants specified in Matlab/Simulink. Through a model transformation, the traditional development process of control applications is combined with state-of-the-art ESL techniques, ensuring model consistency while enabling a high degree of automation. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.acosim

Actor-oriented Modeling and Simulation of Cut-through Communication in Network Controllers - Zhang, Liyuan; Glaß, Michael; Streubühr, Martin; Teich, Jürgen; von Schwerin, Andreas; Liu, Kai (Tagungsunterlagen Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012)
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.actoro

Actor-oriented modeling and simulation of sliding window image processing algorithms - Keinert, Joachim; Falk, Joachim; Haubelt, Christian; Teich, Jürgen (Proceedings of the 2007 IEEE/ACM/IFIP Workshop of Embedded Systems for Real-Time Multimedia (ESTIMEDIA 2007), 2007)
Embedded real-time image processing systems have to process huge amounts of data with limited resources and energy. Hence high efficiency is not only required for manual, but also for automatic system generation. Therefore, in order to allow for different optimizations, a system specification must be such that important algorithm properties are accessible to the system design software. In this paper, we present a new method how multi-dimensional image processing algorithms can be modeled by actor-oriented data flow semantics. Using the example of a binary morphological reconstruction, we investigate the modeling requirements posed by point, local and global image processing algorithms. We show how they can be taken into account in our approach, so that efficient implementation and analysis in terms of buffer size and throughput is possible. In particular, by the explicit specification of the communication behavior, both static and data dependent algorithms are supported allowing for a complete system specification. © 2007 IEEE.

Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation - Kiesel, Rainer; Löhlein, Otto; Terzis, Anestis; Streubühr, Martin; Haubelt, Christian; Teich, Jürgen (Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2010)

Actor-oriented Modeling of Industrial Ethernet in the Automation Domain Using SystemC - Kutzer, Philip; Streubühr, Martin; Haubelt, Christian; Teich, Jürgen; von Schwerin, Andreas (Proceedings of the Embedded World Conference, 2011)

ActorX10: An Actor Library for X10 - Roloff, Sascha; Pöppl, Alexander; Schwarzer, Tobias; Wildermann, Stefan; Baader, Michael; Glaß, Michael; Hannig, Frank; Teich, Jürgen (Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10), 2016)

ActorX10 and Run-Time Application Embedding - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Modeling and Simulation of Invasive Applications and Architectures, 2019)
CRIS-Team WoS Importer:2019-11-08

Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing - Witterauf, Michael; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), 2015)

Adaptive fault tolerance through invasive computing - Witterauf, Michael; Tanase, Alexandru-Petru; Teich, Jürgen; Lari, Vahid; Zwinkau, Andreas; Snelting, Gregor (Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015)
Fault tolerance is a basic necessity to make today's complex systems reliable. Adequate fault tolerance, however, demands a high degree of redundancy, possibly wasting resources when the fault probability is low or when some applications do not require fault tolerance. Under the term adaptive fault tolerance, we investigate means to instead provide on-demand fault tolerance on multi-core systems dynamically and according to application and environmental needs. Such means are provided on a per-application basis by invasive computing, a recent paradigm for resource-aware programming and design of parallel systems: applications request resources in an invade phase, infect the acquired resources with code and data, and finally release them in a retreat phase. We show how to use these simple but powerful constructs to adaptively tolerate faults and that invasive computing harmonizes well with many existing fault tolerance approaches. Finally, a case study on adaptively providing fault tolerance for loops demonstrates how effective invasive computing is for adapting to a varying soft error rate and handling of faults.
Keywords: Adaptation models; Fault tolerant systems; Hardware; Redundancy; Runtime

Adaptive Isolation for Predictability and Security - Mitra, Tulika; Teich, Jürgen; Thiele, Lothar (2016)

Adaptive Isolation for Predictable MPSoC Stream Processing - Teich, Jürgen (Proc. of the 18th Int. Workshop on Software and Compilers for Embedded Systems (SCOPES 2015), 2015)

Adaptive Predictive Power Management for Mobile LTE Devices - Brand, Peter; Falk, Joachim; Ah Sue, Jonathan; Brendel, Johannes; Hasholzner, Ralph; Teich, Jürgen (IEEE Transactions on Mobile Computing, 2021)

Adaptive Traffic Scheduling Techniques for Mixed Real-Time and Streaming Applications on Reconfigurable Hardware - Ziermann, Tobias; Teich, Jürgen (Proc. 17th Reconfigurable Architectures Workshop, 2010)
With the ongoing development of new FPGA generations, the reconfiguration time decreases and therefore the benefit of runtime reconfiguration increases. In this paper, we describe how to use runtime reconfiguration to improve the efficiency of transmitting streaming data on a communication channel shared with real-time applications. This means, the bandwidth that the streaming data has available is dynamically changing. To use the bandwidth effectively, different modules can be loaded on the reconfigurable hardware. These modules have a tradeoff between bandwidth and area requirements. The target now is to find an optimal reconfiguration schedule that minimizes an objective function consisting of two conflicting objectives: reducing the average area needed and providing a certain quality of transmission. In this paper, a model for this scheduling problem is presented and an Integer Linear Programming (ILP) formulation is introduced to calculate an optimal offline solution for benchmarking. In addition, an online scheduling system is presented. It uses the current delay of the streaming application to calculate the schedule. Extensive simulations have been made to show the benefits of the proposed solution.© 2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.adapti

A Decomposition of the Max-min Fair Curriculum-based Course Timetabling Problem: The Impact of Solving Subproblems to Optimality - Mühlenthaler, Moritz; Wanka, Rolf (Proc. 6th Multidisciplinary International Scheduling Conference: Theory and Applications, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.infalg._adeco

A Deeply Pipelined and Parallel Architecture for Denoising Medical Images - Hannig, Frank; Schmid, Moritz; Teich, Jürgen; Hornegger, Heinz (Proc. IEEE International Conference on Field Programmable Technology, 2010)
In this paper we present an almost automatic synthesis of a highly complex, throughput optimized architecture of an adaptive multiresolution filter as used in medical image processing for FPGAs. The filter consists of 16 parallel working modules, where the most computationally intensive module achieves software pipelining of a factor of 85, that is, computations of 85 iterations overlap each other. By applying a state-of-the-art high-level synthesis tool, we show that this approach can be used for real world applications. In addition, we show that our high-level synthesis tool is capable of significantly reducing the well known productivity gap of embedded system design by almost two orders of magnitude. Finally, we can conclude that the FPGA implementation of the multiresolution image processing algorithm is far ahead of a comparable implementation for graphics cards in terms of power efficiency. © 2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.adeepl

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing - Dutta, Hritam; Hannig, Frank; Heigl, Benno; Hornegger, Heinz; Teich, Jürgen (Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors, 2006)
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper, we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. The final architecture deliver similar synthesis results as a hand-tuned design. © 2006 IEEE.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.adesig

A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs - Weichslgartner, Andreas; Wildermann, Stefan; Gangadharan, Deepak; Glaß, Michael; Teich, Jürgen (ACM Transactions on Embedded Computing Systems, 2018)

A Domain-Specific Language and Source-to-Source Compilation Framework for Geometric Multigrid Methods - Schmitt, Christian (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2019)

A Domain-Specific Language Approach for Designing and Programming Heterogeneous Image Systems - Reiche, Oliver (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2018)
Keywords: Domain-specific Languages; Code Generation; Image Processing

Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures - Reimann, Felix; Glaß, Michael; Teich, Jürgen; Cook, Alejandro; Gomez, Laura Rodriguez; Ull, Dominik; Wunderlich, Hans-Joachim; Engelke, Piet; Abelein, Ulrich (Proc. of The 51st Annual Design Automation Conference (DAC), 2014)
The constantly growing amount of semiconductors in au-tomotive systems increases the number of possible defect mechanisms, and therefore raises also the effort to main-tain a sufficient level of quality and reliability. A promising solution to this problem is the on-line application of struc-tural tests in key components, typically ECUs. In this work, an approach for the optimized integration of both Software-Based Self-Tests (SBST) and Built-In Self-Tests (BIST) into E/E architectures is presented. The approach integrates the execution of the tests non-intrusively, i. e., it (a) does not af-fect functional applications and (b) does not require costly changes in the communication schedules or additional com-munication overhead. Via design space exploration, opti-mized implementations with respect to multiple con icting objectives, i. e., monetary costs, safety, test quality, and re-quired execution time are derived. Copyright 2014 ACM.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.advanc

A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template - Kissler, Dmitrij; Hannig, Frank; Kupriyanov, Olexiy; Teich, Jürgen (Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC), 2006)

A Dynamic NoC Approach for Communication in Reconfigurable Devices - Ahmadinia, Ali; Bobda, Christophe; Koch, Dirk; Majer, Mateusz; Teich, Jürgen (Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), 2004)
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.adynam_15

A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware - Ahmadinia, Ali; Bobda, Christophe; Teich, Jürgen (Proceedings of 17th International Conference on Architecture of Computing Systems, Lecture Notes in Computer Science, 2004)
Recent generations of FPGAs allow run-time partial reconfiguration. To increase the efficacy of reconfigurable computing, multitasking on FPGAs is proposed. One of the challenging problems in multitasking systems is online template placement. In this paper, we describe how existing algorithms work, and propose a new free space manager which is one main part of the placement algorithm. The decision where to place a new module depends on its finishing time mobility. Therefore the proposed algorithm is a combination of scheduling and placement. The simulation results show a better performance against existing methods. © Springer-Verlag 2004.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.adynam

A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays - Aliee, Hananeh; Zarandi, Hamid Reza (IEEE Transactions on Reliability, 2012)
UnivIS-Import:2015-03-09:Pub.2012.tech.IMMD.inform.afasta

A fast BDD Minimization Framework for Approximate Computing - Wendler, Andreas; Keszöcze, Oliver (Design, Automation and Test in Europe, 2020)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. Computing the error of the approximated design is an essential step to determine its quality. The computation time for determining the error can become very large, effectively rendering the entire logic approximation procedure infeasible. As a remedy, we present methods to accelerate the computation of error metric computations by (a) exploiting structural information and (b) computing estimates of the metrics for multi-output Boolean functions represented as BDDs. We further present a novel greedy, bucket-based BDD minimization framework employing the newly proposed error metric computations to produce Pareto-optimal solutions with respect to BDD size and multiple error metrics. The applicability of the proposed minimization framework is demonstrated by an experimental evaluation. We can report considerable speedups while, at the same time, creating high-quality approximated BDDs.
Keywords: Approximate Computing; Design Space Exploration; Multi-Objective Optimization; BDD Minimization; Logic Minimization

A fault-tolerant, dynamically scheduled pipeline structure for chip multiprocessors - Aliee, Hananeh; Zarandi, Hamid Reza (Proceedings of the 30th International Conference on Computer Safety, Reliability and Security (SAFECOMP'11), 2011)
This paper presents a dynamically scheduled pipeline structure for chip multiprocessors (CMPs). This technique exploits existing Simultaneous Multithreading (SMT), superscalar chip multiprocessors' redundancy to provide low-overhead, and broad coverage of faults at the cost of performance degradation for processors. This pipeline structure operates in two modes: 1) high-performance and 2) highly-reliable. In high-performance mode, each core works as a real SMT, superscalar processor. Whereas, the main contribution of the highly-reliable mode is: 1) To enhance the reliability of the system without adding extra redundancy strictly for fault tolerance, 2) To detect both transient and permanent faults, and 3) To recover existing faults. The experimental results show that the diagnosis mechanism quickly and accurately diagnoses faults. The fault detection latency for this technique is equal to the pipeline length of the processor, while it provides high fault detection coverage. Moreover, the reliable processor can function quite capably in the presence of both transient and permanent faults, despite of not using redundancy beyond which is already available in a modern microprocessor. Also, in the highly-reliable mode, the static and dynamic power consumption is declined by 25% and 36%, respectively. © 2011 Springer-Verlag.
Keywords: Chip multiprocessor; Fault tolerance; Permanent fault; Pipeline structure; Reliability; Superscalar processor; Transient fault

A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems - Glaß, Michael; Lukasiewycz, Martin; Teich, Jürgen (Proceedings of the 10th International Conference on Parallel Problem Solving from Nature, 2008)
This paper presents a feasibility-preserving crossover and mutation operator for evolutionary algorithms for constrained combinatorial problems. This novel operator is driven by an adapted Pseudo-Boolean solver that guarantees feasible offspring solutions. Hence, this allows the evolutionary algorithm to focus on the optimization of the objectives instead of searching for feasible solutions. Based on a proposed scalable testsuite, six specific testcases are introduced that allow a sound comparison of the feasibility-preserving operator to known methods. The experimental results show that the introduced approach is superior to common methods and competitive to a recent state-of-the-art decoding technique. © 2008 Springer-Verlag Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.afeasi_8

A feasibility-preserving local search operator for constrained discrete optimization problems - Lukasiewycz, Martin; Glaß, Michael; Haubelt, Christian; Teich, Jürgen (Proceedings of the 2008 IEEE Congress on Evolutionary Computation (CEC 2008), 2008)
Meta-heuristic optimization approaches are commonly applied to many discrete optimization problems. Many of these optimization approaches are based on a local search operator like, e.g., the mutate or neighbor operator that are used in Evolution Strategies or Simulated Annealing, respectively. However, the straightforward implementations of these operators tend to deliver infeasible solutions in constrained optimization problems leading to a poor convergence. In this paper, a novel scheme for a local search operator for discrete constrained optimization problems is presented. By using a sophisticated methodology incorporating a backtracking-based ILP solver, the local search operator preserves the feasibility also on hard constrained problems. In detail, an implementation of the local serach operator as a feasibility-preserving mutate and neighbor operator is presented. To validate the usability of this approach, scalable discrete constrained testcases are introduced that allow to calculate the expected number of feasible solutions. Thus, the hardness of the testcases can be quantified. Hence, a sound comparison of different optimization methodologies is presented. © 2008 IEEE.

A Fine-Grained Configurable Cache Architecture for Soft Processors - Biglari, Mehrdad; Barijough, Kamyar Mirzazad; Goudarzi, Maziar; Pourmohseni, Behnaz (Proceedings of the 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS), 2015)
The ever increasing density and performance of FPGAs, has increased the importance and popularity of soft processors. The growing gap between the speed of processors and memories can partly be compensated through memory hierarchy. Since memory accesses follow a non-uniform distribution, and vary from one application to another, variable set-associative cache architectures have emerged. In this paper, a novel cache architecture, primarily aimed at soft processors, is proposed to address the variable access demands of applications, through dynamically configurable line-associativity, with no memory overhead. The FPGA implementation of the proposed architecture achieves an average miss count reduction of 70% compared to the direct-mapped cache which translates in 17% improvement in IPC, on 11 benchmarks.
Keywords: Configurable Cache; Performance; Soft Processors; Energy-Efficiency; FPGA

A Flexible FPGA-based Inference Architecture for Pruned Deep Neural Networks - Posewsky, Thorbjörn; Ziener, Daniel (Proceedings of the International Conference on Architecture of Computing Systems, 2018)
In this paper, we present an architecture for embedded FPGA-based deep neural network inference which is able to handle pruned weight matrices. Pruning of weights and neurons reduces significantly the amount of stored data and calculations which improves enormously the efficiency and performance of inference of neural networks in embedded devices. By using an HLS approach, the architecture is easily extendable and the number of used MAC units and activation functions is configurable at design time. For large neural networks, our approach has at least comparable performance as state-of-the-art x86-based software implementation by using only 10% of the energy.
Keywords: RC

A Flexible Reconfiguration Manager for the Erlangen Slot Machine - Majer, Mateusz; Ahmadinia, Ali; Bobda, Christophe; Teich, Jürgen (Proceedings of the Dynamically Reconfigurable Systems Workshop (DRS'2006), 2006)

A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC - Ziener, Daniel; Wildermann, Stefan; Oetken, Andreas; Weichslgartner, Andreas; Teich, Jürgen (Proceedings of the Workshop on Computer Vision on Low-Power Reconfigurable Architectures at FPL 2011, 2011)

A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (2006)

A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems - Bobda, Christophe; et al. (Proceedings of Design, Automation and Test in Europe, 2003)
The presented architecture has the peculiar feature of being self-timed and comprising a fully interlocked pipelining structure which aims at controlling the different computational paths of a system design. One example is the automotive industry where performance, space, cost, size, and weight are of vital importance, the main features of this architecture. © 2003 IEEE.
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.afully

A Generalized Static Data Flow Clustering Algorithm for MPSoC Scheduling of Multimedia Applications - Falk, Joachim; Keinert, Joachim; Haubelt, Christian; Teich, Jürgen; Bhattacharyya, Shuvra S. (Proc. of the 8th ACM & IEEE international conference on Embedded software (EMSOFT'2008), 2008)

A Generic Framework for Rapid Prototyping of System-on-Chip Designs - Kissler, Dmitrij; Kupriyanov, Olexiy; Hannig, Frank; Koch, Dirk; Teich, Jürgen (Proceedings of the International Conference on Computer Design (CDES), 2006)

A heterogeneous multi-core SoC for mixed criticality industrial automation systems - Salcic, Zoran; Nadeem, Muhammad; Park, Heejong; Teich, Jürgen (Proceedings Emerging Technologies and Factory Automation (ETFA), 2016 IEEE 21st International Conference, 2016)

A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis - Özkan, Mehmet Akif; Reiche, Oliver; Hannig, Frank; Teich, Jürgen (Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP), 2017)

A highly parameterizable parallel processor array architecture - Kissler, Dmitrij; Kupriyanov, Olexiy; Hannig, Frank; Teich, Jürgen (Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006), 2006)
In this paper a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is discussed. The main advantages of the proposed architecture template are the possibility of partial and differential reconfiguration and the systematical classification of different architectural parameters which allow to trade-off flexibility and hardware cost. The applicability of our approach is tested in a case study with different interconnect topologies on an FFGA platform. The results show substantial flexibility gains with only marginal additional hardware cost. © 2006 IEEE.

A High-Performance Image Processing DSL for Heterogeneous Architectures - Selgrad, Kai; Lier, Alexander; Dörntlein, Jan; Reiche, Oliver; Stamminger, Marc (Proceedings of ELS 9th European Lisp Symposium, 2016)
Over the last decade a number of high performance, domain-specific languages (DSLs) have started to grow and help tackle the problem of ever diversifying hard- and software employed in fields such as HPC (high performance computing), medical imaging, computer vision etc. Most of those approaches rely on frameworks such as LLVM for efficient code generation and, to reach a broader audience, take input in C-like form. In this paper we present a DSL for image processing that is on-par with competing methods, yet its design principles are in strong contrast to previous approaches. Our tool chain is much simpler, easing the burden on implementors and maintainers, while our output, C-family code, is both adaptable and shows high performance. We believe that our methodology provides a faster evaluation of language features and abstractions in the domains above.
Keywords: GRK-1773

A High Performance VLIW Processor for Finite Field Arithmetic - Bednara, Marcus; Grabbe, Cornelia; J. Shokrollahi, J.; Teich, Jürgen; von zur Gathen, J. (Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS-2003), 2003)
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.ahighp

A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors - Dutta, Hritam; Kissler, Dmitrij; Hannig, Frank; Kupriyanov, Olexiy; Teich, Jürgen; Pottier, Bernard (Microprocessors and Microsystems, 2009)
New standards in signal, multimedia, and network processing for embedded electronics are characterized by computationally intensive algorithms, high flexibility due to the swift change in specifications. In order to meet demanding challenges of increasing computational requirements and stringent constraints on area and power consumption in fields of embedded engineering, there is a gradual trend towards coarse-grained parallel embedded processors. Furthermore, such processors are enabled with dynamic reconfiguration features for supporting time- and space-multiplexed execution of the algorithms. However, the formidable problem in efficient mapping of applications (mostly loop algorithms) onto such architectures has been a hindrance in their mass acceptance. In this paper we present (a) a highly parameterizable, tightly coupled, and reconfigurable parallel processor architecture together with the corresponding power breakdown and reconfiguration time analysis of a case study application, (b) a retargetable methodology for mapping of loop algorithms, (c) a co-design framework for modeling, simulation, and programming of such architectures, and (d) loosely coupled communication with host processor. © 2008 Elsevier B.V. All rights reserved.
UnivIS-Import:2015-04-14:Pub.2009.tech.IMMD.inform.aholis
Keywords: Architecture/compiler co-design; Coarse-grained embedded parallel processors; Communication; Mapping of loop programs; Reconfiguration

AIS-Autonomous Integrated Systems - Schöber, Volker; Bringmann, Oliver; Herkersdorf, Andreas; Stechele, Walter; Wehn, Norbert; May, Matthias; Ziener, Daniel; Bouajila, Abdelmajid; Baldin, Daniel; Zeppenfeld, Johannes; Sanders, Björn; Teich, Jürgen; et al. (newsletter edacentrum, 2009)
UnivIS-Import:2015-03-09:Pub.2009.tech.IMMD.inform.aisaut

A Joined Architecture/Compiler Environment for ASIPs - Fischer, Dirk; Teich, Jürgen; Trinkert, Stefan; Weper, Ralph (ACM SIG Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems, 2000)
In this paper, we introduce a methodology for rapid prototyping of application-specific instruction set processors (ASIPs) including the automatic generation of bit-true and cycle-accurate instruction-set simulators and corresponding compiler (re)targets. The methodology is based on ASMs (abstract state machines) as the underlying formal model for describing a processor's behavior. We explain the major advantages of using ASMs and outline the main tool flow from graphical entry of a processor's major RTL building blocks and simulator generation as well as the current status of our project.
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.ajoine

A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement - Özkan, Mehmet Akif; Pérard-Gayot, Arsène; Membarth, Richard; Slusallek, Philipp; Teich, Jürgen; Hannig, Frank (Proceedings of the Fifth International Workshop on FPGAs for Software Programmers, 2018)
Field Programmable Gate Arrays (FPGAs) are continually improving their computing capabilities and energy efficiency. Yet, programming FPGAs remains a time-consuming task and requires expert knowledge to obtain good performance. Whereas recent advancements in High-Level Synthesis (HLS) promise to solve this problem, today’s HLS tools need low-level optimizations such that an application-tailored FPGA implementation for a target algorithm needs to be described using vendor-specific compiler hints and requires code restructuring. Despite the pursuit of new programming methodologies for many-core, multi-threading, or vector architectures, the FPGA community mostly tries to improve the design techniques from existing programming languages that are either sequential or developed for other computing platforms. In this paper, we investigate a state-of-the-art functional language, namely Impala, that offers explicit control over code refinement. To demonstrate our approach, we examine the description of image border handling for stencil functions and present elegant code descriptions. Besides, we show that the low-level descriptions can easily be refined to high-level abstractions and serving software developers in the form of either a DSL or a library.
Keywords: DSL; HLS; AnyDSL; FPGA; Border Handling; Intel OpenCL

A Learning-Based Methodology for Scenario-Aware Mapping of Soft Real-Time Applications onto Heterogeneous MPSoCs - Spieck, Jan; Wildermann, Stefan; Teich, Jürgen (ACM Transactions on Design Automation of Electronic Systems, 2023)

ALPACA: An Accelerator Chip for Nested Loop Programs - Walter, Dominik; Brand, Marcel; Heidorn, Christian; Witterauf, Michael; Hannig, Frank; Teich, Jürgen (Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2024)

A LUT-Based Approximate Adder - Becher, Andreas; Echavarria Gutiérrez, Jorge Alfonso; Ziener, Daniel; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, 2016)

A Methodology for the Optimized Design of an E/E Architecture Component Platform - Graf, Sebastian; Glaß, Michael; Teich, Jürgen; Platte, Daniel (Proceedings of the Stuttgart International Symposium, 2015)

A model-based inter-process resource sharing approach for high-level synthesis of dataflow graphs - Zebelein, Christian; Falk, Joachim; Haubelt, Christian; Teich, Jürgen (2nd Electronic System Level Synthesis Conference, ESLsyn 2012, 2012)
High-level synthesis tools are gaining more and more acceptance in industrial design flows. While they increase productivity in implementing a single complex hardware module, synthesizing and optimizing many hardware components simultaneously is still an open problem. In particular, resource sharing is typically only performed for single components, thereby neglecting optimization possibilities across concurrent modules. On the other hand, domain-specific models and specifications, which are generally seen as a key ingredient to raise the level of abstraction in future design flows, may enable such global optimizations. In this paper, we present a model-based approach for inter-process resource sharing which provides for efficient high-level synthesis of streaming applications modeled as a set of communicating processes. The applicability of the proposed approach is validated by a case study. © 2012 ECSI.

A Model for Buffer Exploration in EDF Scheduled Embedded Systems - Teich, Jürgen; Slomka, Frank (VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik (GMM), GMM-Fachbericht, 2003)
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.amodel

Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-based Modeling - Rosales, Rafael; Herglotz, Christian; Glaß, Michael; Teich, Jürgen; Kaup, André (In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 2016)
The new High-Efficiency Video Coding (HEVC) standard achieves much better compression ratios than previous ones by offering multiple coding modes, albeit with a significant increase over the required computational power especially at the encoder side. As the first major contribution, we propose a fine-grained parallelization of the encoding mode decision process using a SystemC actor-based model, exploiting multi-core platforms. Second, based on this model, we analyze achievable speedups compared to the single core sequential implementation of the HM-16.0 reference software. Using four different video sequences, we find that our approach achieves an equivalent rate-distortion performance for different quantization parameter values with a simulated encoding time improvement factor of up to \(9× \) for a maximally parallelized mode decision process. Third, an HEVC encoder has a huge number of different standard-complying encoding modes to choose from for each encoded frame, making the exploration space almost impossible to be fully covered by a brute-force search. Here, we systematically investigate the trade-off in encoding time versus required number of processor cores by proposing a multi-objective Design Space Exploration (DSE) of the mapping of the parallelized mode decision tasks to processing resources, taking as optimization objectives the resulting bitrate, image quality, number of processor cores used, execution time, and total energy consumptio
UnivIS-Import:2016-06-01:Pub.2016.tech.IE.LEN.analys
Keywords: Video encoding · HEVC · ESL · DSE · Parallelization · Actor-based modeling · Hardware/software co-design

Analysis of Dataflow Programs with Interval-limited Data-rates - Bhattacharyya, Shuvra S.; Teich, Jürgen (Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2006)
In this paper, we consider the problem of analyzing dataflow programs with the property that actor production and consumption rates are not constant and fixed, but limited by intervals. Such interval ranges may result from uncertainty in the specification of an actor or as a design freedom of the model. Major questions such as consistencyand buffer memory requirementsfor single-processor scheduleswill be analyzed here for such specifications for the first time. Also, metamodeling formulations of interval limited dataflow are discussed, with special emphasis on the application to cyclo-static dataflow modeling. © 2006 Springer Science + Business Media, LLC.
UnivIS-Import:2015-03-09:Pub.2006.tech.IMMD.inform.analys
Keywords: Buffer memory analysis; Interval rates; Scheduling dataflow models of computation

Analysis of Dataflow Programs with Interval-Limited Data-Rates - Teich, Jürgen; Bhattacharyya, Shuvra S. (Computer Systems: Architectures, Modeling, and Simulation, 2004)
In this paper, we consider the problem of analyzing data flow programs with the property that actor production and consumption rates are not constant and fixed, but limited by intervals. Such interval ranges may result from uncertainty in the specification of an actor or as a design freedom of the model. Major questions such as consistency and buffer memory requirements for single-processor schedules will be analyzed here for such specifications for the first time. © Springer-Verlag Berlin Heidelberg 2004.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.analys

Analysis of systemc actor networks for efficient synthesis - Falk, Joachim; Zebelein, Christian; Keinert, Joachim; Haubelt, Christian; Teich, Jürgen; Bhattacharyya, Shuvra S. (ACM Transactions on Embedded Computing Systems, 2010)
Applications in the signal processing domain are often modeled by dataflow graphs. Due to heterogeneous complexity requirements, these graphs contain both dynamic and static dataflow actors. In previous work, we presented a generalized clustering approach for these heterogeneous dataflow graphs in the presence of unbounded buffers. This clustering approach allows the application of static scheduling methodologies for static parts of an application during embedded software generation for multiprocessor systems. It systematically exploits the predictability and efficiency of the static dataflow model to obtain latency and throughput improvements. In this article, we present a generalization of this clustering technique to dataflow graphs with bounded buffers, therefore enabling synthesis for embedded systems without dynamic memory allocation. Furthermore, a case study is given to demonstrate the performance benefits of the approach. © 2010 ACM.
Keywords: Actor-oriented design; Clustering; Data flow analysis; Scheduling

Analyzing Automotive Networks using Virtual Prototypes - Graf, Sebastian; Streubühr, Martin; Glaß, Michael; Teich, Jürgen (Proceedings of the Automotive meets Electronics (AmE2011), GMM Fachbericht 69, 2011)
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.analyz

An Approximate Sequential Multiplier with Segmented Carry Chain and Variable Accuracy - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Khosravi, Faramarz; Teich, Jürgen (AxC20: 5th Workshop on Approximate Computing, 2020)
Keywords: Approximate Sequential Multiplier

An Architecture Description Language for Massively Parallel Processor Architectures - Kupriyanov, Olexiy; Hannig, Frank; Kissler, Dmitrij; Teich, Jürgen; Schaffer, Rainer; Merker, Renate (Proceedings of the 9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2006)

An Automated Data Structure Migration Concept - From CAN to Ethernet/IP in Automotive Embedded Systems (CANoverIP) - Kern, Andreas; Streichert, Thilo; Teich, Jürgen (Proc. of DATE, 2011)
In premium vehicles, the number of distributed comfort-, safety-, and infotainment-related functions is steadily increasing. For this reason, the requirements for the underlying communication architecture are also becoming stronger. In addition, the diversity of todays deployed communication technologies and the need for higher bandwidths complicate the design of future network architectures. Ethernet and IP, both standardized and widely used, could be one solution to homogenize communication architectures and to provide higher bandwidths. This paper focuses on a migration concept for replacing todays employed CAN-buses by Ethernet/IP-based networks. It highlights several concepts to minimize the protocol header overhead by using EA- and rule-based algorithms and presents migration results for currently deployed automotive CAN subnetworks. © 2011 EDAA.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.anauto
Keywords: automotive; CAN; CANoverIP; embedded; Ethernet; IP; migration; optimization; UDP; XoverIP

An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques - Schmidt, Bernhard; Ziener, Daniel; Teich, Jürgen (In Proceedings of 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, 2014)

An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning - Qiao, Bo; Teich, Jürgen; Hannig, Frank (Proceedings of the 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2021)
Border handling is a crucial step in many image processing applications. For stencil kernels such as the Gaussian filter where a window of pixels is required to compute an output pixel, the border of the image needs to be handled differently than the body of the image. To prevent out-of-bounds accesses, conditional statements need to be inserted into the pixel address calculation. This introduces significant overhead, especially on hardware accelerators such as GPUs. Existing research efforts mostly focus on image body computations, while neglecting the importance of border handling or treating it as a corner case. In this paper, we propose an efficient border handling approach for GPUs. Our approach is based on iteration space partitioning, which is a technique similar to index-set splitting, a well-known general-purpose compiler optimization. We present a detailed systematic analysis including an analytic model that quantitatively evaluates the benefits as well as the costs of the transformation. In addition, manually implementing the border handling technique is a tedious task and not portable at all. We integrate our approach into an image processing DSL and a source-to-source compiler called Hipacc to relieve the burden and increase programmers’ productivity. We evaluate over five commonly used image process- ing applications on two Nvidia GPUs. Results show our proposed approach achieves a geometric mean speedup of up to 87% over a naive implementation.
Keywords: Border Handling; Image Processing; GPU; DSL

An efficient, dynamically adaptive method to tolerate transient faults in multi-core systems - Aliee, Hananeh; Zarandi, Hamid R. (roceedings of the 13th European Workshop on Dependable Computing (EWDC '11), 2011)
This paper presents an adaptive, CPU-aware, fault detection and recovery approach which dynamically modifies the number of replicas in the system. This technique utilizes available unused resources as redundancy. It is transparent for users and does not require modification to the application. This technique benefits from the fact that although all the future product designs are dedicated to multi-cores, these products suffer from poor parallelism in applications. Therefore, there are underutilized CPU resources in the system which can be employed for fault tolerance aim. This is achieved by monitoring the system status periodically, on runtime which creates a set of redundant processes per application. To prevent performance degradation, redundant processes are dynamically scheduled. This technique is more beneficial when the number of cores increases or the application is IO-based with much underutilized CPU resources. Experimental results on a real quad-core system prove that on average, the applications from standard benchmarks like SPLASH-2, PARSEC, and some other suites, utilize the CPU less than 20% which provides high fault detection and recovery with almost 10% performance overhead. Copyright © 2011 ACM.
Keywords: Fault tolerance; Hard errors; Multi-core processors; Redundancy; Reliability

An efficient technique for computing importance measures in automatic design of dependable embedded systems - Aliee, Hananeh; Glaß, Michael; Khosravi, Faramarz; Teich, Jürgen (Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), 2014)
Importance measure analysis judges the relative importance of components in a system and reveals how each component contributes to the system reliability. In the design of large and complex systems, importance measure analysis can therefore be employed to guide an optimization tool which design decisions to investigate to gain higher reliability. While previous research has mainly concentrated on developing analytical importance measure techniques, the automatic and frequent computing of importance measures as required in the context of design space exploration has got very few, if any attention. This paper presents a highly efficient technique to compute the reliability and structural importance measures of components of a system. The proposed technique considers the reliability of a system implementation and subsequently analyzes the importance measures of its components based on a state-of-the-art Monte Carlo simulation. The technique can therefore estimate the importance measures of all components concurrently, highly improving the performance of the computation compared, e. g., to the well-known Birnbaum approach by the factor of 2n with n being the number of components. Moreover, we show how this algorithm can be extended to support importance measure analysis in the existence of transient faults which is essential since in future systems, transient faults are expected to cause relatively more failures than permanent faults. We integrated the proposed analysis approach in an existing multi-objective local-search algorithm that is part of an automatic system-level design space exploration which seeks for system implementations with highest reliability at lowest possible cost. Experimental results show that the proposed algorithm performs efficiently with negligible imprecision, even for large realworld examples. Copyright 2014 ACM.

An Empirical Analysis on Dimensionality in Cellular Genetic Algorithms - Morales-Reyes, Alicia; Escalante, Hugo Jair; Letras, Martin; Cumplido, René (Annual Conference on Genetic and Evolutionary Computation - GECCO '15, 2015)
Keywords: cellular genetic algorithms; selective pressure; topology's dimension

An Evaluation of Domain-Specific Language Technologies for Code Generation - Schmitt, Christian; Kuckuk, Sebastian; Köstler, Harald; Hannig, Frank; Teich, Jürgen (Proc. of the 14th International Conference on Computational Science and its Applications (ICCSA), 2014)
Software systems are becoming increasingly complex, requiring a deep knowledge to work and program with them. This is especially true for simulation frameworks used by scientists and engineers, but also applies to completely different domains such as mobile or web applications. To ease working with these systems, domain-specific languages (DSLs) are a convenient way to enable domain experts describe settings and problems they want to solve using terms familiar to them. Building upon this specification in the DSL, a compiler transform this to the target software framework, e.,g., runnable program code. To write such a compiler, a solid implementation framework is needed. In this paper, we propose criteria for the evaluation of textual programming language implementation frameworks to which we accordingly evaluate four technologies, namely Spoofax/IMP, Rascal MPL, a custom approach using C++ and a custom approach using Scal
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.aneval

An Evolutionary Approach to System-Level Synthesis - Blickle, Tobias; Teich, Jürgen; Thiele, Lothar (Proc. of Codes/CASHE'97, the 5th Int. Workshop on Hardware/Software Co-design, Braunschweig, Germany, pp. 167-171, March 1997, 1997)

An evolutionary approach to system-level synthesis - Teich, Jürgen; Blickle, Tobias; Thiele, Lothar (Proc. of WSC1, the 1st Online Workshop on Soft Computing, 1996)
UnivIS-Import:2015-04-16:Pub.1996.tech.IMMD.inform.anevol

A New Approach for On-line Placement on Reconfigurable Devices - Ahmadinia, Ali; Bobda, Christophe; Bednara, Marcus; Teich, Jürgen (Proc. of the International Parallel and Distributed Processing Symposium (IPDPS-2004), Reconfigurable Architectures Workshop, 2004)
By increasing the amount of resources on reconfigurable platforms with the abililty of partial reconfigurability, the issues of the management of these resources and their sharing among different tasks will become more of a concern. Online placement is one of these management issues that is investigated in this paper. Here we present a new approach for online placement of modules on reconfigurable devices, by managing the occupied space rather the free space on the device. Also an optimization of communication between running modules themselves and outside of the chip is proposed. The experimental results show a considerable decrease in communication and routing costs.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.anewap

A New Approach for Reconfigurable Massively Parallel Computers - Ahmadinia, Ali; Bobda, Christophe; Danne, Klaus; Teich, Jürgen (Proceedings of the IEEE International Conference on Field-Programmable Technology, 2003)
We present a new approach for reconfigurable massively parallel computers. The approach uses FPGA as reconfigurable device to build parallel computers which can adapt their physical topology to match the virtual topology used to model the parallel computation paradigm of a given application. We use a case study in which a virtual ring topology is first simulated on a tree topology and then directly implemented in an FPGA configuration. Preliminary results show that we can increase the performance of the parallel computers which make use of message passing interface by afactor of up to 20 % if a reconfigurable topology approach is used.
UnivIS-Import:2015-04-16:Pub.2003.tech.IMMD.inform.anewap_5

A new approach to solving resource-constrained scheduling problems based on a flow-model - Teich, Jürgen; Thiele, Lothar (1996)

A New Time-Independent Reliability Importance Measure - Borgonovo, Emanuele; Aliee, Hananeh; Glaß, Michael; Teich, Jürgen (European Journal of Operational Research, 2016)

An FPGA Avro Parser Generator for Accelerated Data Stream Processing - Hahn, Tobias; Schüll, Daniel; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC), 2023)
Big Data applications frequently involve processing data streams encoded in semi-structured data formats such as JSON, Protobuf, or Avro. A major challenge in accelerating data stream processing on FPGAs is that the parsing of such data formats is usually highly complex. This is especially true for JSON parsing on FPGAs, which lies in the focus of related work. The parsing of the binary Avro format, on the other hand, is perfectly suited for being processed on FPGAs and can thus serve as an enabler for data stream processing on FPGAs. In this realm, we present a methodology for parsing, projection, and selection of Avro objects, which enforces an output format suitable for further processing on the FPGA. Moreover, we provide a generator to automatically create accelerators based on this methodology. The obtained accelerators can achieve significant speedups compared to CPU-based parsers, and at the same time require only very few FPGA resources. <br
Keywords: Avro; parsing; FPGA; semi-structured data; accelerator

An FPGA-Based Dynamically Reconfigurable Platform: from Concept to Realization - Majer, Mateusz (Proceedings of 16th International Conference on Field Programmable Logic and Applications, 2006)
Dynamically reconfigurable FPGA-based systems offer a new kind of flexibility such as on-demand computing, self-adaption and self-optimization capabilities by restructuring the hardware at run-time. Using partial dynamic reconfiguration allows the main system to run uninterrupted during the reconfiguration process in addition to the reduced time for the reconfiguration process. However, existing FPGA-based platforms are hampered by physical restrictions limiting the practicability of partial reconfiguration. This led us to the concept of the Erlangen Slot Machine architecture in order to eliminate the physical and technical constraints. ©2006 IEEE.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.anfpga

An FPGA Implementation of a Threat-based Strategy for Connect6 - Ziermann, Tobias; Schmidt, Bernhard; Mühlenthaler, Moritz; Ziener, Daniel; Angermeier, Josef; Teich, Jürgen (Proceedings of the International Conference on Field-Programmable Technology, 2011)
In this paper, we present a strategy and an FPGA implementation of a Connect6 player submitted to the FPT 2011 Design Competition. Connect6 is a two-player strategy board game. The winner of the game is the player who first gets six pieces of his color in a connected horizontal, vertical or diagonal line. We assign a strategic value to each potential move depending on the current board configuration. Our approach uses a minimal amount of situation dependent game logic in order to take full advantage of the available compute resources and parallelism. The FPGA implementation of this strategy always wins against the software opponent provided for the competition. Additionally, our implementation wins on average against different software AIs from [1], as long as no sophisticated game-tree search is performed by the software. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.anfpga

An Image Processing Library for C-based High-Level Synthesis - Schmid, Moritz; Apelt, Nicolas; Hannig, Frank; Teich, Jürgen (Proc. of Field-Programmable Logic and Applications (FPL), 2014)
We introduce a library for the productive development of image processing accelerators using C-based high-level synthesis. The key concept of our approach is to provide a set of generic building blocks that is applicable to a multitude of image processing applications. An efficient memory architecture that facilitates easy integration of point and local image processing operators is the centerpiece of the library. The generic building blocks are kept very compact and can be tailored to support sophisticated processing techniques. The representation enables the designer to comply with specific design requirements, such as stringent timing constraints or limited resource budgets. Results show a significant gain in productivity compared to hand coded implementation while delivering comparable performance and resource requirements.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.animag

An Integrated Simulation Framework for Invasive Computing - Gerndt, Michael; Hannig, Frank; Herkersdorf, Andreas; Hollmann, Andreas; Meyer, Marcel; Roloff, Sascha; Weidendorfer, Josef; Wild, Thomas; Zaib, Aurang (Proc. of the Forum on Specification & Design Languages (FDL), 2012)
The trend of current and future domain-specific MPSoCs towards heterogeneous and tiled architectures as well as the increasing number of cores on a single chip impedes the design and the parallel programming of such computing systems. To tackle this problem a new computing paradigm called invasive computing has recently been proposed. Here, the workload and its distribution are not known at compile-time but are highly dynamic and can be adapted to the status (load, temperature, etc.) of the underlying architecture at run-time. The architectures envisaged for this resource-aware programming approach range from standard RISC core based platforms, tightly-coupled processor arrays for exploiting loop level parallelism to HPC systems. In order to explore such heterogeneous invasive architectures during early design phases, new means for modeling and simulating are required. Therefore, we present a novel and flexible simulation framework, which allows to model and simulate resource-aware applications on invasive architectures (including the associated system software) by integrating different architectural simulators in a modular way. © 2012 ECSI.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.aninte
Keywords: Architecture simulation; Hardware/software modeling and simulation; Parallel computing

An operating system infrastructure for fault-tolerant reconfigurable networks - Koch, Dirk; Streichert, Thilo; Dittrich, Steffen; Strengert, Christian; Haubelt, Christian; Teich, Jürgen (Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS 2006), 2006)
Dynamic hardware reconfiguration is becoming a key technology in embedded system design that offers among others new potentials in dependable computing. To make system designers benefit from this new technology, powerful infrastructures and programming environments are needed. In this paper, we will propose new concepts of an operating system (OS) infrastructure for reconfigurable networks that allow to efficiently design fault-tolerant systems. For this purpose, we consider a hardware/software solution that supports dynamic rerouting, hardware and software task migration, hardware/software task morphing, and online partitioning. Finally, we will present an implementation of such a reconfigurable network providing this OS infrastructure. © Springer-Verlag Berlin Heidelberg 2006.

A novel event insertion heuristic for creating feasible course timetables - Wanka, Rolf; Mühlenthaler, Moritz (Proc. 8th International Conference on the Practice and Theory of Automated Timetabling (PATAT), 2010)
We propose a novel event insertion heuristic for finding feasible solutions for instances of the University Course Timetabling Problem (UCTP). We introduce and apply a new neighbourhood structure on partial timetables that permits to approach a feasible timetable. The key insight is that an event can be inserted in a time slot if all the events conflicting with it are moved to other time slots. In order to prevent our event insertion heuristic from running into local optima, a simple perturbation strategy is employed additionally. Our experimental results show that our event insertion heuristic yields superior results compared to other state-of-The-Art feasible solution generation algorithms for a large number of corresponding benchmark instances.
Keywords: Course timetabling problems; Feasible solution generation; Kempe move

A Novel Event Insertion Heuristic for Finding Feasible Solutions of Course Timetabling Problems - Mühlenthaler, Moritz; Wanka, Rolf (Proc. 8th Int. Conf. on the Practice and Theory of Automated Timetabling (PATAT), 2010)
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.infalg._anove

A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators - Bhadouria, Vivek Singh; Tanase, Alexandru-Petru; Schmid, Moritz; Hannig, Frank; Teich, Jürgen; Ghoshal, Dibyendu (Journal of Signal Processing Systems, 2016)

A Novel NoC-Architecture for Fault Tolerance and Power Saving - Heißwolf, Jan; Friederich, Stephanie; Masing, Leonard; Weichslgartner, Andreas; Zaib, Aurang; Stein, Carsten; Duden, Marco; Teich, Jürgen; Herkersdorf, Andreas; Becker, Jürgen (In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS, 2016)

A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms - Letras, Martin; Morales-Reyes, Alicia; Cumplido, René; Martínez-Peñaloza, María Guadalupe; Feregrino-Uribe, Claudia (Microprocessors and Microsystems, 2024)
Solving optimization problems while fulfilling real-time constraints requires high algorithmic and processing performance. Cellular Genetic Algorithms (cGAs) have been competitive at difficult single objective combinatorial and continuous domain problems. Moreover, it has been demonstrated that structural properties in cGAs, such as population topology dimension, local neighborhood configuration and ad-hoc selection mechanisms, allow not only further algorithmic improvement but also, these characteristics can be combined at hardware level for acceleration. In this article, a novel partition strategy to exploit 3D cGAs population dynamics on a 2D processing array using Field Programmable Gate Arrays (FPGAs) as the target processing platform is presented. The proposed architecture fits as an optimization module within an embedded system where real-time constraints must be fulfilled. Therefore, it is important to find an optimal trade-off between hardware resources usage and searching time. Overall results demonstrate that the proposed architecture can run up to 90 MHz when tackling continuous benchmark functions. Moreover, speed-up of up to three and two orders of magnitude are achieved in comparison to a single CPU and a parallel GPU respectively.
CRIS-Team Scopus Importer:2024-01-05
Keywords: Cellular Genetic Algorithms; Field Programmable Gate Arrays; Optimization methods; Parallel hardware architectures

AnyHLS: High-Level Synthesis with Partial Evaluation - Özkan, Mehmet Akif; Pérard-Gayot, Arsène; Membarth, Richard; Slusallek, Philipp; Leißa, Roland; Hack, Sebastian; Teich, Jürgen; Hannig, Frank (International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2020)
FPGAs excel in low power and high throughput computations, but they are challenging to program. Traditionally, developers rely on hardware description languages like Verilog or VHDL to specify the hardware behavior at the register-transfer level. High-Level Synthesis (HLS) raises the level of abstraction, but still requires FPGA design knowledge. Programmers usually write pragma-annotated C/C++ programs to define the hardware architecture of an application. However, each hardware vendor extends its own C dialect using its own vendor-specific set of pragmas. This prevents portability across different vendors. Furthermore, pragmas are not first-class citizens in the language. This makes it hard to use them in a modular way or design proper abstractions. In this paper, we present AnyHLS, an approach to synthesize FPGA designs in a modular and abstract way. AnyHLS is able to raise the abstraction level of existing HLS tools by resorting to modern programming language features such as types and higher-order functions as follows: First, partial evaluation is used to specialize and to optimize the user application based on a library of abstractions. Finally, the backend of AnyHLS generates vendor-specific HLS code for Intel and Xilinx FPGAs. Portability is obtained by avoiding any vendor-specific pragmas at the source code. In order to validate achievable gains in productivity, a library for the domain of image processing is introduced as a case study, and its synthesis results are compared with several state-of-the-art DSL approaches for this domai

AnyHLS: High-Level Synthesis with Partial Evaluation - Özkan, Mehmet Akif; Pérard-Gayot, Arsène; Membarth, Richard; Slusallek, Philipp; Leißa, Roland; Hack, Sebastian; Teich, Jürgen; Hannig, Frank (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020)
FPGAs excel in low power and high throughput computations, but they are challenging to program. Traditionally, developers rely on hardware description languages like Verilog or VHDL to specify the hardware behavior at the register-transfer level. High-Level Synthesis (HLS) raises the level of abstraction but still requires FPGA design knowledge. Programmers usually write pragma-annotated C/C++ programs to define the hardware architecture of an application. However, each hardware vendor extends its own C dialect using its own vendor-specific set of pragmas. This prevents portability across different vendors. Furthermore, pragmas are not first-class citizens in the language. This makes it hard to use them in a modular way or design proper abstractions. In this paper, we present AnyHLS, an approach to synthesize FPGA designs in a modular and abstract way. AnyHLS is able to raise the abstraction level of existing HLS tools by resorting to modern programming language features such as types and higher-order functions as follows: First, partial evaluation is used to specialize and to optimize the user application based on a library of abstractions. Finally, the backend of AnyHLS generates vendor-specific HLS code for Intel and Xilinx FPGAs. Portability is obtained by avoiding any vendor-specific pragmas at the source code. In order to validate achievable gains in productivity, a library for the domain of image processing is introduced as a case study, and its synthesis results are compared with several state-of-the-art DSL approaches for this domain.

Any load-balancing regimen for evolving tree computations on circulant graphs is asymptotically optimal - Wanka, Rolf (Proc. 28th International Workshop on Graph-Theoretic Concepts in Computer Science (WG), 2002)
We analyze evolving tree computations on circulant (rings with "regular" chords) and related graphs. In an evolving α-ary tree computation, a complete tree grows level by level, i. e., every leaf generates α new nodes that become the new leaves. The load balancing task is to spread the new nodes on a network of processors in the moment they were created in such a way that the accumulated number of nodes per processor, i. e., its load, is as close as possible to the average number of nodes per processor. Gao/Rosenberg [2] introduced evolving computations and investigated the growth of complete binary trees on rings of processors. They showed that the so-called ks-regimen behaves optimally in the course of long computations. In this paper, we generalize evolving computations to trees of arbitrary degree and we generalize the regimen notion. We show that any regimen behaves optimally. For this purpose, we model the actual load distribution, the generation process, and the distribution regimen by formal infinite polynomials. Then we show that evaluating these polynomials for certain inputs leads to the analysis of these regimens on circulant and related graphs. It is shown that any regimen leads to a close to optimal load distribution. © Springer-Verlag Berlin Heidelberg 2002.

Anytime Floating-Point Addition and Multiplication – Concepts and Implementations - Brand, Marcel; Witterauf, Michael; Bosio, Alberto; Teich, Jürgen (Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors, 2020)
In this paper, we present anytime instructions for floating- point additions and multiplications. Specific to such instructions is their ability to compute an arithmetic operation at a programmable accuracy of a most significant bits where a is encoded in the instruction itself. Contrary to reduced-precision architectures, the word length is maintained throughout the execution. Two approaches are presented for the efficient implementation of anytime additions and multiplications, one based on on-line arithmetic and the other on bitmasking. We propose implementations of anytime functional units for both approaches and evaluate them in terms of error, latency, area, as well as energy savings. As a result, 15% of energy can be saved on average while computing a floating-point addition with an error of less than 0.1%. Moreover, large latency and energy savings are reported for iterative algorithms such as a Jacobi algorithm with savings of up to 39% in energy.

Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic - Brand, Marcel; Witterauf, Michael; Hannig, Frank; Teich, Jürgen (ACM International Conference on Computing Frontiers 2019, 2019)

Apollo: Modular and Distributed Runtime System for Serverless Function Compositions on Cloud, Edge, and IoT Resources - Smirnov, Fedor; Pourmohseni, Behnaz; Fahringer, Thomas (HiPS 2021 - Proceedings of the 1st Workshop on High Performance Serverless Computing, co-located with HPDC 2021, 2021)
This paper provides a first presentation of Apollo, a runtime system for serverless function compositions distributed across the cloud-edge-IoT continuum. Apollo's modular design enables a fine-grained decomposition of the runtime implementation(scheduling, data transmission, etc.) of the application, so that each of the numerous implementation decisions can be optimized separately, fully exploiting the potential for the optimization of the overall performance and costs. Apollo features (a) a flexible model of the application and the available resources and (b) an implementation process based on a large set of independent agents. This flexible structure enables distributing not only the processing, but the implementation process itself across a large number of resources, each running an independent Apollo instance. The ability to flexibly determine the placement of implementation actions opens up new optimization opportunities, while at the same time providing access to greater computing power for optimizing challenging decisions such as task scheduling and the placement and routing of data.
CRIS-Team Scopus Importer:2021-07-30
Keywords: event-based; iot; orchestration; serverless; workflows

Application-aware cross-layer reliability analysis and optimization - Aliee, Hananeh; Glaß, Michael; Chen, Liang; Ebrahimi, Mojtaba; Khosravi, Faramarz; Kleeberger, Veit B.; Listl, Alexandra; Müller-Gritschneder, Daniel; Oboril, Fabian; Schlichtmann, Ulf; Tahoori, Mehdi B.; Teich, Jürgen; et al. (it - Information Technology, 2015)

Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms - Gangadharan, Deepak; Sousa, Éricles; Lari, Vahid; Hannig, Frank; Teich, Jürgen (Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), 2015)
The growing demand of computationally intensive algorithms/applications has resulted in the widespread acceptance of heterogeneous MPSoC platforms. The primary reason for this trend is due to the better performance and power efficiency exhibited by heterogeneous architectures consisting of standard processor cores and hardware accelerators. However, multiple processors accessing shared resources such as cache/memory and buses may lead to significant contention on them, thereby decreasing not only the performance, but also timing predictability. Moreover, the effect of shared resource contention worsens in the presence of multiple application scenarios with different execution and communication bandwidth requirements. To mitigate this problem, we first propose a Dynamic Bus Reconfiguration Policy (DBRP) that decides when to reconfigure a shared bus between Non-Preemptive Fixed Priority (NP-FP) and Time-Division Multiple Access (TDMA) scheduling. The required TDMA slot sizes are computed on-the-fly before NP-FP to TDMA reconfiguration such that deadlines of all Hard Real-Time (HRT) applications are satisfied and all Soft Real-Time (SRT) applications are serviced evenly. Our proposed DBRP has been implemented on a real MPSoC platform consisting of cores connected by the AMBA AHB. The case studies demonstrate that reconfiguration of bus arbitration ensures that communication deadline constraints of HRT applications are maximally satisfied with low hardware and reconfiguration overhead.

Application Mapping Methodologies for Invasive NoC-Based Architectures - Weichslgartner, Andreas (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2017)

Applied Reconfigurable Computing. Architectures, Tools, and Applications - Derrien, Steven; Hannig, Frank; Diniz, Pedro C.; Chillet, Daniel (Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021)

Approximate Adder Structures on FPGAs - Becher, Andreas; Echavarria Gutiérrez, Jorge Alfonso; Ziener, Daniel; Teich, Jürgen (AxC15: 1st Workshop on Approximate Computing, 2015)
UnivIS-Import:2017-12-18:Pub.2015.tech.IMMD.inform.approx

Approximate Computing - Keszöcze, Oliver (it - Information Technology, 2022)
CRIS-Team WoS Importer:2022-05-20

Approximate Computing Extensions for the Clash HDL Compiler - Keszöcze, Oliver; Kießling, Michael (Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2021)
Approximate Computing is a novel design paradigm sacrificing computational accuracy for gains in other non-functional properties, such as area, latency, and power consumption. Many approximation techniques operate on the netlist of a circuit. We believe that working on a higher level of abstraction is beneficial. For this, we chose the high-level hardware description language Clash. The language is based on the functional programming language Haskell, i.e. describes hardware in a very abstract manner allowing to focus on the functionality instead of technical details. We extend the Clash compiler to support multiple approximation techniques. Initial experiments show promising results with respect to reductions in area, latency, and power consumption of the synthesized approximated circuits.<br

Approximate Frequent Itemsets Mining on Data Streams Using Hashing and Lexicographic Order in Hardware - Bustio, Lazaro; Cumplido, René; Hernández-León, Raudel; Bande, Jose M.; Letras, Martin; Feregrino, Claudia (8th Latin American Symposium on Circuits and Systems (LASCAS), 2017)
Frequent Itemsets Mining is a data mining technique that has been used to extract useful knowledge from datasets; And recently, from data streams. Data streams are an unbounded and infinite flow of data arriving at high rates; Data Mining approaches for Frequent Itemsets Mining can not be used straightforwardly. Finding an alternative to the discovery of frequent itemsets on data streams is an active research topic. This paper introduces the first hardware-based algorithm for search task. It uses the top-k frequent 1-itemets detection, hashing and the lexicographic order of received items. Experimental results demonstrates the viability of the proposed method.

Approximate Logic Synthesis of Very Large Boolean Networks - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Teich, Jürgen (Design, Automation and Test in Europe, DATE 2021, 2021)

Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012)
The design and the programming of heterogeneous future MPSoCs including thousands of processor cores is a hard challenge. Means are necessary to program and simulate the dynamic behavior of such systems in order to dimension the hardware design and to verify the software functionality as well as performance goals. Cycle-accurate simulation of multiple parallel applications simultaneously running on different cores of the architecture would be much too slow and is not the desired level of detail. In this paper, we therefore present a novel high-level simulation approach which tackles the complexity and the heterogeneity of such systems and enables the investigation of a new computing paradigm called invasive computing. Here, the workload and its distribution are not known at compile-time but are highly dynamic and have to be adapted to the status (load, temperature, etc.) of the underlying architecture at run-time. We propose an approach for the modeling of tiled MPSoC architectures and the simulation of resource-aware programming concepts on these. This approach delivers important timing information about the parallel execution and also is taking into account the computational properties of possibly different types of cores. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.approx

Approximationsalgorithmen - Eine Einführung - Wanka, Rolf (Teubner, 2006)
UnivIS-Import:2015-04-02:Pub.2006.tech.IMMD.infalg._appro

A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices - Ahmadinia, Ali; Bobda, Christophe; Ding, Ji; Fekete, Sandor P.; Majer, Mateusz; Teich, Jürgen; Van Der Veen, Jan C. (Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping, 2005)
Management of communication by on-line routing in new FPGAs with a large amount of logic resources and partial reconfigurability is a new challenging problem. A Network-on-Chip (NoC) typically uses packet routing mechanism, which has often unsafe data transfers, and network interface overhead. In this paper, circuit routing for such dynamic NoCs is investigated, and a practical 1-dimensional network with an efficient routing algorithm is proposed and implemented. Also, this concept has been extended to the 2-dimensional case. The implementation results show the low area overhead and high performance of this network. © 2005 IEEE.
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.apract

A Predictive Dynamic Power Management for LTE-Advanced Mobile Devices - Ah Sue, Jonathan; Brand, Peter; Brendel, Johannes; Hasholzner, Ralph; Falk, Joachim; Teich, Jürgen (2018 IEEE Wireless Communications and Networking Conference (WCNC'18), 2018)
Power consumption is a key challenge for LTE-Advanced or future 5G mobile devices and current power management systems successfully achieve significant power savings. However, these systems are driven by static rules and provide a posteriori responses to traffic and context changes. In this paper, we propose a smart dynamic power management system for cellular modems, extending existing power saving mechanisms by using machine learning-based traffic prediction. With the a priori knowledge of specific scheduling messages, internal device parameters can be finely tuned to improve the modem power consumption. In order to accurately estimate the power saving potential of several LTE use cases, we build a relevant data set of live network modem traces, as well as a power model of the baseband physical layer and radio frequency components. Subsequently, we propose an evaluation methodology and apply it to analyze the predictive power management performance in terms of error rate and global power consumption outcome. Our analysis results in maximal power savings of 12% for meaningful traffic scenarios as well as the identification of variables of interest to improve the proposed power manage

A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture - Sousa, Éricles; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, 2013)
Continuous software and hardware innovations impose on the one hand a high degree of flexibility from an algorithm and on the other hand it requires that a given processing architecture has the capability to adapt to changing computation patterns at run-time. In this work, we demonstrate how a computer vision application can adapt itself at runtime in order to satisfy different requirements of quality and throughput. For that, we consider an implementation of the Harris Corner Detector on an MPSoC (Multi-Processor System-on-Chip) architecture composed of a quad-core RISC processor and one accelerator based on a programmable massively parallel processor array.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.aproto

A Prototype of an Invasive Tightly-Coupled Processor Array - Muddasani, Shravan; Boppu, Srinivas; Hannig, Frank; Kuzmin, Boris; Lari, Vahid; Teich, Jürgen (Proc. of the 2012 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2012)
Invasive computing is a novel paradigm for the exploitation of runtime parallelism of future MPSoC architectures through resource-aware programming and dynamic reconfiguration of the underlying architectures. Based on the state and availability of resources, an invasive algorithm organizes its computation itself. A highly-parameterizable weakly programmable VLIW processor array called Tightly-Coupled Processor Array (TCPA) that is augmented with decentralized units for hardware-accelerated resource exploration is well suited for invasive computing, especially for accelerating computationally intensive loop programs. We present a prototype of an invasive TCPA, which demonstrates the benefits of invasive computing using the example of video processing. More specifically, the targeted applications in this prototype are 2D convolution filters (such as edge detection and Gaussian filtering) that are applied on a real-time input video stream. For different workload scenarios and resource competition between applications, a varying quality of the output video streams is shown. © 2012 ECSI.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.aproto

A Quick Tour of High-Level Synthesis Solutions for FPGAs - Hannig, Frank (FPGAs for Software Programmers, 2016)

A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip - May, Matthias; Wehn, Norbert; Bouajila, Abdelmajid; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas; Ziener, Daniel; Teich, Jürgen (Proc. Design, Automation and Test in Europe, 2010)
Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only profitable if the costs in terms of area, energy and delay for reliability keep within limits. Therefore, the traditional worst case design methodology will become infeasible. Future architectures have to be error resilient, i.e., the hardware architecture has to tolerate autonomously transient errors. In this paper, we present an FPGA based rapid prototyping system for multi-processor systems-on-chip composed of autonomous hardware units for error-resilient processing and interconnect. This platform allows the fast architectural exploration of various error protection techniques under different failure rates on the microarchitectural level while keeping track of the system behavior. We demonstrate its applicability on a concrete wireless communication system. © 2010 EDAA.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.arapid

Architecture/Compiler Co-Exploration for ASIPs - Fischer, Dirk; Teich, Jürgen; Thies, Michael; Weper, Ralph (International Journal of Circuits, Systems and Signal Processing, 2002)
UnivIS-Import:2015-03-09:Pub.2002.tech.IMMD.inform.archit

Architecture Decomposition in System Synthesis of Heterogeneous Many-Core Systems - Richthammer, Valentina; Schwarzer, Tobias; Wildermann, Stefan; Teich, Jürgen; Glaß, Michael (55th ACM/EDAC/IEEE Design Automation Conference (DAC 2018), 2018)

Architecture of computing systems – ARCS 2016: 29th international conference Nuremberg, Germany, April 4-7, 2016 Proceedings - Hannig, Frank; Cardoso, João; Fey, Dietmar; Schröder-Preikschat, Wolfgang; Teich, Jürgen (Springer Verlag, 2016)

Architectures, Methods, and Tools for Distributed Run-Time Reconfigurable FPGA-based Systems - Koch, Dirk (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2009)

Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures - Wolinski, Christophe; Kuchcinski, Krzysztof; Teich, Jürgen; Hannig, Frank (Proceedings of the International Conference on Field Programmable Logic and Applications, 2008)
In this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized significantly (62% in average). ©2008 IEE
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.areaan

A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays - Sousa, Éricles; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (International Conference on ReConFigurable Computing and FPGA's (ReConFig), 2017)

Are Current ESL Tools Meeting the Requirements of Advanced Embedded Systems? - Teich, Jürgen (CODES ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, 2006)
Electronic System Level (ESL) tools are becoming more and more important in order to bridge the well-known productivity design gap. This panel brings together specialists from industry and ESL tool houses to discuss whether current ESL tools available are usable and meeting the requirements of the industry. In particular, we would like to know to what degree currently available tools from major ESL tool houses are used for designing what kind of systems in industry, and for what purpose such as analysis, design space exploration, or synthesis, etc. these tools are currently used. Also, we would like to discuss to what degree existing tools can help in reducing design time, and finally, what the industry sees the most challenging features of tools currently not yet available. On the other side, we would like to know the opinion of the ESL tool houses what they see the most important offerings of ESL tools currently available as well as the most challenging points and problems why ESL hasn't really taken off so far. Could this either be an industry issue, a methodology issue, a design issue or a tool issue. © Copyright 2006 ACM.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.arecur
Keywords: Behavioral and system synthesis; Electronic design automation; Electronic System Level (ESL) design

Artificial Intelligence for Molecular Communication - Bartunik, Max; Kirchner, Jens; Keszöcze, Oliver (it - Information Technology, 2023)
Keywords: Molecular Communication; Demodulation; Convolutional Neural Network

A Rule-Based Quasi-Static Scheduling Approach for Static Islands in Dynamic Dataflow Graphs - Falk, Joachim; Zebelein, Christian; Haubelt, Christian; Teich, Jürgen (ACM Transactions on Embedded Computing Systems, 2013)
In this article, an efficient rule-based clustering algorithm for static dataflow subgraphs in a dynamic dataflow graph is presented. The clustered static dataflow actors are quasi-statically scheduled, in such a way that the global performance in terms of latency and throughput is improved compared to a dynamically scheduled execution, while avoiding the introduction of deadlocks as generated by naive static scheduling approaches. The presented clustering algorithm outperforms previously published approaches by a faster computation and more compact representation of the derived quasi-static schedule. This is achieved by a rulebased approach, which avoids an explicit enumeration of the state space. A formal proof of the correctness of the presented clustering approach is given. Experimental results show significant improvements in both, performance and code size, compared to a state-of-the-art clustering algorithm. © 2013 ACM.
UnivIS-Import:2019-03-25:Pub.2013.tech.IMMD.inform.aruleb
Keywords: Actor-oriented design; Clustering; Data flow analysis; Scheduling

A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs - Falk, Joachim; Zebelein, Christian; Haubelt, Christian; Teich, Jürgen (ACM Transactions on Embedded Computing Systems, 2013)
In this article, an efficient rule-based clustering algorithm for static dataflow subgraphs in a dynamic dataflow graph is presented. The clustered static dataflow actors are quasi-statically scheduled, in such a way that the global performance in terms of latency and throughput is improved compared to a dynamically scheduled execution, while avoiding the introduction of deadlocks as generated by naive static scheduling approaches. The presented clustering algorithm outperforms previously published approaches by a faster computation and more compact representation of the derived quasi-static schedule. This is achieved by a rulebased approach, which avoids an explicit enumeration of the state space. A formal proof of the correctness of the presented clustering approach is given. Experimental results show significant improvements in both, performance and code size, compared to a state-of-the-art clustering algorithm. © 2013 ACM.
Keywords: Actor-oriented design; Clustering; Data flow analysis; Scheduling

A rule-based static dataflow clustering algorithm for efficient embedded software synthesis - Falk, Joachim; Zebelein, Christian; Haubelt, Christian; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE'11), 2011)
In this paper, an efficient embedded software synthesis approach based on a generalized clustering algorithm for static dataflow subgraphs embedded in general dataflow graphs is proposed. The clustered subgraph is quasi-statically scheduled, thus improving performance of the synthesized software in terms of latency and throughput compared to a dynamically scheduled execution. The proposed clustering algorithm outperforms previous approaches by a faster computation and a more compact representation of the derived quasi-static schedules. This is achieved by a rule-based approach, which avoids an explicit enumeration of the state space. Experimental results show significant improvements in both performance and code size when compared to a state-of-the-art clustering algorithm. © 2011 EDAA.
Keywords: Actor-Oriented Design; MPSoC Scheduling; Software Synthesis

A Runtime System for Finite Element Methods in a Partitioned Global Address Space - Groth, Stefan; Grünewald, Daniel; Teich, Jürgen; Hannig, Frank (Proceedings of the 17th ACM International Conference on Computing Frontiers (CF), 2020)
With approaching exascale performance, applications in the domain of High-Performance Computing (HPC) have to scale to an ever-increasing amount of compute nodes. The Global Address Space Programming Interface (GASPI) communication API promises to handle this challenge by providing a highly flexible and efficient programming model in a Partitioned Global Address Space (PGAS). Suitable applications targeting supercomputers include the domain of mesh-based solvers for Partial Differential Equations (PDEs) due to their high computational intensity. The implementation of such solvers is highly interdisciplinary, which therefore requires an abstraction of hardware-specific parallelization techniques from developing numerical algorithms. We present an open-source Run-Time System (RTS) that distributes and parallelizes device-agnostic kernels, which define algorithms on unstructured grids. We describe how the RTS abstracts common parts of iterative solvers and further explain how to parallelize and distribute these components. We further show the efficiency of our approach for several microbenchmarks and an implementation of the Discontinuous Galerkin Method (DGM). The results show that we can almost completely hide all synchronization overhead and that the RTS only imposes a small computational cos
Keywords: Runtime System; Finite Element Methods; PGAS; GASPI

A Safari through FPGA-based Neural Network Compilation and Design Automation Flows - Plagwitz, Patrick; Hannig, Frank; Ströbel, Martin; Strohmeyer, Christoph; Teich, Jürgen (Proceedings of the 29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021)

A scalable and customizable processor array for implementing cellular genetic algorithms - Letras, Martin; Morales-Reyes, Alicia; Cumplido, René (Neurocomputing, 2016)
<span style="color: rgb(46, 46, 46); font-family: Arial, Helvetica, "Lucida Sans Unicode", "Microsoft Sans Serif", "Segoe UI Symbol", STIXGeneral, "Cambria Math", "Arial Unicode MS", sans-serif; font-size: 16px; word-spacing: -1.35px;">Architectures design for Genetic Algorithms (GAs) has proved its effectiveness to tackle hard real-time constrained problems that require an optimization mechanism in one of their phases. Most of these approaches are problem dependent and cannot be easily adapted to other problems. Moreover, GAs based architectures preserve the algorithmic structure of a panmictic population in a sequential GA and therefore they are similar to a software implementation. Recently, a combination of GAs, both sequential and parallel and reconfigurable devices such as FPGAs have been merged to create GAs based parallel hardware architectures. This study proposes a novel hardware architectural framework that implements a fine-grained or cellular GAs while maintaining a toroidal connection among individuals within the population. Achieving massive parallelism is limited by available resources; therefore, the proposed architectural design implements a segmentation strategy that partitions the entire decentralized population while maintaining original algorithmic interaction among solutions. The proposed architecture aims at preserving fine-grained GAs algorithmic structure while improving resources usage. It also allows flexibility in terms of population and solutions representation size and the evaluation module containing the objective function is interchangeable.
Keywords: Cellular Genetic Algorithms; Hardware Architecture; FPGA

A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms - Köstler, Harald; Schmitt, Christian; Kuckuk, Sebastian; Kronawitter, Stefan; Hannig, Frank; Teich, Jürgen; Rüde, Ulrich; Lengauer, Christian (International Journal of Computational Science and Engineering, 2017)
Many problems in computational science and engineering involve partial differential equations and thus require the numerical solution of large, sparse (non)linear systems of equations. Multigrid is known to be one of the most efficient methods for this purpose. However, the concrete multigrid algorithm and its implementation highly depend on the underlying problem and hardware. Therefore, changes in the code or many different variants are necessary to cover all relevant cases. In this article we provide a prototype implementation in Scala for a framework that allows abstract descriptions of PDEs, their discretization, and their numerical solution via multigrid algorithms. From these, one is able to generate data structures and implementations of multigrid components required to solve elliptic PDEs on structured grids. Two different test problems showcase our proposed automatic generation of multigrid solvers for both CPU and GPU target platform

A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs - Spieck, Jan; Wildermann, Stefan; Teich, Jürgen (ACM Transactions on Design Automation of Electronic Systems, 2024)

A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor - Glein, Robert; Schmidt, Bernhard; Rittner, Florian; Teich, Jürgen; Ziener, Daniel (Proceedings of Field-Programmable Custom Computing Machines (FCCM 2014), 2014)
In this paper, we propose a self-adaptive FPGAbased, partially reconfigurable system for space missions in order to mitigate Single Event Upsets in the FPGA configuration and fabric. Dynamic reconfiguration is used here for an on-demand replication of modules in dependence of current and changing radiation levels. More precisely, the idea is to trigger a redundancy scheme such as Dual Modular Redundancy or Triple Modular Redundancy in response to a continuously monitored Single Event Upset rate measured inside the on-chip memories itself, e.g., any subset (even used) internal Block RAMs. Depending on the current radiation level, the minimal number of replicas is determined at runtime under the constraint that a required Safety Integrity Level for a module is ensured and configured accordingly. For signal processing applications it is shown that this autonomous adaption to the different solar conditions realizes a resource efficient mitigation. In our case study, we show that it is possible to triplicate the data throughput at the Solar Maximum condition (no flares) compared to a Triple Modular Redundancy implementation of a single module. We also show the decreasing Probability of Failures Per Hour by 2 × 10 at flare-enhanced conditions compared with a non-redundant system. Our work is a part of the In-Orbit Verification of the Heinrich Hertz communication satellite.

A self-organizing distributed reinforcement learning algorithm to achieve fair bandwidth allocation for priority-based bus communication - Ziermann, Tobias; Mühleis, Nina; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 1st IEEE Workshop on Self-Organizing Real-Time systems (SORT 2010), 2010)
Due to the raising complexity in distributed embedded systems, a single designer will not be able to plan and organize the communication for such systems. Therefore, it will get more and more important to relieve the designer in that task. Our idea is a communication system that is capable to organize itself to satisfy predefined properties. In this paper, we want to solve the problem of establishing fair bandwidth sharing on priority-based buses by using simple local rules on the distributed system to avoid a single point of failure and cope with online system changes. Based on a game theoretical analysis, a multi-agent reinforcement learning algorithm is proposed that establishes fair bandwidth distribution. The main idea is to penalize nodes that claim too much bandwidth by the other nodes. We experimentally evaluated the algorithm with different parameter settings. The algorithm showed to converge to a fair solution in any experiment. This means the system is able to completely self-organize without global information for our assumptions. In addition, we could figure out that we can configure a trade-off between convergence speed and computation effort. We hope this is a small first step towards totally self-organizing real-time systems. © 2010 IEEE.
Keywords: Bus-based communication; Multi-agent reinforcement learning; Self-organizing

A self-propagating wakeup mechanism for point-to-point networks with partial network support - Seyler, Jan R.; Streichert, Thilo; Warkentin, Juri; Spägele, Matthias; Glaß, Michael; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE 2014), 2014)
As a result of the increased demand for bandwidth, current automotive networks are getting more heterogeneous. New technologies like Ethernet as a packet-switched point-to-point network are introduced. Nevertheless, the requirements on stand-by power consumption and short activation times are still the same as for existing field buses. Ethernet does not provide wakeup mechanisms that are sufficient for automotive systems. As a remedy, this paper introduces a novel physical-layer mechanism called Low Frequency Wakeup that is largely independent of the communication technology and topology used. It provides parallel and remote wakeup for all nodes even in a point-to-point network as well as full support of partial networking. The overall wakeup detection time is smaller than 10ms and every node can actively feed a wakeup signal asynchronously to all other nodes. In terms of latency, it is shown that Low Frequency Wakeup reaches a reduction of more than 30 % for a three-hop network and more than 50 % for a five-hop network in comparison to the current state-of-the-art technology for automotive point-to-point networks. © 2014 EDAA.

A Sequential Learning Resource Allocation Network for Image Processing Applications - Teich, Jürgen; Wildermann, Stefan (Proceedings of the 8th International Conference on Hybrid Intelligent Systems, 2008)
Online adaptation is a key requirement for image processing applications when used in dynamic environments. In contrast to batch learning, where retraining is required each time a new observation occurs, sequential learning algorithms offer the ability to iteratively adapt the existing classifier. In this paper, we present a neural network architecture and a fast online learning algorithm that allow to use the class of resource allocation networks for such adaptive image processing applications. The network is based on receptive fields that are processed by RBF sub-nets. The learning algorithm builds such networks online by adding new units to the sub-nets each time novel input data is observed. For this, we define a global and a local novelty criterion. Experimental results show that the proposed network outperforms existing RAN algorithms when used for face detection and recognition and is competitive with existing classifiers. © 2008 IEEE.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.aseque

A SystemC-based Design Methodology for Digital Signal Processing Systems - Haubelt, Christian; Falk, Joachim; Keinert, Joachim; Schlichter, Thomas; Streubühr, Martin; Deyhle, Andreas; Hadert, Andreas; Teich, Jürgen (EURASIP Journal on Embedded Systems, 2007)
Digital signal processing algorithms are of big importance in many embedded systems. Due to complexity reasons and due to the restrictions imposed on the implementations, new design methodologies are needed. In this paper, we present a SystemC-based solution supporting automatic design space exploration, automatic performance evaluation, as well as automatic system generation for mixed hardware/software solutions mapped onto FPGA-based platforms. Our proposed hardware/software codesign approach is based on a SystemC-based library called SysteMoC that permits the expression of different models of computation well known in the domain of digital signal processing. It combines the advantages of executability and analyzability of many important models of computation that can be expressed in SysteMoC. We will use the example of an MPEG-4 decoder throughout this paper to introduce our novel methodology. Results from a five-dimensional design space exploration and from automatically mapping parts of the MPEG-4 decoder onto a Xilinx FPGA platform will demonstrate the effectiveness of our approach.
UnivIS-Import:2015-04-14:Pub.2007.tech.IMMD.inform.asyste

A system-level approach to hardware reconfigurable systems - Haubelt, Christian; Otto, Stephan; Grabbe, Cornelia; Teich, Jürgen (Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05), 2005)
There is trend towards networked and distributed hardware reconfigurable systems, complicating the design process at the system-level. This paper will provide a solution to the problem of design space exploration for such embedded systems of the next generation. We will show the problems occurring while exploring the design space at the system-level, leading to new properties for valid implementations. The novelty of this approach lies in the support of explicit communication modeling and time-multiplexed architecture modeling in a single model. The proposed design space exploration is based on Evolutionary Algorithms and a new slack-based list scheduler. © 2005 IEEE.

A system-level synthesis approach from formal application models to generic bus-based MPSoCs - Gladigau, Jens; Gerstlauer, Andreas; Haubelt, Christian; Streubühr, Martin; Teich, Jürgen (Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2010)
System-level synthesis is the task of automatically implementing application models as hardware/software systems. It encompasses four basic sub tasks, namely decision making and refinement for both computation and communication. In the past, several system-level synthesis approaches have been proposed. However, it was shown that each of these approaches has drawbacks in at least one of the four sub tasks. In this paper, we present our efforts towards a comprehensive system-level synthesis by combining two academic system-level solutions into a seamless approach that automatically generates pin-accurate implementation-level models starting from a formal application model and generic MPSoC architecture templates. We analyze the system-level synthesis flow and define intermediate representations in terms of transaction level models that serve as link between existing tools. Furthermore, we present the automated transformation between models for combining two design flows. We demonstrate the combined flow on an industrial-strength example and show the benefits of fully automatic exploration and synthesis for rapid and early system-level design. ©2010 IEEE.

A Target Platform Description Language for Parallel Code Generation - Schmitt, Christian; Hannig, Frank; Teich, Jürgen (Workshop Proceedings of the 31st GI/ITG International Conference on Architecture of Computing Systems (ARCS), 2018)
Today, facilities used for scientific computing are highly parallel and becoming more and more heterogeneous. This trend can be easily seen in the TOP500 list, where an increasing number of systems is equipped with accelerators, such as GPUs or many-cores. To achieve the best performance on such machines, special tweaking of the code is necessary, which takes time and expert knowledge of the hardware and corresponding optimization techniques. Domain-specific languages (DSLs) are a remedy to this dilemma by separating the algorithm specification from its implementation, leaving room for optimizations to be applied automatically by the DSL compiler. Thus, the compiler needs to have a profound knowledge of the target platform, e.g., available accelerators and how to program them, details of the network topology to optimize communication patterns, as well as CPU specifications for cache optimizations and vectorization. In this paper, we introduce our approach to modeling hardware and software information to provide platform details that our code generator requires to optimize and emit code for the solution of partial differential equations using the geometric multigrid method.

A transformative approach to the partitioning of processor arrays - Teich, Jürgen; Thiele, Lothar (Proc. Int. Conf. on Application Specific Array Processors, 1992)
UnivIS-Import:2015-04-16:Pub.1992.tech.IMMD.inform.atrans

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation - Teich, Jürgen; Hannig, Frank; Ruckdeschel, Holger; Dutta, Hritam; Kissler, Dmitrij; Stravet, Andrej (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2007)

AUTO-GS: Self-optimization of NoC Traffic Through Hardware Managed Virtual Connections - Zaib, Aurang; Heisswolf, Jan; Weichslgartner, Andreas; Wild, Thomas; Teich, Jürgen; Becker, Jürgen; Herkersdorf, Andreas (Proc. 16th Euromicro Conference on Digital System Design, 2013)
Networks-on-Chip have shown their scalability for future many-core systems on chip. In real world scenarios, where multiple applications are being executed over a shared NoC based platform, efficient utilization of Networks-on-Chip resources becomes challenging. Methodologies are required to ensure better utilization of NoC, especially in the scenarios, where the communication patterns of NoC traffic are difficult to predict before run-time. In this paper, we propose a self-optimization mechanism which detects frequent communication by monitoring communication patterns at run-time and uses this information to establish virtual connections autonomously. Communication monitoring and connection establishment are realized in hardware. Hardware managed virtual connections lead to better utilization of NoC resources and reduce the communication latencies suffered by applications. In addition, energy consumption by the communication infrastructure is reduced. The proposed concept is investigated through simulation of real world application scenarios. The simulation results highlight the performance improvement and synthesis results show the low area overhead of the proposed hardware implementation. © 2013 IEEE.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.autogs

Automateddesign of two-dimensional rational decimation systems - Evans, Brian L.; Schwarz, Christian; Teich, Jürgen (Proc. IEEE Asilomar Conf. on Signals, Systems and Computers, 1994)
UnivIS-Import:2015-04-16:Pub.1994.tech.IMMD.inform.automa

Automated Design Space Exploration on System Level for Embedded Systems - Bednara, Marcus; Hardt, Wolfram; Rettberg, Achim; Teich, Jürgen (Proc. Ninth Annual International HDL Conference and Exhibition, 2000)
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.automa

Automatic and Optimized Generation of Compiled High-Speed RTL Simulators - Hannig, Frank; Kupriyanov, Olexiy; Teich, Jürgen (Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004), 2004)

Automatic communication-driven virtual prototyping and design for networked embedded systems - Falk, Joachim; Schwarzer, Tobias; Zhang, Liyuan; Glaß, Michael; Teich, Jürgen (Microprocessors and Microsystems, 2015)
This work presents a communication-driven virtual prototyping approach integrated in an existing ESL design methodology to automatically synthesize, evaluate, and optimize a data-flow application for mixed hardware/software and even networked MPSoCs. While existing synthesis tools are suitable for individual subsystems (e.g., software tasks for CPUs, hardware accelerators), the problem of establishing the communication between different subsystems that may even be simulated at different levels of abstraction is still challenging. As a remedy, we introduce the concept of bridge components in our architecture model that, during virtual prototyping, serve as integrators between subsystems that may have different communication protocols and be simulated at different levels of abstraction (e.g., TLM, behavioral level, RTL). We propose to consider bridges throughout the complete ESL design flow: Already during Design Space Exploration (DSE), the characteristics of bridge components such as implementation cost and additional latency on the application can be taken into account. Moreover, we extend the exploration model of the DSE to include required communication-related design decisions, i.e., the mapping of binary code for software tasks and the selection of different synchronization patterns for the communication. For virtual prototyping of implementation candidates derived by the DSE, the bridge components enable to automatically disassemble the system into subsystems and hand each subsystem over to an individual synthesis tool. When integrating the subsystems together, our methodology also synthesizes the interfaces for all bridges which significantly simplifies system integration. As a proof of concept, we present (I) a distributed control application that is transformed into a virtual prototype consisting of six subsystems and (II) a data-flow application from the video processing domain transformed into a virtual prototype consisting of three subsystems. The resulting subsystems can be concurrently simulated at TLM, behavioral level, and RTL. The experiments give evidence of the proposed technique's applicability, the achieved productivity gain, and the resulting simulation performance at the considered levels of abstractio
Keywords: Communication refinement; ESL design flow; SystemC-TLM; Virtual prototyping

Automatic Conversion of Simulink Models to SysteMoC Actor Networks - Letras, Martin; Falk, Joachim; Wildermann, Stefan; Teich, Jürgen (20th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2017)
In different domains, Simulink has gained a lot of acceptance because it is a robust tool for rapid design and simulation of control systems. However, it is not supported by Simulink. In the literature, there are some of the most popular translation tools in the world. C or C ++ code from Simulink models, which is used for implementation or validation purposes. (ESL) Design methodologies and tools like SystemCoDesigner. (DFGs) from a given Simulink model. (ESD) and design code for hardware / software parts directly from the ESL model. As a validation step, we found the results of the simulation in Simulink and the results of the DFG in SysteMoC for a signal processing case study.
Keywords: Data Flow Graph; Simulink; SyteMoC; Code Generation

Automatic FIR Filter Generation for FPGAs - Dutta, Hritam; Hannig, Frank; Teich, Jürgen; et al. (In Proceedings of the 5th International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS 2005), 2005)
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. PARO is a design system project for modeling, transformation, optimization, and synthesis of massively parallel VLSI architectures. The FIR filter generator employs during the design flow the following advanced transformations, (a) hierarchical partitioning in order to balance the amount of local memory with external communication, and (b), partial localization to achieve higher throughput and smaller latencies. Furthermore, our filter generator allows for design space exploration to tackle trade-offs in cost and speed. Finally, synthesizable VHDL code is generated and mapped to an FPGA, the results are compared with a commercial filter generator. © Springer-Verlag Berlin Heidelberg 2005.
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.automa_0

Automatic generation of system-level virtual prototypes from streaming application models - Kutzer, Philip; Gladigau, Jens; Haubelt, Christian; Teich, Jürgen (Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011)
Virtual prototyping is a more and more accepted technology to enable early software development in the design flow of embedded systems. Since virtual prototypes are typically constructed manually, their value during design space exploration is limited. On the other hand, system synthesis approaches often start from abstract and executable models, allowing for fast design space exploration, considering only predefined design decisions. Usually, the output of these approaches is an ad hoc implementation, which is hard to reuse in further refinement steps. In this paper, we propose a methodology for automatic generation of heterogeneous MPSoC virtual prototypes starting with models for streaming applications. The advantage of the proposed approach lies in the fact that it is open to subsequent design steps. The applicability of the proposed approach to real-world applications is demonstrated using a Motion JPEG decoder application that is automatically refined into several virtual prototypes within seconds, which are correct by construction, instead of using error-prone manual refinement, which typically requires several days. © 2011 IEEE.

Automatic Graph-based Success Tree Construction and Analysis - Aliee, Hananeh; Glaß, Michael; Wanka, Rolf; Teich, Jürgen (Proc. 60th Annual Reliability and Maintainability Symposium (RAMS), 2014)
This paper presents a graph-based representation of success trees to evaluate the reliability of an embedded system. First, a success tree is constructed by deriving a characteristic function from a graph-based system model automatically. The constructed success tree is then translated to a graph (called a success graph) which supports both cyclic and acyclic data dependencies in applications to be mapped to the system resources and analyzed for reliability. To analyze the success graph, an algorithm called 0-propagation is introduced which propagates errors through the graph. The system fails if the errors propagate to the output of the success graph. Experimental results show that the proposed technique can simply and efficiently construct and analyze success trees of real-life embedded systems in a short time with negligible inaccuracy which suits well for evaluating the reliability of complex systems, e. g., as part of a design space exploration. © 2014 IEEE.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.infalg._autom
Keywords: design space exploration; fault tree; permanent fault; stochastic logic; Success tree; transient fault

Automatic Kernel Fusion for Image Processing DSLs - Qiao, Bo; Reiche, Oliver; Hannig, Frank; Teich, Jürgen (Proceedings of the 21th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2018)
Programming image processing algorithms on hardware accelerators such as graphics processing units (GPUs) often exhibits a trade-off between software portability and performance portability. Domain-specific languages (DSLs) have proven to be a promising remedy, which enable optimizations and generation of efficient code from a concise, high-level algorithm representation. The scope of this paper is an optimization framework for image processing DSLs in the form of a source-to-source compiler. To cope with the inter-kernel communication bound via global memory for GPU applications, kernel fusion is investigated as a primary optimization technique to improve temporal locality. In order to enable automatic kernel fusion, we analyze the fusibility of each kernel in the algorithm, in terms of data dependencies, resource utilization, and parallelism granularity. By combining the obtained information with the domain-specific knowledge captured in the DSL, a method to automatically fuse the suitable kernels is proposed and integrated into an open source DSL framework. The novel kernel fusion technique is evaluated on two filter-based image processing applications, for which speedups of up to 1.60 are obtained for an NVIDIA Geforce 745 graphics card target.
Keywords: Domain-specific Languages; Image Processing; Kernel Fusion

Automatic Operating Point Distillation for Hybrid Mapping Methodologies - Pourmohseni, Behnaz; Glaß, Michael; Teich, Jürgen (Proceedings of the 20th Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017)
Keywords: Operating point distillation; hybrid application mapping; design space exploration; run-time management; heterogeneous many-core systems

Automatic Optimization of Hardware Accelerators for Image Processing - Reiche, Oliver; Häublein, Konrad; Reichenbach, Marc; Hannig, Frank; Teich, Jürgen; Fey, Dietmar (Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015), 2015)
In the domain of image processing, often real-time constraints are required. In particular, in safety-critical applications, such as X-ray computed tomography in medical imaging or advanced driver assistance systems in the automotive domain, timing is of utmost importance. A common approach to maintain real-time capabilities of compute-intensive applications is to offload those computations to dedicated accelerator hardware, such as Field Programmable Gate Arrays (FPGAs). Programming such architectures is a challenging task, with respect to the typical FPGA-specific design criteria: Achievable overall algorithm latency and resource usage of FPGA primitives (BRAM, FF, LUT, and DSP). High-Level Synthesis (HLS) dramatically simplifies this task by enabling the description of algorithms in well-known higher languages (C/C++) and its automatic synthesis that can be accomplished by HLS tools. However, algorithm developers still need expert knowledge about the target architecture, in order to achieve satisfying results. Therefore, in previous work, we have shown that elevating the description of image algorithms to an even higher abstraction level, by using a Domain-Specific Language (DSL), can significantly cut down the complexity for designing such algorithms for FPGAs. To give the developer even more control over the common trade-off, latency vs. resource usage, we will present an automatic optimization process where these criteria are analyzed and fed back to the DSL compiler, in order to generate code that is closer to the desired design specifications. Finally, we generate code for stereo block matching algorithms and compare it with hand
UnivIS-Import:2015-04-17:Pub.2015.tech.IMMD.IMMD3._autom
Keywords: GRK-1773

Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging - Membarth, Richard; Hannig, Frank; Teich, Jürgen; Körner, Mario; Eckert, Wieland (Proc. of the 11th International Symposium on Parallel and Distributed Computing (ISPDC), 2012)
An efficient memory bandwidth utilization for GPU accelerators is crucial for memory bound applications. In medical imaging, the performance of many kernels is limited by the available memory bandwidth since only a few operations are performed per pixel. For such kernels only a fraction of the compute power provided by GPU accelerators can be exploited and performance is predetermined by memory bandwidth. As a remedy, this paper investigates the optimal utilization of available memory bandwidth by means of increasing in-flight memory transactions. Instead of doing this manually for different GPU accelerators, the required CUDA and OpenCL code is automatically generated from descriptions in a Domain-Specific Language (DSL) for the considered application domain. Moreover, the DSL is extended to also support global reduction operators. We show that the generated target-specific code improves bandwidth utilization for memory-bound kernels significantly. Moreover, competitive performance compared to the GPU back end of the widely used image processing library OpenCV can be achieved. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.automa
Keywords: code generation; CUDA; domain-specific language; global operators; GPU; medical imaging; memory bandwidth utilization; OpenCL; reductions

Automatic Optimization of Redundant Message Routings in Automotive Networks - Smirnov, Fedor; Reimann, Felix; Teich, Jürgen; Han, Zhao; Glaß, Michael (Proceedings of 21st International Workshop on Software and Compilers for Embedded Systems (SCOPES 2018), 2018)
To cope with the strict reliability requirements of safety-critical ADAS applications, the upcoming TSN standard introduces mechanisms that enable transmission redundancy at any switch or end node. However, it is up to the designer to decide at which points and for which messages to activate transmission redundancy. This significantly increases the design space and requires to trade-off reliability with other routing-related design objectives like network load, transmission timing, or the monetary cost of the hardware. As a remedy, this paper a) presents two different exact approaches to generate feasible redundant message routings and b) proposes an extension of the state-of-the-art approach for the multi-objective routing optimization, enabling the optimizer to directly adjust system features that are relevant for the design objectives. A case study with an application from the automotive domain compares the optimization capabilities of the presented approaches for the routing generation and demonstrates the significant gain in optimization power that is achieved with the proposed optimization extension.
Keywords: Design Space Exploration; Network Optimization; Automotive Ethernet

Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks - Smirnov, Fedor; Reimann, Felix; Teich, Jürgen; Glaß, Michael (ACM Transactions on Design Automation of Electronic Systems, 2018)
Dividing the communication network into so-called Virtual Local Area Networks (VLANs), i.e., subnetworks that are isolated at the data link layer (OSI layer 2), is a promising approach to address the increasing security challenges in automotive networks. The automation of the VLAN partitioning is a well-researched problem in the domain of local or metropolitan area networks. However, the approaches used there are hardly applicable for the design of automotive networks as they mainly focus on reducing the amount of broadcast traffic and cannot capture the many design objectives of automotive networks like the message timing or the link load, which are affected by the VLAN partitioning. As a remedy, this article proposes an approach based on a set of Pseudo-Boolean constraints to generate a message routing which is feasible with respect to the VLAN-related routing restrictions in automotive networks. This approach can be used for a design space exploration to optimize not only the VLAN partitioning but also other routing-related objectives. We demonstrate both the efficiency of our message routing approach and the now accessible optimization potential for the complete Electric/Electronic architecture with a mixed-criticality system from the automotive domain. There we thoroughly investigate the impact of the VLAN partitioning on the message timing and the link loads by optimizing these design objectives concurrently. During the exploration of the huge design space, where each resource can be assigned to one of 4 VLANs, our approach requires less than 40 milliseconds for the creation of a valid solution and ensures that all messages satisfy their deadlines and link load bounds.<br
Keywords: Packet-switching networks; Automotive Ethernet; Design Automation; Virtual Local Area Networks

Automatic Reliability Analysis in the Presence of Probabilistic Common Cause Failures - Khosravi, Faramarz; Glaß, Michael; Teich, Jürgen (IEEE Transactions on Reliability, 2017)
Common cause failures (CCFs) are simultaneous failures of multiple components in a system and must be considered for accurate and realistic reliability analysis. Traditional CCF analysis techniques typically assume deterministic failures of the affected components. However, CCFs are usually probabilistic, i.e., when a common cause occurs, the affected components fail with different probabilities. Existing techniques that consider probabilistic CCFs (PCCFs) introduce significant execution time and memory overheads to the underlying reliability analysis—limiting their application to small systems only. This paper proposes a fast and automatic PCCF analysis that is based on i) deriving the mutually exclusive success paths of the system using binary decision diagrams (BDDs), and ii) analyzing each path considering PCCFs using explicit and implicit methods. Moreover, an alternative stochastic logic-based technique is presented that compromises analysis accuracy for execution time, and can be used when BDD-based techniques are prohibitive due to their memory overheads. Experimental results show that compared to the state of the art, our methods calculate the system's reliability between 1.1x  and 43.4x faster while requiring up to 99.94 % less memory.
Keywords: Binary decision diagrams; probabilistic common cause failures; reliability analysis; stochastic logic

Automatic Success Tree-Based Reliability Analysis for the Consideration of Transient and Permanent Faults - Aliee, Hananeh; Glaß, Michael; Reimann, Felix; Teich, Jürgen (Proc. Design, Automation and Test in Europe, 2013)
Success tree analysis is a well-known method to quantify the dependability features of many systems. This paper presents a system-level methodology to automatically generate a success tree from a given embedded system implementation and subsequently analyzes its reliability based on a state-of-the-art Monte Carlo simulation. This enables the efficient analysis of transient as well as permanent faults while considering methods such as task and resource redundancy to compensate these. As a case study, the proposed technique is compared with two analysis techniques, successfully applied at system level: (1) a BDD-based reliability analysis technique and (2) a SAT-assisted approach, both suffering from exponential complexity in either space or time. Experimental results performed on an extensive test suite show that: (a) Opposed to the Success Tree (ST) and SAT-assisted approaches, the BDD-based approach is highly vulnerable to exhaust available memory during its construction for moderate and large test cases. (b) The proposed ST technique is competitive to the SAT-assisted analysis in analysis speed and accuracy, while being the only technique that is suitable to also handle large and complex system implementations in which permanent and transient faults may occur concurrently. © 2013 EDAA.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.automa

Automatic Synthesis of Design Alternatives for Fast Stream-Based Out-of-Order Communication - Keinert, Joachim; Haubelt, Christian; Teich, Jürgen (Proceedings of the 2008 IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, (VLSI-SoC 2008), 2008)

Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms - Teich, Jürgen; Bednara, Marcus (Journal of Supercomputing, 2003)
We consider the problem of automatic mapping of computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there exists no continuous design flow that allows automated generation of FPGA configuration data from a loop nest specified in a high level language. Here, we present a methodology for automatic generation of synthesizable VHDL code specifying a processor array and optimized for FPGA implementation.
UnivIS-Import:2015-03-09:Pub.2003.tech.IMMD.inform.automa
Keywords: Design automation; FPGA; Regular processor arrays; Space-time mapping

Automatic Synthesis of FSMs for Enforcing Non-Functional Requirements on MPSoCs Using Multi-Objective Evolutionary Algorithms - Esper, Khalil; Wildermann, Stefan; Teich, Jürgen (ACM Transactions on Design Automation of Electronic Systems, 2023)
Embedded system applications often require guarantees regarding non-functional properties when executed on a given MPSoC platform. Examples of such requirements include real-time, energy or safety properties on corresponding programs. One option to implement the enforcement of such requirements is by a reactive control loop, where an enforcer decides based on a system response (feedback) how to control the system, e.g., by adapting the number of cores allocated to a program or by scaling the voltage/frequency mode of involved processors. Typically, a violation of a requirement must either never happen in case of strict enforcement, or only happen temporally (in case of so-called loose enforcement). However, it is a challenge to design enforcers for which it is possible to give formal guarantees with respect to requirements, especially in the presence of typically largely varying environmental input (workload) per execution. Technically, an enforcement strategy can be formally modeled by a finite state machine (FSM) and the uncertain environment determining the workload by a discrete-time Markov chain. It has been shown in previous work that this formalization allows the formal verification of temporal properties (verification goals) regarding the fulfillment of requirements for a given enforcement strategy. In this paper, we consider the so far unsolved problem of design space exploration and automatic synthesis of enforcement automata that maximize a number of deterministic and probabilistic verification goals formulated on a given set of non-functional requirements. For the design space exploration (DSE), an approach based on multi-objective evolutionary algorithms is proposed in which enforcement automata are encoded as genes of states and state transition conditions. For each individual, the verification goals are evaluated using probabilistic model checking. At the end, the DSE returns a set of efficient FSMs in terms of probabilities of meeting given requirements. As experimental results, we present three use cases while considering requirements on latency and energy consumption.
Keywords: Finite State Machine; Genetic Algorithm; Probabilistic Model Cheking; Design Space Exploration; Verification; Runtime Requirement Enforcement; Optimization; Enforcement FSM; MPSoC; Steady State; Evolutionary Algorithm; PCTL; Markov Chain

Automatic System-Level Synthesis: From Formal Application Models to Generic Bus-Based MPSoCs - Gladigau, Jens; Gerstlauer, Andreas; Haubelt, Christian; Streubühr, Martin; Teich, Jürgen (LNCS Transactions on High-Performance Embedded Architectures and Compilers, 2011)

Automatic Test Case Generation with Model Checker NuSMV - Bunin, Gregor; Schneider, Axel; Haubelt, Christian; Langer, Jan; Heinkel, Ulrich (Proceedings of the Informatik 2006 - Workshop Modellbasiertes Testen, 2006)

Automatic Test Generation with Model Checking Techniques - Schneider, Axel; Bunin, Gregor; Haubelt, Christian; Heinkel, Ulrich (Software Quality in Service-Oriented Architectures Proceedings of the Conference on Quality Engineering in Software Technology (CONQUEST2006), 2006)

Automating the Development of High-Performance Multigrid Solvers - Schmitt, Christian; Kronawitter, Stefan; Hannig, Frank; Teich, Jürgen; Lengauer, Christian (Proceedings of the IEEE, 2018)
The purpose of a domain-specific language (DSL) is to enable the application programmer to specify a problem, or an abstract algorithm description, in his/her domain of expertise without being burdened by implementation details. The ideal scenario is that the implementation detail is added in an automatic process of program translation and code generation. The approach of domain-specific program generation has lately received increasing attention in the area of computational science and engineering. We introduce the new code generation framework Athariac. Its goal is to support the quick implementation of a language processing and program optimization platform for a given DSL based on stepwise term-rewriting. We demonstrate the framework's use on our DSL ExaSlang for the specification and optimization of multigrid solvers. On this example, we provide evidence of Athariac's potential for making domain-specific software engineering more productiv
Keywords: ExaStencils; ExaSlang; DSL; Domain-Specific Languages; Code Generation; Program Transformation; Compiler

Automation Approaches for the Application of Side-Channel Analysis in Real-World Scenarios - Trautmann, Jens (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2023)

Automatische Verification von ADeVA-Spezifikationen - Dinkel, Thomas; Haubelt, Christian; Heinkel, Ulrich; Schlichter, Thomas; Teich, Jürgen (Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2005)

Autonomic MPSoCs for Reliable Systems - Stechele, Walter; Bringmann, Oliver; Ernst, Rolf; Herkersdorf, Andreas; Hojenski, Katharina; Janacik, Peter; Rammig, Franz; Teich, Jürgen; Wehn, Norbert; Zeppenfeld, Johannes; Ziener, Daniel (Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), 2007)
UnivIS-Import:2015-04-16:Pub.2007.tech.IMMD.inform.autono

Auto-Tuning of Raw Filters for FPGAs - Hahn, Tobias; Wildermann, Stefan; Teich, Jürgen (IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications, 2022)
Many Big Data applications include the processing of data streams on semi-structured data formats such as JSON. A disadvantage of these formats, however, is that applications may require a significant portion of their processing time to unselectively parse all data. As a remedy, so-called raw filters have been introduced in the past, aiming to reduce the data load before the costly parsing stage. Since filtering unparsed data can also become very costly, raw filters can be designed to filter data approximately, in the sense that they allow false positives to occur, in order to be implemented efficiently. While previously proposed CPU-based solutions are restricted to just string filtering, FPGA approaches have recently been proposed with much more expressive raw filters, allowing also to capture numbers and structural relationships. Yet, as a consequence of the variety of filter possibilities as well as the limited amount of resources available on FPGAs, the selection of optimal filters before their deployment has been identified as a complex problem resulting in the potential need to select less expressive filters in order to consume fewer resources. Many Big Data applications (e.g., stream processing) operate on incoming real-time data over long, potentially unlimited time periods. As a consequence, the conditions for which such a filter is optimized can change over time after its deployment. In this realm, this paper presents a new methodology which automatically adapts the hardware accelerator for raw filtering by means of dynamic hardware reconfiguration. Data is sampled on-the-fly during operation and used by an optimizer-in-the-loop to select and generate a raw filter with optimized selectivity for these data samples. As the optimizer has to take into account the resource costs of the hardware accelerator, we introduce models to estimate the resource costs in order to avoid performing a full synthesis. The filter selection problem can thus be solved within a few minutes with results close to the accurate resource cost estimation. If the selectivity of a query changes over time, such as seasonal differences in the analysis of IoT data, the system can auto-tune its filter to adapt to the situation. Depending on the query and the variability of inherent data changes, significant improvements in the amount of filtered data are presented, resulting in a significant parsing speedup in comparison to a state-of-the-art non-adaptive approach.
Keywords: Raw Filtering; Auto-Tuning; Self-Evolution; JSON; FPGA; HW/SW-Co-Design

Auto-vectorization for Image Processing DSLs - Reiche, Oliver; Kobylko, C.; Hannig, Frank; Teich, Jürgen (Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES), 2017)
The parallelization of programs and distributing their workloads to multiple threads can be a challenging task. In addition to multi-threading, harnessing vector units in CPUs proves highly desirable. However, employing vector units to speed up programs can be quite tedious. Either a program developer solely relies on the auto-vectorization capabilities of the compiler or he manually applies vector intrinsics, which is extremely error-prone, difficult to maintain, and not portable at all. Based on whole-function vectorization, a method to replace control flow with data flow, we propose auto-vectorization techniques for image processing DSLs in the context of source-to-source compilation. The approach does not require the input to be available in SSA form. Moreover, we formulate constraints under which the vectorization analysis and code transformations may be greatly simplified in the context of image processing DSLs. As part of our methodology, we present control flow to data flow transformation as a source-to-source translation. Moreover, we propose a method to efficiently analyze algorithms with mixed bit-width data types to determine the optimal SIMD width, independently of the target instruction set. The techniques are integrated into an open source DSL framework. Subsequently, the vectorization capabilities are compared to a variety of existing state-of-the-art C/C++ compilers. A geometric mean speedup of up to 3.14 is observed for benchmarks taken from ISPC and image processing, compared to non-vectorized executions.
Keywords: Domain-Specific Languages; Vectorization; Image Processing

A very fast and quasi-accurate power-state-based system-level power modeling methodology - Xu, Yang; Rosales, Rafael; Wang, Bo; Streubühr, Martin; Hasholzner, Ralph; Haubelt, Christian; Teich, Jürgen (Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 2012)
In this paper, we propose a novel system-level power modeling methodology that allows for very fast joint power-performance evaluation at specification phase. This methodology adopts approximately-timed task-accurate performance models and augments them with power-state-based power models to enable efficient simulation. A flexible method is also proposed to model complex dynamic power management policies so that their effects can be evaluated. We validate the accuracy of our methodology by comparing simulation results with measurements on a real mobile phone platform. Experimental results show that the simulated power profile matches very well with the measurements and it only takes about 100 ms to simulate a 20 ms GSM paging burst use case. © 2012 Springer-Verlag.

Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs - Fickenscher, Jörg; Hannig, Frank; Teich, Jürgen; Bouzouraa, Mohammed Essayed (4th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS), 2018)

Basic OS Support for Distributed Reconfigurable Hardware - Haubelt, Christian; Koch, Dirk; Teich, Jürgen (Proceedings of the Third International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'03), 2003)

Basic OS support for distributed reconfigurable hardware - Haubelt, Christian; Koch, Dirk; Teich, Jürgen (Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), 2004)
While recent research is mainly focused on the OS support for a single reconfigurable node, this paper presents a general approach to manage distributed reconfigurable hardware. The most outstanding properties of these systems are the ability of reconfiguration, hardware task migration, and fault tolerance. This paper presents first ideas of an operating system (OS) for such architectures. Furthermore, a prototype implementation consisting of four fully connected FPGAs will be presented. © Springer-Verlag Berlin Heidelberg 2004.

Basics of Invasive Computing - Teich, Jürgen; Esper, Khalil; Falk, Joachim; Pourmohseni, Behnaz; Schwarzer, Tobias; Wildermann, Stefan (Invasive Computing, 2022)

BDD-based Error Metric Analysis, Computation and Optimization - Keszöcze, Oliver (IEEE Access, 2022)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. Computing the error of the approximated design is an essential step to determine its quality. The computation time for determining the error can become very large, effectively rendering the entire logic approximation procedure infeasible. In this work we extensively analyze various error metrics and approximation operations.We present methods to accelerate the computation of error metric computations by (a) exploiting structural information of the function obtained by applying the analyzed operations and (b) computing estimates of the metrics for multi-output Boolean functions represented as Binary Decision Diagrams (BDDs). We further present a novel greedy, bucket-based BDD minimization framework employing the newly proposed error metric computations to produce Pareto-optimal solutions with respect to BDD size and multiple error metrics. The applicability of the proposed minimization framework is demonstrated by an experimental evaluation. We can report considerable speedups while, at the same time, creating high-quality approximated BDDs. The presented framework is publicly available as open-source software on GitHu
CRIS-Team Scopus Importer:2022-01-21
Keywords: Approximate Computing; BDD Minimization; Design Space Exploration; Error Metrics; Logic Minimization; Multi-Objective Optimization

Big Data and HPC Acceleration with Vivado HLS - Schmid, Moritz; Schmitt, Christian; Hannig, Frank; Malazgirt, Gorker Alp; Sönmez, Nehir; Yurdakul, Arda; Cristal, Adrián (FPGAs for Software Programmers, 2016)

Bitonic Sorting on Dynamically Reconfigurable Architectures - Angermeier, Josef; Sibirko, Eugen; Wanka, Rolf; Teich, Jürgen (Proc. IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011)
Sorting is one of the most investigated tasks computers are used for. Up to now, not much research has been put into increasing the flexibility and performance of sorting applications by applying reconfigurable computer systems. There are parallel sorting algorithms (sorting circuits) which are highly suitable for VLSI hardware realization and which outperform sequential sorting methods applied on traditional software processors by far. But usually they require a large area that increases with the number of keys to be sorted. This drawback concerns ASIC and statically reconfigurable systems. In this paper, we present a way to adopt the well-known Bitonic sorting method to dynamically reconfigurable systems such that this drawback is overcome. We present a detailed description of the design and actual implementation, and we present experimental results of our approach to show its benefits in performance and the trade-offs of our approach. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.infalg._biton

Bitstream Decompression for High Speed FPGA Configuration from Slow Memories - Koch, Dirk; Beckhoff, Christian; Teich, Jürgen (Proc. of the IEEE International Conference on Field-Programmable Technology 2007, 2007)
In this paper, we present hardware decompression accelerators for bridging the gap between high speed FPGA configuration interfaces and slow configuration memories. We discuss different compression algorithms suitable for a decompression on FPGAs as well as on CPLDs with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations with one capable to decompress at high data rates of up to 400 megabytes per second while only requiring slightly more than a hundred look-up tables. Furthermore, we present a sophisticated configuration bitstream benchmark. © 2007 IEEE.
UnivIS-Import:2015-04-16:Pub.2007.tech.IMMD.inform.bitstr

Boundary control: A new distributed control architecture for space-time transformed (VLSI) processor arrays - Bednara, Marcus; Hannig, Frank; Teich, Jürgen (Proc. 35th IEEE Asilomar Conf. on Signals, Systems and Computers, 2001)
We present a new methodology for controlling the space-time behavior of VLSI and FPGA-based processor arrays. The main idea is to generate simple local control elements which take control over the activeness of each attached processor element. Each control element thereby propagates a "start" and a "stop execution" signal to its neighbors. We show that our control mechanism is much more efficient than existing approaches such as [10, 17] because 1) only two control signals (start/stop) are required, 2) no extension of the computation space is necessary. 3) By the local propagation of just one start/stop signal, energy is saved as processing elements are only active between the time they have received the start signal and the time they have received the stop signal. Our methodology is applicable to one- and multi-dimensional processor arrays and is based on local control signal propagation. We provide a theoretical analysis of the overhead caused by the control structure.
Keywords: Control; FPGA; Hardware mapping; Processor arrays