Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study - Sousa, Éricles; Witterauf, Michael; Brand, Marcel; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018)

Invasive computing for predictable stream processing: A simulation-based case study - Roloff, Sascha; Wildermann, Stefan; Hannig, Frank; Teich, Jürgen (13th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2015, 2015)
Heterogeneous many-core systems enable the integration of more and more applications into a single system. Executing multiple applications in the same system inevitably leads to resource sharing, e.g., when accessing on-chip communication and memory. This poses a challenge when applications are expected to guarantee user requirements regarding timing, reliability, security, etc. In this paper, we review a design methodology that (a) allows an application designer to model a stream processing application and user requirements, and then (b) automatically generates a set of resource requirements that guarantee the fulfillment of these user requirements. Techniques from the Invasive Computing paradigm enable the program-driven dynamic reservation of resources according to these generated resource requirements.We demonstrate that this provides means for predictable execution of stream processing applications by evaluating a simulation-based case stud
Keywords: Computer architecture; Design methodology; Jitter; Object detection; Prediction algorithms; Throughput; Timing

Invasive Computing for Timing-Predictable Stream Processing on MPSoCs - Wildermann, Stefan; Bader, Michael; Bauer, Lars; Damschen, Marvin; Gabriel, Dirk; Gerndt, Michael; Glaß, Michael; Henkel, Jörg; Paul, Johny; Pöppl, Alexander; Roloff, Sascha; Schwarzer, Tobias; et al. (it - Information Technology, 2016)

Invasive Manycore Architectures - Henkel, Jörg; Herkersdorf, Andreas; Bauer, Lars; Wild, Thomas; Hübner, Michael; Pujari, Ravi Kumar; Grudnitsky, Artjom; Heisswolf, Jan; Zaib, Aurang; Vogel, Benjamin; Lari, Vahid; Kobbe, Sebastian (Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012)
This paper introduces a scalable hardware and software platform applicable for demonstrating the benefits of the invasive computing paradigm. The hardware architecture consists of a heterogeneous, tile-based manycore structure while the software architecture comprises a multi-agent management layer underpinned by distributed runtime and OS services. The necessity for invasive-specific hardware assist functions is analytically shown and their integration into the overall manycore environment is described. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.invasi
Keywords: invasive computing; manycore architectures; multiprocessor system on a chip; networks on chip; reconfigurable adaptive processors; resource aware programming

Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach - Hannig, Frank; Lari, Vahid; Boppu, Srinivas; Tanase, Alexandru-Petru; Reiche, Oliver (ACM Transactions on Embedded Computing Systems, 2014)
We introduce a novel class of massively parallel processor architectures called invasive Tightly-Coupled Processor Arrays (TCPAs). The presented processor class is a highly parameterizable template which can be tailored before runtime to fulfill costumers' requirements such as performance, area cost, and energy efficiency. These programmable accelerators are well suited for domain-specific computing from the areas of signal, image, and video processing as well as other streaming processing applications. To overcome future scaling issues (e.g., power consumption, reliability, resource management, as well as application parallelization and mapping), TCPAs are inherently designed in way that they support self-adaptivity and resource awareness at hardware level. Here, we follow a recently introduced resource-aware parallel computing paradigm called invasive computing where an application can dynamically claim, execute, and release the resources. Furthermore, we show how invasive computing can be used as an enabler for power management. For the first time, we present a seamless mapping flow for TCPAs, based on a domain-specific language. Moreover, we outline a complete symbolic mapping approach. Finally, we support our claims by comparing a TCPA against an ARM Mali-T604 GPU in terms of performance and energy efficiency. © 2014 ACM.
UnivIS-Import:2015-03-09:Pub.2014.tech.IMMD.inform.invasi
Keywords: Code generation; Energy efficiency; Performance; Processor arrays

Invasive Tightly Coupled Processor Arrays - Lari, Vahid (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2015)

Invasive Tightly-Coupled Processor Arrays - Teich, Jürgen; Brand, Marcel; Hannig, Frank; Heidorn, Christian; Walter, Dominik; Witterauf, Michael (Invasive Computing, 2022)

Investigating the Impact of Energy-Efficient Ethernet on Automotive Applications via High-level Modeling - Graf, Sebastian; Glaß, Michael; Teich, Jürgen (Tagungsunterlagen Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.invest

IP-based System Design within the PARADISE Design Environment - Hardt, Wolfram; Rammig, Franz; Böke, Carsten; Stroop, Joachim; Rettberg, Achim; Kleinjohann, Bernd; Teich, Jürgen; et al. (Journal of Systems Architecture, 2000)

IP-Cores Watermarking Scheme at Behavioral Level Using Genetic Algorithms - Echavarria Gutiérrez, Jorge Alfonso; Morales-Reyes, Alicia; Cumplido, René; Salido, Miguel Ángel; Feregrino, Claudia (Engineering Applications of Artificial Intelligence, 2019)
This paper proposes an improved scheme to watermark soft Intellectual Property (IP) Cores using Genetic Algorithms (GAs). For this purpose, a water-mark signature and an IP-Core behavioral description are translated into FiniteState Machines (FSMs). Both FSMs are merged into one that contains the watermarked IP-Core preserving its original functionality without disruption. However, a key problem of the resulting FSM is dealing with not deeply embedded states that allow the watermark to be removed. In order to overcome this problem, an FSM reduction process is necessary. Both, FSMs merging and reduction are NP-complete problems that can be tackled via GAs. The proposed watermarking scheme shows a significant improvement in terms of reduction and watermark embedding strength.
Keywords: IP Cores; Finite State Machine; Watermarking; Genetic Algorithms

Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems - Pourmohseni, Behnaz; Smirnov, Fedor; Wildermann, Stefan; Teich, Jürgen (Proceedings of the 31th Euromicro Conference on Real-Time Systems (ECRTS), 2019)
Composable many-core systems enable the independent development and analysis of applications which will be executed on a shared platform where the mix of concurrently executed applications may change dynamically at run time. For each individual application, an off-line DSE is performed to compute several mapping alternatives on the platform, offering Pareto-optimal trade-offs in terms of real-time guarantees, resource usage, etc. At run time, one mapping is then chosen to launch the application on demand. In this context, to enable an independent analysis of each individual application at design time, so-called inter-application isolation schemes are applied which specify temporal/spatial isolation policies between applications. State-of-the-art composable many-core systems are developed based on a fixed isolation scheme that is exclusively applied to every resource in every mapping of every application and use a timing analysis tailored to that isolation scheme to derive timing guarantees for each mapping. A fixed isolation scheme, however, heavily restricts the explored space of solutions and can, therefore, lead to suboptimality. Lifting this restriction necessitates a timing analysis that is applicable to mappings with an arbitrary mix of isolation schemes on different resources. To address this issue, in this paper, we (a) present an isolation-aware timing analysis that - unlike existing analyses - can handle multiple isolation schemes in combination within one mapping and delivers safe yet tight timing bounds by identifying and excluding interference scenarios that can never happen under the given combination of isolation schemes. Based on the timing analysis, we (b) present a DSE which explores the choices of isolation scheme per resource within each mapping and uses the proposed timing analysis for timing verification. Experimental results demonstrate that, for a variety of real-time applications and many-core platforms, the proposed approach achieves an improvement of up to 67% in the quality of delivered mappings compared to approaches based on a fixed isolation scheme.
Keywords: Many-core systems; timing analysis; design space exploration (DSE); isolation scheme; predictability; composability

IVaM: Implicit Variant Modeling and Management for Automotive Embedded Systems - Graf, Sebastian; Glaß, Michael; Wintermann, Dominic; Teich, Jürgen; Lauer, Christoph (Proc. International Conference on Hardware/Software Codesign and System Synthesis, 2013)
In this paper, we propose a graph-based approach for the modeling and efficient analysis of functional variants of a car's electric and electronic (E/E) architecture functionality by combining local technical expert knowledge with global business knowledge. Starting with a variants system specification including a set of task graphs, linear constraints on binary variables are specified for their alternative selection as well as the selection of groups of alternatives called application groups. These constraints may stem from a certain domain knowledge, e. g., entertainment or power train domain, or global constraints. The typically vast space of resulting possible combinations of different selections of alternative behaviors will be termed variant space and those satisfying the set of formulated constraints valid variants. An important result of this paper is that the set of variants, and especially the set of valid variants, do not need to be modeled or stored explicitly but rather implicitly. Nevertheless do we show that using state-of-the-art PB solver techniques, we may determine the set of valid variants very efficiently. Each of these valid variants may subsequently be used as a candidate for design space exploration (DSE) in order to optimize also the mapping of the corresponding task graph functionalities to a final optimized E/E architecture. A real-world case study is provided to demonstrate the capabilities and efficiency of the presented approach on implicit variant modeling and analysis. © 2013 IEEE.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.ivamim

Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution using Invasive Computing - Teich, Jürgen; Glaß, Michael; Roloff, Sascha; Schröder-Preikschat, Wolfgang; Snelting, Gregor; Weichslgartner, Andreas; Wildermann, Stefan (Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), 2016)

Leviathan: SPL Support on Filesystem Level - Hofer, Wanja; Elsner, Christoph; Blendinger, Frank; Schröder-Preikschat, Wolfgang; Lohmann, Daniel (Proceedings of the 14th International Software Product Line Conference (SPLC-Poster 2010), 2010)
A lot of configurable software, especially in the domain of embedded and operating systems, is configured with a source preprocessor, mostly to avoid run-time overhead. However, developers then have to face a myriad of preprocessor directives and the corresponding complexity in the source code, even when they might only be working on the implementation of a single feature at a time. Thus, it has long been recognized that tool support is needed to cope with this '#ifdef hell'. Current approaches, which assist the software developer by providing preprocessed views, are all bound to a special integrated development environment. This eliminates them from being used both in industry settings (where domain-specific toolchains are often mandated) and in open-source projects (where diverse sets of editors and tools are being used). © 2010 Springer-Verlag Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.IMMD4.leviat
Keywords: Leviathan; Software Product Lines; Variability Implementation; Preprocessor-Based Configuration; Toolchain-Independent Variability Support; Filesystem Views; VAMOS

Lifetime Reliability Optimization for Embedded Systems: A System-Level Approach - Glaß, Michael; Lukasiewycz, Martin; Haubelt, Christian; Teich, Jürgen (Proceedings of IEEE International Workshop on Reliability Aware System Design and Test (RASDAT '10), 2010)

LION: Real-Time I/O Transfer Control for Massively Parallel Processor Arrays - Walter, Dominik; Teich, Jürgen (Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), 2021)
The performance of many accelerator architectures depends on the communication with external memory. During execution, new I/O data is continuously fetched forth and back to memory. This data exchange is very often performance-critical and a careful orchestration thus vital. To satisfy the I/O demand for accelerators of loop nests, it was shown that the individual reads and writes can be merged into larger blocks, which are subsequently transferred by a single DMA transfer. Furthermore, the order in which such DMA transfers must be issued, was shown to be reducible to a real-time task scheduling problem to be solved at run time. Rather than just concepts, we investigate in this paper the architecture and implementation of such a Loop I/O Controller (LION) for a class of CGRAs called TCPAs. Based on a novel heap-based priority queue approach, the proposed controller is able to issue every 6 cycles a new DMA request to a memory bus. Even on a simple FPGA prototype running at just 200 MHz, this allows for more than 33 million DMA requests to be issued per second. Since the execution time of a typical DMA request is in general at least one order of magnitude longer, we can conclude that this rate is sufficient to fully utilize a memory bus. In the evaluation of our architecture, we compare the proposed priority queue with various state-of-the-art approaches and conclude that our priority queue is not only cheaper, but also guaranteeing real-time constraints. Furthermore, we discuss many different optimizations for the Loop I/O Controller, which can reduce the area of the proposed architecture significantly. <br

Local Divergence of Markov Chains and the Analysis of Iterative Load-Balancing Schemes - Rabani, Yuval; Sinclair, Alistair; Wanka, Rolf (Proc. 39th IEEE Symposium on Foundations of Computer Science (FOCS), 1998)
We develop a general technique for the quantitative analysis of iterative distributed load balancing schemes. We illustrate the technique by studying two simple, intuitively appealing models that are prevalent in the literature: the diffusive paradigm, and periodic balancing circuits (or the dimension exchange paradigm). It is well known that such load balancing schemes can be roughly modeled by Markov chains, but also that this approximation can be quite inaccurate. Our main contribution is an effective way of characterizing the deviation between the actual loads and the distribution generated by a related Markov chain, in terms of a natural quantity which we call the local divergence. We apply this technique to obtain bounds on the number of rounds required to achieve coarse balancing in general networks, cycles and meshes in these models. For balancing circuits, we also present bounds for the stronger requirement of perfect balancing, or counting.

Look-Ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits - Wille, Robert; Keszocze, Oliver; Walter, Marcel; Rohrs, Patrick; Chattopadhyay, Anupam; Drechsler, Rolf (21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, 2016)

Loop Coarsening in C-based High-Level Synthesis - Schmid, Moritz; Reiche, Oliver; Hannig, Frank; Teich, Jürgen (Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2015)
Current tools for High-Level Synthesis (HLS) excel at exploiting Instruction-Level Parallelism (ILP), the support for Data-Level Parallelism (DLP), one of the key advantages of Field Programmable Gate Arrays (FPGAs), is in contrast very limited. This work examines the exploitation of DLP on FPGAs using code generation for C-based HLS of image filters and streaming pipelines, consisting of point and local operators. In addition to well known loop tiling techniques, we propose loop coarsening, which delivers superior performance and scalability. Loop tiling corresponds to splitting an image into separate regions, which are then processed in parallel by replicated accelerators. For data streaming, this also requires the generation of glue logic for the distribution of image data. Conversely, loop coarsening allows to process multiple pixels in parallel, whereby only the kernel operator is replicated within a single accelerator. We augment the FPGA back end of the heterogeneous Domain-Specific Language (DSL) framework HIPAcc by loop coarsening and compare the resulting FPGA accelerators to highly optimized software implementations for Graphics Processing Units (GPUs), all generated from the exact same code base. Moreover, we demonstrate the advantages of code generation for algorithm development by outlining how design space exploration enabled by HIPAcc can yield a more efficient implementation than handcoded VHDL.
UnivIS-Import:2015-11-17:Pub.2015.tech.IMMD.inform.loopco
Keywords: GRK-1773

LoopInvader: A Compiler for Tightly Coupled Processor Arrays - Tanase, Alexandru-Petru; Witterauf, Michael; Sousa, Éricles; Lari, Vahid; Hannig, Frank; Teich, Jürgen (Tool presentation at the University Booth, 2016)

Loop Parallelization Techniques for FPGA Accelerator Synthesis - Reiche, Oliver; Özkan, Mehmet Akif; Hannig, Frank; Teich, Jürgen; Schmid, Moritz (Journal of Signal Processing Systems, 2018)
Current tools for High-Level Synthesis (HLS) excel at exploiting Instruction-Level Parallelism (ILP). The support for Data-Level Parallelism (DLP), one of the key advantages of Field Programmable Gate Arrays (FPGAs), is in contrast very limited. This work examines the exploitation of DLP on FPGAs using code generation for C-based HLS of image filters and streaming pipelines. In addition to well-known loop tiling techniques, we propose loop coarsening, which delivers superior performance and scalability. Loop tiling corresponds to splitting an image into separate regions, which are then processed in parallel by replicated accelerators. For data streaming, this also requires the generation of glue logic for the distribution of image data. Conversely, loop coarsening allows processing multiple pixels in parallel, whereby only the kernel operator is replicated within a single accelerator. We present concrete implementations of tiling and coarsening for Vivado HLS and Altera OpenCL. Furthermore, we present a comparison of our implementations to the keyword-driven parallelization support provided by the Altera Offline Compiler. We augment the FPGA back end of the heterogeneous Domain-Specific Language (DSL) framework Hipacc to generate loop coarsening implementations for Vivado HLS and Altera OpenCL. Moreover, we compare the resulting FPGA accelerators to highly optimized software implementations for Graphics Processing Units (GPUs), all generated from exactly the same code bas
Keywords: Altera OpenCL; Vivado HLS; Vectorization; Loop coarsening; Loop tiling

Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators - Boppu, Srinivas; Hannig, Frank; Teich, Jürgen (Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, 2013)
We present a novel design methodology for the mapping of nested loops onto programmable hardware accelerators. Key features of our approach are: (1) Design entry in form of a functional programming language and loop parallelization in the polyhedron model, (2) the underlying accelerator architectures consist of lightweight, tightly-coupled, and programmable processor arrays, which can exploit both loop-level parallelism and instruction-level parallelism, (3) support of zero-overhead looping not only for inner most loops but also for arbitrarily nested loops. We implemented the proposed methodology in a prototype design tool and evaluated selected benchmarks by comparing our code generator with the Trimaran compilation framework. As the results show, our approach can reduce the size of the generated processor codes up to 64% while at the same time achieving a significant higher throughput. © 2013 IEEE.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.looppr

Low cost concurrent error detection for on-chip memory based embedded processors - Khosravi, Faramarz; Farbeh, Hamed; Fazeli, Mahdi; Miremadi, Seyed Ghassem (Proceedings of the 9th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2011), 2011)
This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions and generate signatures for the running program, and 2) an external watchdog processor to compare runtime signatures and branch addresses with the information extracted offline. The proposed method is implemented on an embedded processor core and is evaluated by a simulation based statistical fault injection approach where faults are injected into cache and main memory. Experimental results show that the proposed method detects more than 96.7% of all errors with only 2.6% overhead in area and less than 1% increase in power consumption. Furthermore, this technique imposes almost no performance degradation. © 2011 IEEE.
Keywords: Concurrent error detection methods; Control flow checking; Embedded processors; External watchdog processor

Maestro: A High Performance AES Encryption/Decryption System - Biglari, Mehrdad; Qasemi, Ehsan; Pourmohseni, Behnaz (Proceedings of the 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS), 2013)
High throughput AES encryption/decryption is a necessity for many of modern embedded systems. This article presents a high performance yet cost efficient AES system. Maestro can be used in a wide range of embedded applications with various requirements and limitations. Maestro is about one million times faster than the pure software implementation. The Maestro architecture is composed of two major components; the soft processor aimed at system initialization and control, and the hardware AES engine for high performance AES encryption/decryption. A ten stage implicit pipelined architecture is considered for the AES engine. Two novel techniques are proposed in design of AES engine which enable it to reach a throughput of 12.8 Gbps. First, tightly coupled encryption and round key generation units in encryption unit, and second, ahead of time round key generation in decryption unit. Altera DE2-115 development and educational FPGA board is used as the platform for Maestro. In the proposed architecture the DMA modules act as interfaces between data sources and data sinks by loading the input data into AES engine and taking encrypted and generated test data to target memories.
Keywords: Advanced Encryption Standard (AES); FPGA; FPGASoC; Throughput; Design Contest

MAESTRO - Holistic Actor-oriented Modeling of Non-Functional Properties and Firmware Behavior for MPSoCs - Rosales, Rafael; Glaß, Michael; Teich, Jürgen; Wang, Bo; Xu, Yang; Hasholzner, Ralph (ACM Transactions on Design Automation of Electronic Systems, 2014)
UnivIS-Import:2015-04-14:Pub.2014.tech.IMMD.inform.maestr

Mahler: Sketch-based Model-driven Virtual Prototyping - Rosales, Rafael; Glaß, Michael; Teich, Jürgen (Proc. of the 27th International Conference on Architecture of Computing Systems (ARCS), 2014)
Virtual prototyping and Electronic System Level (ESL) modeling have become valuable resources to cope with the ever-increasing complexity of embedded systems. Their effectiveness, however, is highly dependent on their quick development time and accuracy, both conflicting goals. In this paper, we present a novel tool, Mahler, to accelerate the development of ESL models. Mahler provides an early design phase playground to manually explore the modeling of functionality at a high level of abstraction and analyze its performance on different architecture implementations very fast. It generates a ready-to-execute source code functional model in an open source SystemC-based language, bridging the gap between a design's very preliminary stage and a more mature design stage that can serve as a starting point for automatic design space exploration on existing ESL design flows. Mahler achieves this through the most natural interface: the designer's pen, enabling an intuitive model-driven creation of virtual prototypes following the Y-chart approach; literally sketching actor-oriented functional models at the ESL which are then mapped to the architecture platform for a simulation-based evaluation of power and performance. We demonstrate its advantage in terms of improved design productivity through the implementation of an MPEG-4 encoder virtual prototype. © 2014 Springer International Publishing Switzerland.
UnivIS-Import:2015-04-20:Pub.2014.tech.IMMD.inform.mahler
Keywords: Energy Aware Design; ESL; Model-Driven Design; Simulation-based Performance and Power Consumption evaluation; Sketch-based User Interface; Virtual Prototyping Tool

MAML: An ADL for Designing Single and Multiprocessor Architectures - Kupriyanov, Olexiy; Hannig, Frank; Kissler, Dmitrij; Teich, Jürgen (Processor Description Languages, 2008)
This chapter focuses on machine markup language (MAML), an architecture description language (ADL) used for modeling and simulation of both single and multiprocessor architectures. It is based on XML, which allows the characterization of the resources of complex processor architectures at both structural and behavioral levels in a convenient manner. The MAML has its roots in designing application-specific instruction set processors and an MAML description contains a clearly arranged list of the architecture's resources such as functional units, pipeline stages, and register files; operation sets such as binding possibilities of operations to functional units and operand directions; communication structures such as buses and ports; and timing behavior such as latency of operations and behavior of multicycle operations. The extracted parameters are used for a fast interactive cycle-accurate simulation and for compiler retargeting. Finally, the processor architecture described within MAML is automatically synthesized for rapid prototyping. © 2008 Elsevier Inc. All rights reserved.

MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I - Kupriyanov, Olexiy; Hannig, Frank; Kissler, Dmitrij; Schaffer, Rainer; Teich, Jürgen (2006)

Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (International Journal of Embedded Systems, 2006)
UnivIS-Import:2015-03-09:Pub.2006.tech.IMMD.inform.mappin_3

Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays – Architectural Parameters and Methodology - Hannig, Frank; Dutta, Hritam; Teich, Jürgen (International Journal of Embedded Systems, 2006)
Existing compilation techniques for coarse-grained reconfigurable arrays are closely related to approaches from the DSP world. These approaches employ several loop transformations, like pipelining or temporal partitioning, but they are not able to exploit the full parallelism of a given algorithm and the computational potential of a typical 2-dimensional array. In this paper, - we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable arrays - we present our design methodology for mapping regular algorithms onto massively parallel arrays which is characterised by loop parallelisation in the polytope model - in a first case study, we adapt our design methodology for targeting reconfigurable arrays. The case study shows that the presented regular mapping methodology may lead to highly efficient implementations taking into account the constraints of the architectur
UnivIS-Import:2015-03-09:Pub.2004.tech.IMMD.inform.mappin_2

Mapping Actor-Oriented Models to TLM Architectures - Gladigau, Jens; Haubelt, Christian; Niemann, Bernardt; Teich, Jürgen (Proceedings FDL'07, Forum on specification and Design Languages 2007, 2008)

Mapping of Applications to MPSoCs - Marwedel, Peter; Teich, Jürgen; Kouveli, Georgia; Bacivarov, Iuliana; Thiele, Lothar; Ha, Soonhoi; Lee, Chanhee; Xu, Qiang; Huang, Lin (Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, part of ESWeek'11, 2011)
The advent of embedded many-core architectures results in the need to come up with techniques for mapping embedded applications onto such architectures. This paper presents a representative set of such techniques. The techniques focus on optimizing performance, temperature distribution, reliability and fault tolerance for various models. Copyright 2011 ACM.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.mappin
Keywords: Application mapping; Embedded systems; Multi-processor systems on a chip (mpsocs)

Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, 2006)
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.mappin

Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays – Constraints and Methodology - Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of the 18th International Parallel and Distributed Processing Symposium, 2004)
Apart from academic, recently more and more commercial coarse-grained reconfigurable arrays have been developed. Computational intensive applications from the area of video and wireless communication seek to exploit the computational power of such massively parallel SoCs. Conventionally, DSP processors are used in the digital signal processing domain. Thus, the existing compilation techniques are closely related to approaches from the DSP world. These approaches employ several loop transformations, like pipelining or temporal partitioning, but they are not able to exploit the full parallelism of a given algorithm and the computational potential of a typical 2-dimensional array. In this paper, (i) we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable arrays, (ii) we present our design methodology for mapping regular algorithms onto massively parallel arrays which is characterized by loop parallelization in the polytope model, and (iii), in a first case study, we adapt our design methodology for targeting reconfigurable arrays. The case study shows that the presented regular mapping methodology may lead to highly efficient implementations taking into account the constraints of the architecture.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.mappin

Massively Parallel Processor Architectures: A Co-design Approach - Dutta, Hritam; Hannig, Frank; Kupriyanov, Olexiy; Kissler, Dmitrij; Teich, Jürgen; Schaffer, Rainer; Siegel, Sebastian; Merker, Renate; Pottier, Bernard (Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC), 2007)

Massively Parallel Processor Architectures for Resource-aware Computing - Lari, Vahid; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Proc. of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), 2014)
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.massiv

Mastering Software Variant Explosion for GPU Accelerators - Membarth, Richard; Hannig, Frank; Teich, Jürgen; Körner, Mario; Eckert, Wieland (Proceedings of the 10th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), 2012)
UnivIS-Import:2015-04-20:Pub.2012.tech.IMMD.inform.master

Memory and Interface Architectures for Invasive Tightly Coupled Processor Arrays - Sousa, Éricles (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2018)

Memory-based meso-scale modeling of Covid-19 - Kergaßner, Andreas; Burkhardt, Christian; Lippold, Dorothee; Kergaßner, Matthias; Pflug, Lukas; Budday, Dominik; Steinmann, Paul; Budday, Silvia (Computational Mechanics, 2020)
The COVID-19 pandemic has lead to an unprecedented world-wide effort to gather data, model, and understand the viral spread. Entire societies and economies are desperate to recover and get back to normality. However, to this end accurate models are of essence that capture both the viral spread and the courses of disease in space and time at reasonable resolution. Here, we combine a spatially resolved county-level infection model for Germany with a memory-based integro-differential approach capable of directly including medical data on the course of disease, which is not possible when using traditional SIR-type models. We calibrate our model with data on cumulative detected infections and deaths from the Robert-Koch Institute and demonstrate how the model can be used to obtain county- or even city-level estimates on the number of new infections, hospitality rates and demands of intensive care units. We believe that the present work may help guide decision makers to locally fine-tune their expedient response to potential new outbreaks in the near future.<br

Memory mapped SPM: Protecting instruction scratchpad memory in embedded systems against soft errors - Farbeh, Hamed; Fazeli, Mahdi; Khosravi, Faramarz; Miremadi, Seyed Ghassem (Proceedings of the 9th European Dependable Computing Conference (EDCC 2012), 2012)
Predictability, energy consumption, area and reliability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories play an increasing role to satisfy these concerns. Both cache and SPM as on-chip SRAM memories are highly vulnerable to soft errors and as they contain the most frequently used blocks of the program, their errors can easily propagate in system leading to erroneous results. Unlike the instruction cache, an error in the instruction SPM cannot be corrected using only parity bits by invalidating the erroneous line. This study suggests a low-cost mechanism to protect the instruction SPM against soft errors. The main idea underlying the proposed mechanism includes four stages: 1) to use parity codes for error detection in the SPM, 2) to keep an address matching table in the main memory to store the address of the copy of SPM blocks in the main memory, in the case of dynamic SPM, 3) to allocate a specific segment of the main memory as an SPM backup, in the case of static SPM, and 4) to recover from errors using an interrupt service routine (ISR). Compared with a single error correction /double error detection (SEC-DED) scheme, by using a 2-bit interleaved-parity per word, the proposed mechanism can correct at least three bit errors, while SEC-DED is capable of correcting only single bit error and detecting 2-bit errors. The experimental results reveal that the energy consumption and area overheads of the proposed mechanism are approximately 22% and 15% less than that of SEC-DED for a 4Kbyte SPM, respectively. Moreover, this mechanism provides 10 times lower performance loss compared with SEC-DED. © 2012 IEEE.
Keywords: embedded processors; error correction; reliability; scratchpad memory; soft errors

Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen - Haubelt, Christian; Teich, Jürgen (Shaker Verlag, 2007)

Methods for Generating Response Ranges for Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs - Esper, Khalil; Wildermann, Stefan; Teich, Jürgen (Design, Automation and Test in Europe Conference, 2024)

microYOLO: Towards Single-Shot Object Detection on Microcontrollers - Deutel, Mark; Mutschler, Christopher; Teich, Jürgen (ITEM: IoT, Edge, and Mobile for Embedded Machine Learning, 2023)
This work-in-progress paper presents results on the feasibility of single-shot object detection on microcontrollers using YOLO. Single-shot object detectors like YOLO are widely used, however due to their complexity mainly on larger GPU-based platforms. We present microYOLO, which can be used on Cortex-M based microcontrollers, such as the OpenMV H7 R2, achieving about 3.5 FPS when classifying 128x128 RGB images while using less than 800 KB Flash and less than 350 KB RAM. Furthermore, we share experimental results for three different object detection tasks, analyzing the accuracy of microYOLO on them.<br
Keywords: TinyML; Microcontrollers; Object Detection

Migration Strategies for Ethernet-based E/E Architectures - Reimann, Felix; Glaß, Michael; Teich, Jürgen (Proc. Embedded World Conference, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.migrat

Minimal communication in massively parallel architectures - Teich, Jürgen; Thiele, Lothar; Zhang, L (Proc. of PARS Workshop 93, 1993)
UnivIS-Import:2015-04-16:Pub.1993.tech.IMMD.inform.minima

Minimizing communication cost for reconfigurable slot modules - Fekete, Sandor P.; Van Der Veen, Jan C.; Majer, Mateusz; Teich, Jürgen (Proceedings of 16th International Conference on Field Programmable Logic and Applications, 2006)
We discuss the problem of communication-aware module placement in array-like reconfigurable environments, such as the Erlangen Slot Machine (ESM). Bad placement of modules may degrade performance due to increased signal delays and wastes chip space for the reconfigurable multiple bus. We present integer linear programming (ILP) formulations that address both of these problems; both ILPs can be used stand-alone or as building blocks for more involved mathematical models. We validate our models by demonstrating their usefulness for a set of realistic benchmarks. © 2006 IEEE.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.minimi

Minimizing Internal Fragmentation by Fine-grained Two-dimensional Module Placement for Runtime Reconfigurable Systems - Koch, Dirk; Beckhoff, Christian; Teich, Jürgen (Proc. 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2009)
This paper analyzes fragmentation issues and proves that the reconfigurable area must be tiled much finer as has been done in existing approaches. The optimal tile grid can typically only be implemented by tiling the reconfigurable area into a two-dimensional grid. This will further increase the utilization of dedicated resources such as block RAMs. In order to provide communication with the reconfigurable modules, the novel ReCoBus communication architecture is enhanced for two-dimensional communication. A case study will demonstrate a system with 248 individual logic tiles that are each less than 200 LUTs in size while still being able of providing a module connection in each particular tile. © 2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.minimi

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning - Schmidt, Bernhard; Ziener, Daniel; Teich, Jürgen (Proc. of the Reconfigurable Architectures Workshop (RAW), 2014)
Existing techniques for SEU mitigation on FPGAs by scrubbing do not prevent permanent malfunction of a circuit design in case that the corresponding configuration bits do belong to feedback loops. In this paper, we a) provide a circuit analysis technique to distinguish so-called critical bits from essential bits to determine which parts of a bitstream will need also state-restoring actions after scrubbing and which not. Moreover, b) we will propose floorplanning techniques to reduce the effective number of frames that need to be scrubbed and c), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits may be reduced by up to 48.5% in comparison to a standard approach. For the MTTR calculation, we assume a system with checkpointing using the Xilinx SEM IP core to implement the scrubbing controller.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.minimi

Model-based actor multiplexing with application to complex communication protocols - Zebelein, Christian; Haubelt, Christian; Falk, Joachim; Schwarzer, Tobias; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE 2014), 2014)
We propose a dynamic scheduling approach for the concurrent execution of logical actor instances on a single synthesized actor instance. Based on a formal dataflow model of computation, the proposed approach can be applied to a wide range of applications in a model-based design flow. As case-study, we evaluate a bus-cycle-accurate SystemC RTL model based on an InfiniBand network adapter in a PCI Express system. © 2014 EDAA.

Model-based analysis, synthesis and testing of automotive hardware/software architectures - Chakraborty, Samarjit; Ramesh, S.; Teich, Jürgen (6th Embedded Systems Week 2010, ESWEEK 2010 - 10th ACM International Conference on Compilers, Architecture and Synthesis for Embedded Systems, EMSOFT'10, 2010)
This tutorial is concerned with various aspects of model-based design of hardware/software architectures of automotive systems. It will be split into three parts, the first dealing with model-based analysis of automotive ECU networks, the second with synthesis of schedules for such networks, and finally the third with model-based testing of such architectures.
Keywords: Automotive electronics; ECUs; Hardware/software co-design; Scheduling

Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs - Streit, Franz-Josef; Letras, Martin; Wildermann, Stefan; Hackenberg, Benjamin; Falk, Joachim; Becher, Andreas; Teich, Jürgen (IEEE Proceedings of the 13th International Conference on ReConFigurable Computing and FPGAs, 2018)
Shorter design cycles in FPGA-based Programmable System-on-Chips (PSoCs) development require a higher level of abstraction, which has led to a wide acceptance of model driven engineering. However, design and implementation of such heterogeneous PSoC platforms still desire a comprehensive expertise in hardware/software co-design. Therefore, to keep up with this trend, an automated systematic design flow that directly incorporates model simulation with High-Level Synthesis (HLS) for hybrid hardware and software implementations is necessary. In order to address this issue, the work at hand makes use of the modeling and simulation environment MATLAB/Simulink, a de facto standard in model-based development. Additionally, we present a novel design flow, which enables the assignment of functional tasks of a Simulink application to individual hardware/software solutions for Xilinx Zynq PSoCs. Thereby, the proposed method- ology enables control and system engineers to automatically explore different hardware and software implementation variants from a behavioral model. As a case study, we present a JPEG decoder application and investigate design objectives like resource costs and throughput to show the practicability of our approach.<br
Keywords: FPGA; SoC; Hardware/Software Co-Design; Model-Based Engineering

Model-Based Embedded System Design - Lukasiewycz, Martin (Proceedings of the 1st Chinese-German Summer School, 2006)
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.modelb

Model-Based Representation of Schedules for Dataflow Graphs - Zebelein, Christian; Haubelt, Christian; Falk, Joachim; Teich, Jürgen (Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2013), 2013)

Model-based synthesis and optimization of static multi-rate image processing algorithms - Keinert, Joachim; Dutta, Hritam; Hannig, Frank; Haubelt, Christian; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE 2009), 2009)
High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special purpose architectures in form of FPGAs or ASICs. However, their efficient implementation is still a challenge, as the design complexity causes exploding development times and costs. This paper presents a new design flow which permits to specify, analyze, and synthesize complex image processing algorithms. A novel buffer requirement analysis allows exploiting possible tradeoffs between required communication memory and computational logic for multi-rate applications. The derived schedule and buffer results are taken into account for resource optimized synthesis of the required hardware accelerators. Application to a multi-resolution filter shows that buffer analysis is possible in less than one second and that scheduling alternatives influence the required communication memory by up to 24% and the computational resources by up to 16%. © 2009 EDAA.

Model-Based Virtual Prototype Acceleration - Gladigau, Jens; Haubelt, Christian; Teich, Jürgen (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012)
Today, virtual prototypes are often employed for software development early in the design flow. There, high simulation speed may support fast development. So, the acceleration of virtual prototype simulation is important in the early phases of design. To accelerate virtual prototypes, complex prototype simulation can be prevented by exploiting model-specific knowledge. We replace complex event-driven interaction with execution of predefined traces. In particular, we show that, for many dataflow-dominated application models, such accelerating traces may be efficiently determined. Trace determination is based on a novel symbolic search technique. We show that virtual prototypes exploiting such traces may lead to a significant simulation time reduction. The benefits are quantified for the prototype of a SystemC/TLM network packet filter, where traces result in up to 30% simulation acceleration. © 2012 IEEE.
UnivIS-Import:2015-04-14:Pub.2012.tech.IMMD.inform.modelb
Keywords: Model-based design; simulation acceleration; symbolic techniques; SystemC; virtual prototype

Model-based Virtual Prototyping for Automotive Applications - Streubühr, Martin (Proceedings of the 3rd Chinese-German Summer School, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.modelb

Modeling, Analysis and Optimization of Automotive Networks - Lukasiewycz, Martin (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2010)

Modeling and Analysis of Distributed Reconfigurable Hardware - Haubelt, Christian; Teich, Jürgen (Proc Dresdener Arbeitstagung Schaltungs- und Systementwurf (DASS 2004), 2004)

Modeling and analysis of indirect communication in Particle Swarm Optimization - Helwig, Sabine; Haubelt, Christian; Teich, Jürgen (Proceedings of the 2005 IEEE Congress on Evolutionary Computation, 2005)
Particle Swarm Optimization (PSO) has successfully been applied to many optimization problems. One particularly interesting aspect of these algorithms is to study the communication behavior of the particles. Often, a neighborhood topology is defined a priori and used throughout the optimization run. However, the cost of communication between particles has not been analyzed up to now. In this paper, we will propose a novel algorithm called DAPSO (Distributed Archives PSO) that makes use of stationary archives to establish an indirect communication architecture in the swarms. Moreover, we provide analytical results of the required communication energy in such a scenario. This might be especially important in robot swarms and sensor networks. The applicability of our new methodology will be shown on some selected test cases. ©2005 IEEE.

Modeling and analysis of windowed synchronous algorithms - Keinert, Joachim; Haubelt, Christian; Teich, Jürgen (Proceedings of the 31st International Conference on Acoustics, Speech, and Signal Processing (ICASSP2006), 2006)
Sliding window algorithms are fundamental parts of each image processing system. Especially those belonging to the class of static algorithms offer various possibilities for analysis and optimization. Only if this potential is exploited, a high level synthesis of such algorithms will lead to efficient implementations. Such an analysis relies on an efficient representation by a well-defined model of computation. It must abstract important properties of sliding windows as for instance the relation between input and output data as well as the required buffer space. In this paper, a corresponding static model of computation for sliding window algorithms is elaborated, called Windowed Synchronous Data Flow (WSDF). Its main focus lies on applications with two or more dimensions. Furthermore, the WSDF balance equation is derived allowing to verify bounded token accumulation during execution. © 2006 IEEE.

Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems - Koch, Dirk; Streichert, Thilo; Teich, Jürgen; Haubelt, Christian (EURASIP Journal on Embedded Systems, 2006)
Automotive, avionic, or body-area networks are systems that consist of several communicating control units specialized for certain purposes. Typically, different constraints regarding fault tolerance, availability and also flexibility are imposed on these systems. In this article, we will present a novel framework for increasing fault tolerance and flexibility by solving the problem of hardware/software codesign online. Based on field-programmable gate arrays (FPGAs) in combination with CPUs, we allow migrating tasks implemented in hardware or software from one node to another. Moreover, if not enough hardware/software resources are available, the migration of functionality from hardware to software or vice versa is provided. Supporting such flexibility through services integrated in a distributed operating system for networked embedded systems is a substantial step towards self-adaptive systems. Beside the formal definition of methods and concepts, we describe in detail a first implementation of a reconfigurable networked embedded system running automotive applications.
UnivIS-Import:2015-04-14:Pub.2006.tech.IMMD.inform.modeli_9

Modeling and Efficient Simulation of Complex System-on-a-Chip Architectures - Kupriyanov, Olexiy (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2009)

Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model - Teich, Jürgen; Lee, Edward A.; Thiele, Lothar (Proc. of the 8th Int. Symposium on System Level Synthesis, 1995)
UnivIS-Import:2015-04-16:Pub.1995.tech.IMMD.inform.simula

Modeling and Simulation of IEEE 802.11g using OMNeT++ - Sarkar, Nurul; Membarth, Richard (Handbook of Research on Discrete Event Simulation Environments: Technologies and Applications, 2009)
Due to the complex nature of computer and telecommunication networks, it is often difficult to predict the impact of different parameters on system performance especially when deploying wireless networks. Computer simulation has become a popular methodology for performance study of computer and telecommunication networks. This popularity results from the availability of various sophisticated and powerful simulation software packages, and also because of the flexibility in model construction and validation offered by simulation. While various network simulators exist for building a variety of network models, choosing a good network simulator is very important in modeling and performance analysis of wireless networks. A good simulator is one that is easy to use; more flexible in model development, modification and validation; and incorporates appropriate analysis of simulation output data, pseudorandom number generators, and statistical accuracy of the simulation results. OMNeT++ is becoming one of the most popular network simulators because it has all the features of a good simulator. This chapter aims to provide a tutorial on OMNeT++ focusing on modeling and performance study of the IEEE 802.11g wireless network. © 2010, IGI Global.
UnivIS-Import:2015-04-20:Pub.2009.tech.IMMD.inform.modeli

Modeling and Simulation of Invasive Applications and Architectures - Roloff, Sascha (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2018)

Modeling and Simulation of Invasive Applications and Architectures - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Springer, 2019)

Modeling and Simulation of Invasive Applications and Architectures Conclusions and Future Directions - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Modeling and Simulation of Invasive Applications and Architectures, 2019)
CRIS-Team WoS Importer:2019-11-08

Modeling and synthesis of communication subsystems for loop accelerator pipelines - Dutta, Hritam; Hannig, Frank; Schmid, Moritz; Keinert, Joachim (Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), 2010)
The communication synthesis for data transfer and synchronization between loop accelerators is a major challenge in streaming applications. The complexity of the problem arises from the fact that optimal memory mapping and address generation in communication subsystems for parallel data access and out-of-order communication depend on tiling and scheduling choices. This paper solves the problem of communication synthesis by leveraging the windowed synchronous data flow (WSDF) model for communication synthesis. In this context, an intermediate representation of communicating loops in the polyhedral model and a unified methodology for their projection onto the WSDF model is proposed. Finally, we present the architecture template, synthesis methodology, and overhead of the communication primitive. © 2010 IEEE.

Modeling and synthesis of hardware-software morphing - Koch, Dirk; Haubelt, Christian; Streichert, Thilo; Teich, Jürgen (Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007)
In state of the art hardware-software-co-design flows for FPGA based systems, the hardware-software partitioning problem is solved offline, thus, omitting the great flexibility provided through partial runtime reconfiguration. The decision which functions are best suitable to be implemented in hardware or software, is typically taken with respect to the expected worst case computational demands and certain objectives like power consumption, throughput or cost. However, if these parameters change at runtime, e.g., due to environmental changes, traditional designed systems lack to adapt to the new conditions, because the hardware-software partitioning is static. In this paper we will systematically present a new methodology that allows to change the implementation style of tasks at runtime by hardware-software morphing. Based on a formal model, we will demonstrate, how morphing can be performed without loosing internal states. Moreover, we will present results from applying our methodology to a 16-tap FIR Alter. © 2007 IEEE.

Modeling of Interconnection Networks in Massively Parallel Processor Architectures - Kupriyanov, Olexiy; Hannig, Frank; Kissler, Dmitrij; Teich, Jürgen; Lallet, Julien; Sentieys, Olivier; Pillement, Sébastien (2006)

Modeling of interconnection networks in massively parallel processor architectures - Kupriyanov, Olexiy; Hannig, Frank; Kissler, Dmitrij; Teich, Jürgen; Lallet, Julien; Sentieys, Olivier; Pillement, Sébastien (Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS 2007), 2007)
In this paper, we present a new concept for modeling of interconnection networks in the field of massively parallel processor embedded architectures. The main focus of the paper is on two interconnection concepts, namely, interconnect-wrapper and DyRIBox definitions of reconfigurable interconnection networks. We compare both interconnection concepts against each other and formally prove their equality. Both concepts allow to model many different reconfigurable inter-processor networks efficiently. Furthermore, we point out how to define the interconnect using an architecture description language for massively parallel processor architectures called MAML. Finally, we demonstrate the pertinence of our approach by modeling and evaluation of different reconfigurable interconnect topologies. © Springer-Verlag Berlin Heidelberg 2007.

Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs - Fickenscher, Jörg; Reiche, Oliver; Schlumberger, Jens; Hannig, Frank; Teich, Jürgen (Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT), 2016)
Future Advanced Driver Assistance Systems (ADAS) require the continuous computation of detailed maps of the vehicle’s environment. Due to the high demand of accuracy and the enormous amount of data to be fused and processed, common architectures used today, like single-core processors in automotive Electronic Control Units (ECUs), do not provide enough computing power. Here, emerging embedded multi-core architectures are appealing such as embedded Graphics Processing Units (GPUs). In this paper, we (a) identify and analyze common subalgorithms of ADAS algorithms for computing environment maps, such as interval maps, for suitability to be parallelized and run on embedded GPUs. From this analysis, (b) performance models are derived on achievable speedups with respect to sequential single-core CPU implementations. (c) As a third contribution of this paper, these performance models are validated by presenting and comparing a novel parallelized interval map GPU implementation against a parallel occupancy grid map implementation. For both types of environment maps, implementations on an Nvidia Tegra K1 prototype are compared to verify the correctness of the introduced performance models. Finally, the achievable speedups with respect to a single-core CPU solution are reported. These range from 3x to 275x for interval and grid map computations.

Modellierung Rekonfigurierbarer Systemarchitekturen - Haubelt, Christian; Teich, Jürgen; Richter, Kai; Ernst, Rolf (GI / ITG / GMM Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2002)

Modular Video Streaming on a Reconfigurable Platform - Ahmadinia, Ali; Bobda, Christophe; Ding, Ji; Majer, Mateusz; Teich, Jürgen (IFIP VLSI-SOC 2005, 2005)
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.modula

Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays - Witterauf, Michael; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2016)

Molecular Force Field Parameterization using Multi-Objective Evolutionary Algorithms - Frauenheim, Th.; Hoffmann, M.; König, P.H.; Mostaghim, Sanaz; Teich, Jürgen (Proceedings of the Congress on Evolutionary Computation (CEC '04), 2004)

MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks - Sabih, Muhammad; Mishra, Ashutosh; Hannig, Frank; Teich, Jürgen (2022 IEEE 13th International Green and Sustainable Computing Conference (IGSC), 2022)
Deep neural networks (DNNs) are computationally intensive, making them difficult to deploy on resource-constrained embedded systems. Model compression is a set of techniques that removes redundancies from a neural network with affordable degradation in task performance. Most compression methods do not target hardware-based objectives such as latency directly; however, few methods approximate latency with floating-point operations (FLOPs) or multiply-accumulate operations (MACs). Using these indirect metrics cannot directly translate to the relevant performance metric on the hardware, i.e., latency and throughput. To address this limitation, we introduce Multi-Objective Sensitivity Pruning, “MOSP,” a three-stage pipeline for filter pruning: hardware-aware sensitivity analysis, Criteria-optimal configuration selection, and pruning based on explainable AI (XAI). Our pipeline is compatible with a single or combination of target objectives such as latency, energy consumption, and accuracy. Our method first formulates the sensitivity of layers of a model against the target objectives as a classical machine learning problem. Next, we choose a Criteria-optimal configuration controlled by hyperparameters specific to each objective of choice. Finally, we apply XAI-based filter ranking to select filters to be pruned. The pipeline follows an iterative pruning methodology to recover any loss in degradation in task performance (e.g., accuracy). We allow the user to prefer one objective function over the other. Our method outperforms the selected baseline method across different neural networks and datasets in both accuracy and latency reductions and is competitive with state-of-the-art approaches.<br
Keywords: Compression; Pruning; Energy Efficiency; Deep Neural Networks; Structured Pruning; Multi-Objective compression

Multidimensional Exploration of Software Implementations for DSP Algorithms - Bhattacharyya, Shuvra S.; Teich, Jürgen; Zitzler, Eckart (Journal of VLSI Signal Processing, 2000)
When implementing software for programmable digital signal processors (PDSPs), the design space is defined by a complex range of constraints and optimization objectives. Three implementation metrics that are crucial in many PDSP applications are the program memory requirement (code size), data memory requirement, and execution time. This paper addresses the problem of exploring the 3-dimensional space of trade-offs that is defined by these crucial metrics. Given a software library for a target PDSP, and a dataflow-based block diagram specification of a DSP application in terms of this library, our objective in this paper is to compute a full range of Pareto-optimal solutions. For solving this multi-objective optimization problem, an evolutionary algorithm based approach is applied. We illustrate our techniques by analyzing the trade-off fronts of a practical application for a number of well-known, commercial PDSPs.
UnivIS-Import:2015-03-09:Pub.2000.tech.IMMD.inform.multid

Multimodal Medical Image Registration Using Particle Swarm Optimization with Influence of the Data's Initial Orientation - Schmitt, Manuel; Wanka, Rolf; Schwab, Lydia (Proc. 12th IEEE Conf. on Computational Intelligence in Bioinformatics and Computational Biology (CIBCB), 2015)
UnivIS-Import:2015-10-26:Pub.2015.tech.IMMD.infalg._multi

Multi-Objective Design Space Exploration for the Optimization of the HEVC Mode Decision Process - Herglotz, Christian; Rosales, Rafael; Glaß, Michael; Teich, Jürgen; Kaup, André (Picture Coding Symposium (PCS), 2016)
Finding the best possible encoding decisions for compressing a video sequence is a highly complex problem. In this work, we propose a multi-objective Design Space Exploration (DSE) method to automatically find HEVC encoder implementations that are optimized for several different criteria. The DSE shall optimize the coding mode evaluation order of the mode decision process and jointly explore early skip conditions to minimize the four objectives a) bitrate, b) distortion, c) encoding time, and d) decoding energy. In this context, we use a SystemC-based actor model of the HM test model encoder for the evaluation of each explored solution. The evaluation that is based on real measurements shows that our framework can automatically generate encoder solutions that save more than 60% of encoding time or 3% of decoding energy when accepting bitrate increases of around 3

Multi-Objective Distributed Run-time Resource Management for Many-Cores - Wildermann, Stefan; Glaß, Michael; Teich, Jürgen (Proc. of Design, Automation and Test in Europe (DATE), 2014)
Dynamic usage scenarios of many-core systems require sophisticated run-time resource management that can deal with multiple often conflicting application and system objectives. This paper proposes an approach based on nonlinear programming techniques that is able to trade off between objectives while respecting targets regarding their values. We propose a distributed application embedding for dealing with soft system-wide constraints as well as a centralized one for strict constraints. The experiments show that both approaches may significantly outperform related heuristics. © 2014 EDAA.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.multio

Multi-objective local-search optimization using reliability importance measuring - Khosravi, Faramarz; Reimann, Felix; Glaß, Michael; Teich, Jürgen (Proceedings of the 51st Design Automation Conference (DAC 2014), 2014)
In recent years, reliability has become a major issue and ob- jective during the design of embedded systems. Here, differ- ent techniques to increase reliability like hardware-/software- based redundancy or component hardening are applied sys- tematically during Design Space Exploration (DSE), aiming at achieving highest reliability at lowest possible cost. Exist- ing approaches typically solely provide reliability measures, e. g. failure rate or Mean-Time-To-Failure (MTTF), to the optimization engine, poorly guiding the search which parts of the implementation to change. As a remedy, this work proposes an efficient approach that (a) determines the im- portance of resources with respect to the system's reliability and (b) employs this knowledge as part of a local search to guide the optimization engine which components/design de- cisions to investigate. First, we propose a novel approach to derive Importance Measures (IMs) using a structural eval- uation of Success Trees (STs). Since ST-based reliability analysis is already used for MTTF calculation, our approach comes at almost no overhead. Second, we enrich the global DSE with a local search. Here, we propose strategies guided by the IMs that directly change and enhance the implemen- tation. In our experimental setup, the available measures to enhance reliability are the selection of hardening levels during resource allocation and software-based redundancy during task binding; exemplarily, the proposed local search considers the selected hardening levels. The results show that the proposed method outperforms a state-of-the-Art ap- proach regarding optimization quality, particularly in the search for highly-reliable yet affordable implementations at negligible runtime overhead. Copyright 2014 ACM.

Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements - Letras, Martin; Falk, Joachim; Schwarzer, Tobias; Teich, Jürgen (ACM Transactions on Design Automation of Electronic Systems, 2020)
Dataflow modeling is well suited for a large variety of applications for modern multi-core architectures, e.g., from the signal processing and the control domain. Furthermore, Design Space Exploration (DSE) can be used to explore mappings of tasks to hardware resources (cores of an MPSoC) and their scheduling to obtain optimized trade-off solutions between throughput and resource costs. However, the throughput evaluation of an implementation candidate via compilation-in-the-loop or simulation-based approaches can be extremely time-consuming. Such a deficiency is very detrimental, because a typical DSE run needs to evaluate thousands of implementation candidates. As a remedy, we propose a hybrid-adaptive DSE where a max-plus algebra-based analytic throughput calculation method is used in the initial DSE phase to enable a fast progress of the search space exploration. However, as this analysis may be inaccurate as neglecting some real-world effects like cache and scheduling overhead, throughput measurements are taken later in the DSE. Moreover, we explore the trade-off between scheduling efficiency of implementation candidates—in favor of reducing concurrency—and exploiting concurrency to a large extent for parallel execution of the application. To find solutions of highest achievable throughput, it is shown that not only highly scheduling efficient implementation candidates but also highly parallel implementation candidates are essential when determining the initial population. In this realm, we contribute a method for diversity-based population initialization. For a representative set of benchmarks, it is shown that the combination of the two major contributions allows us to find much higher throughput multi-core solutions within a given exploration time compared to a state-of-the-art DSE approach.<br
Keywords: Dataflow; clustering; design space exploration; max-plus algebra; MPSoC

Multi-Objective Particle Swarm Optimization - Mostaghim, Sanaz; Teich, Jürgen (Dagstuhl Seminar No. 04461, 2004)

Multi-objective routing and topology optimization in networked embedded systems - Glaß, Michael; Lukasiewycz, Martin; Wanka, Rolf; Haubelt, Christian; Teich, Jürgen (Proc. 8th Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS), 2008)
Modern networked embedded system design has to cope with multiple design objectives. One major challenge is the determination of optimal routings with respect to these objectives. Existing automatic optimization approaches carry out a two step optimization: First, they perform a multi-objective topology optimization of the networked embedded system. Then, a multi-objective routing optimization for a subset of Pareto-optimal solutions obtained from the first step is performed. In general, this may exclude several globally optimal solutions from the optimization process. To overcome this drawback, a unified approach based on Multi-Objective Evolutionary Algorithms is presented that ensures a combined optimization of the topology and routing. Since the system topology is varied within the optimization, the main contribution of this paper contribution is a novel routing technique that always samples feasible paths using a topology independent genetic encoding. This encoding preserves optimized routing information when changing the underlying topology. An experimental evaluation shows the effectiveness of the presented approach.

Multi-objective topology optimization for networked embedded systems - Streichert, Thilo; Haubelt, Christian; Teich, Jürgen (Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2006), 2006)
In this paper, a new methodology is presented for topology optimization of networked embedded systems as they occur in automotive and avionic systems and partially in wireless sensor networks. By introducing a model which is (1.) suitable for heterogeneous networks with different communication bandwidths, (2.) modeling of routing restrictions, and (3.) flexible binding of tasks onto processors, current design issues of networked embedded systems can be investigated. On the basis of this model, the presented methodology firstly allocates the required resources which can be communication links as well as computational nodes and secondly binds the functionality onto the nodes and the data dependencies onto the links such that no routing restrictions will be violated or capacities on communication links will be exceeded. By applying Evolutionary Algorithms, we are able to consider multiple objectives simultaneously during the optimization process and allow for a subsequent unbiased decision making. An experimental evaluation as well as a demonstration of a case study from the field of automotive electronics will show the applicability of the presented approach. ©2006 IEEE.

Multiplexing Methods for Power Watermarking - Ziener, Daniel; Baueregger, Florian; Teich, Jürgen (Proc. IEEE Int. Symposium on Hardware-Oriented Security and Trust, 2010)
In this paper, we present several enhancements to power watermarking that allow to simultaneously transmit and verify multiple signatures. Power watermarking of netlist IP cores for FPGA architectures is used for detecting IP fraud where the signature (watermark) is transmitted over the power supply pins of the FPGA. Many (watermarked) IP cores can be combined in an FPGA design, which raises the question of how multiple signatures can be detected using the same set of pins. As a solution, we propose multiplexing techniques for power side channel communication, so that all watermarked cores inside the FPGA can be identified to establish a proof of authorship. We analyze different multiplexing methods in order to adapt them to power watermarking and provide experimental results with several cores concurrently transmitting signatures. ©2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.multip

Multi-requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study - Esper, Khalil; Wildermann, Stefan; Teich, Jürgen (Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022), 2022)
Embedded system applications usually have to meet hard real-time, energy or safety requirements on programs typically concurrently executed on a given MPSoC target platform. Enforcing such properties, e.g., by adapting the number of processors allocated to a program or by scaling the voltage/frequency mode of involved processors, is a difficult problem to solve, especially with a typically large varying environmental input (workload) per execution. In a previous work [1], we formalized the related enforcement problem using (a) finite state machines to model enforcement strategies, (b) discrete-time Markov chains to model the uncertain environment determining the system’s workload, and (c) the system response that defines the feedback for the reactive enforcer. In this paper, we apply that approach to specify and verify multi-requirement enforcement strategies and assess a case study for enforcing two independent requirements at the same time, i.e., latency and energy consumption. We evaluate and compare different enforcement strategies using probabilistic verification for the use case of an object detection application
Keywords: Runtime Requirement Enforcement; Verification; Finite State Machine; Markov Chain; Probabilistic Model Cheking; PCTL; MPSoC

Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems - Brand, Peter; Falk, Joachim; Potwigin, Eduard; Teich, Jürgen (Proceedings of the 2021 International Symposium on Networks, Computers and Communications (ISNCC 2021), 2021)
Reducing the energy consumption is an important objective in the development of cellular modems for LTE and 5G standards. In addition to hardware optimizations, Dynamic Power Management (DPM) techniques that aim at powering down idle system components are crucial for achieving this goal. However, most DPM techniques proposed so far for mobile devices are purely reactive. More promising are recently proposed proactive approaches that predict whether communication with the cellular base station will occur in the next time slot or not. Due to transition times between power states, however, such single-step approaches may not exploit deeper power-saving states of components. As a remedy, this paper proposes multi-step ahead prediction techniques that forecast periods of no communication lasting multiple time-slots. In this context, we define a formal fine-grained power model and introduce novel predictive power management policies. Furthermore, we explore the impact of the forecast period–the number of predicted time-slots–in terms of false-negative error rate as well as achievable energy savings compared to a standard LTE-compliant reactive DPM. Finally, it is shown that this overall energy-saving potential of the proposed multi-step predictive approach may be higher by up to a factor of 3 compared to a single-step predictive approach without incurring a higher false-negative error rate. Alternatively, the multi-step approach may allow a reduction of the false negative error rate by a factor of 4.1 compared to the single-step approach without reduction of expectable energy savings. In fact, the observed low false-negative error rate of 0.0083 may facilitate a realization in future modem solutions.<br

Multi-Valued Decision Diagrams for the Verification of Consistency in Automotive Product Data - Berndt, Rüdiger; Bazan, Peter; Hielscher, Kai-Steffen; German, Reinhard; Lukasiewycz, Martin (Proceedings of 12th International Conference on Quality Software (IEEE), 2012)
Highly customizable products and mass customization - as increasing trends of the last years - are mainly responsible for an immense growth of complexity within the digital representations of knowledge of car manufacturers. We developed a method to detect and analyze inconsistencies by employing a Multi-Valued Decision Diagram (MDD) which is used to encode the set of all valid product configurations. On this basis, we stated a number of rules of consistency that are checked by a set-based verification scheme. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.IMMD7.multiv
Keywords: Digital manufacturing; Formal verification; Knowledge representation; Multi-valued decision diagram; Product configuration

Multi-Variant-based Design Space Exploration for Automotive Embedded Systems - Graf, Sebastian; Glaß, Michael; Teich, Jürgen; Lauer, Christoph (Proc. of Design, Automation and Test in Europe (DATE), 2014)
This paper proposes a novel design method for modern automotive electrical and electronic (E/E) architecture component platforms. The addressed challenge is to derive an optimized component platform termed Baukasten where components, i. e., different manifestations of Electronic Control Units (ECUs), are reused across different car configurations, models, or even OEM companies. The proposed approach derives an efficient graph-based exploration model from defined functional variants. From this, a novel symbolic formulation of multi-variant resource allocation, task binding, and message routing serves as input for a state-of-the-art hybrid optimization technique to derive the individual architecture for each functional variant and the resulting Baukasten at once. For the first time, this enables a concurrent analysis and optimization of individual variants and the Baukasten. Given each manifestation of a component in the Baukasten induces production, storage, and maintenance overhead, we particularly investigate the trade-off between the number of different hardware variants and other established design objectives like monetary cost. We apply the proposed technique to a real-world automotive use case, i. e., a subsystem within the safety domain, to illustrate the advantages of the multi-variant-based design space exploration approach. © 2014 EDAA.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.multiv

Near-Data Query Processing on Heterogeneous FPGA-based Systems - Becher, Andreas (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2022)
Query processing is a traditional yet still ongoing field of research. Its significance is derived from the increase of data created and processed every day and the opportunities provided by the analysis of the data. In today’s world, complete businesses are built on top of sophisticated data processing capabilities. However, with the increase of data, processing these huge amounts of data becomes more and more challenging. This is not only because of the time and resources it takes to process such amounts of data but also due to the energy costs. Consequently, researchers broadened the range of processing architectures to investigate for query processing beyond traditional processor-based systems. Next to programmable graphic processing units (GPUs), field programmable gate arrays (FPGAs) have become of great interest due to their unique features. FPGAs not only allow for the construction of highly optimized hardware circuits for specific tasks but also enable the adaption of hardware to the tasks during runtime. Hence, many researchers have presented various proposals to exploit the features provided by FPGAs. Although the proposed systems can achieve high throughput and efficiency in general, they are often not able to accelerate queries that haven’t been considered during their design. Performance and efficiency can only be gained best through specialization, and thus, a system should adapt to an incoming and unknown query. This is possible with FPGAs due to their ability to be reconfigured fully or in parts during runtime. However, this comes at the cost of high startup times as the FPGA has to be configured according to the query prior to the execution of the query. Furthermore, it is almost impossible to generate hardware configurations for every possible query. This thesis introduces an innovative FPGA-based near-data processing system able to process a wide variety of queries at I/O-rate (line-rate). It is based on reconfigurable and parametrizable accelerators. The accelerators are composed of parametrizable modules within a library. These modules do not only implement a specific operator for a specific type but are optimized to implement operators for multiple types or even multiple functions without a drastic increase of resources. Another contribution of this thesis is the concept of optimistic query processing for demanding operators such as the join and regular matching operator. It is based on the idea to approximately filter as much data as possible in hardware without removing tuples that should be kept. The resulting, often reduced, intermediate table is guaranteed to be a superset of the accurate filter operation. A software-based operator implementation can then be applied on an intermediate table with less tuples to finalize the operation. As an example, the implementation of a module for regular expression matching is presented. Equipped with a parameter sequencer, accelerators assembled from this library are able to implement a greater variety of queries by setting the parameters of the modules according to the query to process. However, the schema which the tables are stored in also influences the design of the accelerator and, therefore, may limit the types of queries it can implement. For this, a hardware unit called ReOrder is introduced. It decouples the table schema and storage layout from the accelerator enabling all accelerators to be used on every table with row-oriented and column-oriented storage layouts. Even though the developed accelerators are able to implement a wide variety of queries, no one-fits-all accelerator is possible. Consequently, the system is designed to concatenate multiple partially reconfigurable (i.e., exchangeable) accelerators without a decrease in tuple throughput. This increases the types of queries that can be processed even further. As accelerators might not use all available resources within a partially reconfigurable FPGA region, the idea of in situ statistics generation is proposed. In situ statistics modules can utilize the free resources to gather information on the table that is processed by an accelerator without additional costs in terms of time. Complementary to the hardware related parts already mentioned, a control software managing the execution of a query on such a system is presented as well. Starting from the basic components needed to execute queries on the platform, the description goes into depth on the particularities of such a FPGA-based query execution system. Especially the query placement problem which describes the problem of finding a query-specific-configuration of the system’s hardware according to an incoming query is formulated. In addition, the challenges to obtain an optimal placement is discussed and exemplified using the problem of buffer assignment. Afterwards, the parameters of the modules have to be generated. In this regard, an algorithm to obtain the parameters for a ReOrder unit is presented and evaluated in depth. Additionally, considerations about parameter generators for a histogram module and the optimistic regular expression matching module are provided. Finally, an implemented prototype of the system called ReProVide unit has been evaluated. It is able to provide I/O-rate processing of simple as well as complex queries. Compared to a software-based in-memory database system executed on an ARM processor, queries could be executed 19.9× faster on the prototype on average. When executed on an x86 processor, comparable execution times have been observed. This means the prototype system storing the tables on two solid states drives was able to process queries as fast as an x86 system holding the tables in memory. Furthermore, the prototype built is shown to be very energy-efficient, consuming only less than 25% of the energy consumed by the x86 system on average.<br
Keywords: FPGA; Hardware-Software-Co-Design; Query Acceleration

Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs - Schmid, Moritz; Ziener, Daniel; Teich, Jürgen (Proceedings of IEEE International Conference on Field-Programmable Technology, 2008)
This paper presents a novel approach to watermark FPGA designs on the netlist level. We restrict the dynamically addressable part of the logic table, thus freeing space for insertion of signature bits into lookup tables (LUTs). In this way, we tightly integrate the watermark with the design so that simply removing mark carrying components would damage the intellectual property core. Converting functional LUTs to LUT-based RAMs or shift registers prevents deletion due to optimization. With this technique, we take watermark carrying components out of the scope of optimization algorithms to achieve complete transparency towards development environments. We can extract the marks from the bitfile of an FPGA. The method was tested on a Xil-inx Virtex-II Pro FPGA and showed low overhead in terms of timing and resources at a reasonable number of watermarked cells. © 2008 IEEE.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.netlis

Network bandwidth optimization of ethernet-based streaming applications in automotive embedded systems - Kern, Andreas; Schmutzler, Christoph; Streichert, Thilo; Hübner, Michael; Teich, Jürgen (Proceedings of the Internaional Conference on Computer Communication Networks (ICCCN) 2010 – Track on Network Algorithms, Performance Evaluation and Theory (NAPET), 2010)
Modern cars are equipped with an increasing number of electronic systems which encompass comfort, security, and infotainment related features. The complexity of the physical and logical network topology as well as the bandwidth requirements are steadily increasing. Therefore, a bus standard that can handle upcoming application requirements and is suitable for the automotive environment is needed. One possibility is the use of Ethernet/IP - both standards are widespread and have proven to be very reliable and robust, however they were formerly not designed for embedded systems. Previous work shows that the achievable bandwidth on embedded systems lies far below the theoretical achievable line rate speed of Ethernet. This paper focuses on improving the networking performance of automotive embedded systems which send Ethernet-based data into a network. It highlights several system variants and evaluates the achievable performance with consideration of the necessary hardware and software changes. © 2010 IEEE.

Network interface with task spawning support for NoC-based DSM architectures - Zaib, Aurang; Heißwolf, Jan; Weichslgartner, Andreas; Wild, Thomas; Teich, Jürgen; Becker, Jürgen; Herkersdorf, Andreas (Proceedings of 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS), 2015)
Distributed Shared Memory (DSM) architectures are becoming popular to exploit parallelism of architectures while offering flexibility of using both shared and distributed memory paradigms to application developers. At the same time, Networks on Chip (NoC) have become reality to address communication bottlenecks in massively parallel tile-based processor architectures. In NoC-based DSM architectures, the synchronization overhead for spawning a task on a remote network node may lead to high performance penalties. In order to reduce the synchronization delays during remote task spawning, the design of Network Interface (NI) becomes important. In this paper, we present a network interface architecture which supports task spawning between network nodes by employing efficient synchronization mechanisms. The proposed NI internal hardware support offloads the software from handling the synchronization during remote task spawning and hence results in achieving better overall performance. Simulation results highlight that the proposed hardware architecture improves the performance by up to 42% in comparison to existing state of the art approaches. The FPGA prototype is also used to depict the benefits of the proposed approach for real world applications. Implementation results show the low area footprint of the proposed hardware.

New Directions for FPGA IP Core Watermarking and Identification - Ziener, Daniel; Teich, Jürgen (Dagstuhl Seminar 10281 Proceedings, 2010)

No-Break Dynamic Defragmentation of Reconfigurable Devices - Fekete, Sandor P.; Kamphans, Tom; Schweer, Nils; Tessars, Christopher; Van Der Veen, Jan C.; Angermeier, Josef; Koch, Dirk; Teich, Jürgen (Proceedings of International Conference on Field-Programmable Logic and Applications, 2008)
We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs. Our method is based on dynamic relocation of module positions during runtime, with only very little reconfiguration overhead: the objective is to maximize the length of contiguous free space that is available for new modules. We describe a number of algorithmic aspects of good defragmen-tation, and present an optimization method based on tabu search. Experimental results indicate that we can improve the quality of module layout by roughly 50% over static layout. Among other benefits, this improvement avoids unnecessary rejection of modules.© 2008 IEEE.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.nobrea

NoC Simulation in Heterogeneous Architectures for PGAS Programming Model - Roloff, Sascha; Weichslgartner, Andreas; Heißwolf, Jan; Hannig, Frank; Teich, Jürgen (Proc. 16th International Workshop on Software and Compilers for Embedded Systems, 2013)
Multi- And many-core systems become more and more mainstream and therefore new communication infrastructures like Networks-on-Chip (NoC) and new programming languages like IBM's X10 with its partitioned global address space (PGAS) are introduced. In this paper we present an X10- based simulator, which is capable to simulate the network traffic that occurs inside the X10 program. This holistic approach enables to simulate the functionality and the indicated traffic together, in contrast to pure network simulators where usually only synthetic traffic or traces are used. We explain how the communication overhead is extracted from the X10 run-time and how to simulate the NoC behavior. In experiments we show that the proposed simulator is up to 10× faster than a comparable SystemC-based simulator and at the same time preserves high accuracy. Furthermore, we present a quality and simulation speed tradeoff by using different simulation modes for a set of real world parallel applications. Copyright © 2013 ACM.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.nocsim
Keywords: Modeling; Network-on-chip; Parallel programming; Simulation

Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - Abelein, Ulrich; Cook, Alejandro; Engelke, Piet; Glaß, Michael; Reimann, Felix; Gómez, Laura Rodríguez; Russ, Thomas; Teich, Jürgen; Ull, Dominik; Wunderlich, Hans Joachim (Proc. of Design, Automation and Test in Europe (DATE), 2014)
With ever more complex automotive systems, the current approach of using functional tests to locate faulty components results in very long analysis procedures and poor diagnostic accuracy. Built-In Self-Test (BIST) offers a promising alternative to collect structural diagnostic information during E/E-architecture test. However, as the automotive industry is quite cost-driven, structural diagnosis shall not deteriorate traditional design objectives. With this goal in mind, the work at hand proposes a design space exploration to integrate structural diagnostic capabilities into an E/E-architecture design. The proposed integration is performed non-intrusively, i. e., the addition and execution of tests (a) does not affect any functional applications and (b) does not require any costly changes in the communication schedules. © 2014 EDAA.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.nonint

Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device - Ahmadinia, Ali; Fekete, Sandor P.; Göhringer, Diana; Majer, Mateusz; Teich, Jürgen; et al. (IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 2008)
UnivIS-Import:2015-04-14:Pub.2007.tech.IMMD.inform.offlin

On confident task-accurate performance estimation - Xu, Yang; Wang, Bo; Rosales, Rafael; Hasholzner, Ralph; Teich, Jürgen (Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 2013)
Task-accurate performance estimation methods are widely applied for design space exploration at the Electronic System Level (ESL). These methods estimate performance by simulating task-level models annotated with nominal execution time. In early design phases, source code, which is necessary for generating accurate annotations, is usually not available. Instead, extrapolated values or even estimated values are used for performance estimation, which makes the results unreliable and may eventually cause performance violations if used to guide critical design decisions. In this paper, we propose a confident task-accurate performance estimation methodology that uses high-level information available in early design phases and provides confident estimation to guide design space exploration with respect to performance constraints. © 2013 Springer-Verlag.

On-demand fault-tolerant loop processing on massively parallel processor arrays - Tanase, Alexandru-Petru; Witterauf, Michael; Teich, Jürgen; Hannig, Frank; Lari, Vahid (In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2015)
We present a compilation-based technique for providing on-demand structural redundancy for massively parallel processor arrays. Thereby, application programmers gain the capability to trade throughput for reliability according to application requirements. To protect parallel loop computations against errors, we propose to apply the well-known fault tolerance schemes dual modular redundancy (DMR) and triple modular redundancy (TMR) to a whole region of the processor array rather than individual processing elements. At the source code level, the compiler realizes these replication schemes with a program transformation that: (1) replicates a parallel loop program two or three times for DMR or TMR, respectively, and (2) introduces appropriate voting operations whose frequency and location may be chosen from three proposed variants. Which variant to choose depends, for example, on the error resilience needs of the application or the expected soft error rates. Finally, we explore the different tradeoffs of these variants in terms of performance overheads and error detection latenc

One-pass Synthesis for Digital Microfluidic Biochips: A Survey - Keszöcze, Oliver; Wille, Robert; Drechsler, Rolf (International Symposium on Devices, Circuits and Systems, 2020)
With the advances of the microfluidic technology, the design of Digital Microfluidic Biochips (DMFBs) received significant attention in the recent past. The corresponding design process usually consists of multiple, consecutive design tasks, namely binding, scheduling, placement, and routing. These tasks, however, are often considered and solved separately. This can lead to design gaps between the individual steps, yielding less-than-optimal overall solutions or prevent to solve the next step altogether. In order to address these shortcomings, the concept of one-pass synthesis for DMFBs has been introduced. In this survey paper, we review the main ideas of this concept and provide an overview on two different implementations of it: (1) an exact, SAT-based approach which guarantees optimal solutions with respect to area and/or timing and (2) a heuristic graph-based approach which focuses on run-time efficiency. We discuss the (dis-)advantages of those approaches with respect to their quality as well as scalability and illustrate them on various benchmark assays.<br
Keywords: DMFB; one-pass synthesis; survey; Biochips

On finding a minimal enclosing parallelogram - Evans, Brian L.; Schwarz, Christian; Teich, Jürgen; Welzl, Emo (In Proc. 11th ACM Symposium on Computational Geometry, 1995)

On finding a minimal enclosing parallelogram - Evans, Brian L.; Schwarz, Christian; Teich, Jürgen; Welzl, Emo (4th MSI Workshop on Computational Geometry, 1994)
UnivIS-Import:2015-04-16:Pub.1994.tech.IMMD.inform.onfind

Online hardware/software partitioning in networked embedded systems - Streichert, Thilo; Haubelt, Christian; Teich, Jürgen (Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05), 2005)
Today's embedded systems are typically distributed and more often confronted with time-varying demands. Existing methodologies that optimize the partitioning of computational tasks to hardware (HW) and software (SW) at compile-time become obsolete or inefficient in this context as the optimal use of existing resources cannot be foreseen. Here, we investigate a discrete iterative algorithm that balances the load of a HW/SW partition online: Once there are changing computational demands, the system will dynamically assign tasks to reconflgurable HW or SW resources and migrates tasks to other nodes if necessary. For this purpose an Evolutionary Algorithm combined with a discrete version of a diffusion algorithm is presented. Concerning the diffusion algorithm, we will show theoretically and by experiment that our version is run-time optimal in a linear number of steps. © 2005 IEEE.

Online Placement for Dynamically Reconfigurable Devices - Ahmadinia, Ali; Bobda, Christophe; Teich, Jürgen (EURASIP Journal on Embedded Systems, 2006)
UnivIS-Import:2015-03-09:Pub.2006.tech.IMMD.inform.online

On robust task-accurate performance estimation - Xu, Yang; Wang, Bo; Hasholzner, Ralph; Rosales, Rafael; Teich, Jürgen (Proceedings of the 50th Design Automation Conference (DAC 2013), 2013)
Task-accurate performance estimation methods are widely applied in early design phases to explore different architecture options. These methods rely on accurate annotations generated by software profiling or real measurements to guarantee accurate results. However, in practice, such accurate annotations are not available in early design phases due to lack of source code and hardware platform. Instead, estimated mean or worst-case annotations are usually used, which makes the final result inaccurate because of the errors induced by the estimations, especially for designs with tight time constraints. In this paper, we propose a novel methodology that combines Distributionally Robust Monte Carlo Simulation with task-accurate performance estimation method to guarantee robust system performance estimation in early design phases, i.e., determining the lower bound of the confidence level of fulfilling a specific time constraint. Instead of using accurate annotations, our method only uses estimated annotations in the form of intervals and it does not make any assumptions of the distribution types of these intervals. Copyright © 2013 ACM.
Keywords: Distributionally robust Monte Carlo simulation; Robust performance estimation; Task-accurate

On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures - Letras, Martin; Falk, Joachim; Schwarzer, Tobias; Teich, Jürgen (Proceedings of the 22st International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019, Sankt Goar, Germany, 2019)
Dataflow modeling is well suited for a wide variety of applications for multi-core architectures, e.g. signal processing and control domain. Additionally, DSE can be used to explore the distribution of tasks to resources and their scheduling to obtain optimized trade-off solutions between throughput and resource costs. However, the performance evaluation of an implementation candidate in particular via compilation and throughput measurement on the target hardware is prohibitively time-consuming. Thus, we propose to use a max-plus algebra-based analytic throughput calculation method in the initial DSE phase where a fast evaluation with low accuracy is sufficient to guide the search through the design space. However, this analysis neglects some real-world concerns like cache effects and scheduling overhead. Thus, a hybrid DSE is proposed where throughput measurements are taken later in the DSE to get more accurate throughput results for real-world platforms. Results show that our approach is able to find much higher throughput multi-core solutions within a given exploration time compared to a state-of-the-art DSE approach.<br
Keywords: Dataflow; Clustering; Design Space Exploration; Max-Plus algebra

On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Keszöcze, Oliver; Khosravi, Faramarz; Becher, Andreas; Teich, Jürgen (2021)

On the Approximation of Arithmetic Functions and Logic Snythesis of Approximate Very Large Boolean Networks - Echavarria Gutiérrez, Jorge Alfonso (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2022)

On the Boolean Extension of the Birnbaum Importance to Non-Coherent Systems - Aliee, Hananeh; Borgonovo, Emanuele; Glaß, Michael; Teich, Jürgen (Reliability Engineering & System Safety, 2017)

On the Complexity of Mapping Feasibility in Many-Core Architectures - Schwarzer, Tobias; Roloff, Sascha; Richthammer, Valentina; Khaldi, Rami; Wildermann, Stefan; Glaß, Michael; Teich, Jürgen (Proceedings of Multicore/Many-core Systems-on-Chip (MCSoC-2018), 2018)

On the design of hardware architectures for parallel frequent itemsets mining - Letras, Martin; Bustio, Lazaro; Cumplido, René; Hernández-León, Raudel; Feregrino, Claudia (Expert Systems With Applications, 2020)
Algorithms for Frequent Itemsets Mining have proved their effectiveness for extracting frequent sets of patterns in datasets. However, in some specific cases, they do not obtain the expected results in an acceptable time. For this reason, Field Programmable Gates Array-based architectures for Frequent Itemsets Mining have been proposed to accelerate this task. The current paper proposes a search strategy for Frequent Itemsets Mining based on equivalence classes partitioning. The partitioning on equivalence classes allows dividing the search space into disjoint sets that can be processed in parallel. Consequently, this paper presents the design and implementation of two hardware architectures that exploit the nested parallelism in the proposed search strategy. These hardware architectures are capable of obtaining frequent itemsets regardless of the number of distinct items and the number of transactions in the dataset, which are the main issues reported in the reviewed literature. Furthermore, the proposed architectures explore the trade-off between acceleration and hardware resource utilization. The experimental results obtained demonstrate that the proposed search strategy can be scaled to achieve a speedup in the processing time of 40 times faster than software-based implementations.<br
Keywords: Frequent itemsets mining; Data streams; Custom architectures; FPGAs; ECLAT

On-the-fly Composition of FPGA-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library - Dennl, Christopher; Ziener, Daniel; Teich, Jürgen (Proc. of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), 2012)
In this paper, we introduce a novel FPGA-based methodology for accelerating SQL queries using dynamic partial reconfiguration. Query acceleration is of utmost importance in large database systems to achieve a very high throughput. Although common FPGA-based accelerators are suitable to achieve such a high throughput, their design is hard to extend for new operations. Using partial dynamic reconfiguration, we are able to build more flexible architectures which can be extended to new operations or SQL constructs with a very low area overhead on the FPGA. Furthermore, the reconfiguration of a few FPGA frames can be used to switch very fast from one query to the next. In our approach, an SQL query is transformed into a hardware pipeline consisting of partially reconfigurable modules. The assembly of the (FPGA) data path is done at run-time using a static system providing the stream-based communication interfaces to the partial modules and the database management system. More specifically, each incoming SQL query is analyzed and divided into single operations which are subsequently mapped onto library modules and the composed data path loaded on the FPGA. We show that our approach is able to achieve a substantially higher throughput compared to a software-only solution. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.onthef

On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures - Spieck, Jan; Wildermann, Stefan; Teich, Jürgen (CODES+ISSS 2022, 2022)

OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes - Kenter, Tobias; Mahale, Gopinath; Alhaddad, Samer; Grynko, Yevgen; Schmitt, Christian; Afzal, Ayesha; Hannig, Frank; Förstner, Jens; Plessl, Christian (Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2018)
The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.

Open Source Hardware - Hannig, Frank; Teich, Jürgen (IEEE Computer, 2021)
Hardware that can be manufactured from free and open source descriptions has gained a lot of momentum. This article gives a general introduction, focusing on electronics and integrated circuits, corresponding open ecosystems and organizations, and highlights benefits and challenge

Operational Mode Exploration for Reconfigurable Systems with Multiple Applications - Wildermann, Stefan; Reimann, Felix; Teich, Jürgen; Salcic, Zoran (Proceedings of the International Conference on Field-Programmable Technology, 2011)
Modern embedded systems incorporate multiple applications that run on the same execution platform. However, due to limited resources and other constraints, not all the combinations of applications may run concurrently. This paper tackles the problem of determining which combinations of applications can run on a given hardware architecture without violating given constraints, thus creating feasible operational modes of the system. The architecture itself may include standard processors for software implementation of applications and dynamically (partially) reconfigurable hardware resources, which enable dynamic sharing of the resource in different operational modes. The paper describes the models, theoretical results, and the mode exploration algorithm to perform this task. Here, the specification is symbolically encoded so that the feasibility of modes can be tested by applying a SAT solver. In the experiment, we demonstrate how to apply our approach to build a self-organizing smart camera framework. © 2011 IEEE.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.operat

Opt4J - A Modular Framework for Meta-heuristic Optimization - Lukasiewycz, Martin; Glaß, Michael; Reimann, Felix; Teich, Jürgen (Proc. of the 13th Annual Genetic and Evolutionary Computation Conference, 2011)
This paper presents a modular framework for meta-heuristic optimization of complex optimization tasks by decomposing them into subtasks that may be designed and developed separately. Since these subtasks are generally correlated, a separate optimization is prohibited and the framework has to be capable of optimizing the subtasks concurrently. For this purpose, a distinction of genetic representation (genotype) and representation of a solution of the optimization problem (phenotype) is imposed. A compositional genotype and appropriate operators enable the separate development and testing of the optimization of subtasks by a strict decoupling. The proposed concept is implemented as open source reference OPT4J [6]. The architecture of this implementation is outlined and design decisions are discussed that enable a maximal decoupling and flexibility. A case study of a complex real-world optimization problem from the automotive domain is introduced. This case study requires the concurrent optimization of several heterogeneous aspects. Exemplary, it is shown how the proposed framework allows to efficiently optimize this complex problem by decomposing it into subtasks that are optimized concurrently. Copyright 2011 ACM.
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.inform.opt4ja
Keywords: Framework; Modular; Optimization

Optimal FPGA Module Placement with Temporal Precedence Constraints - Fekete, Sandor P.; Köhler, Ekkehard; Teich, Jürgen (Proc. DATE 2001, Design, Automation and Test in Europe, 2001)
We consider the optimal placement of hardware modules in space and time for FPGA architectures with reconfiguration capabilities, where modules are modeled as three-dimensional boxes in space and time. Using a graph-theoretic characterization of feasible packings, we are able to solve the following problems. (a) Find the minimal execution time of the given problem on an FPGA of fixed size, (b) Find the FPGA of minimal size to accomplish the tasks within a fired time limit. Furthermore, our approach is perfectly suited for the treatment of precedence constraints for the sequence of tasks, which are present in virtually all practical instances. Additional mathematical structures are developed that lead to a powerful framework for completing optimal solutions. The usefulness is illustrated by computational results. © 2001 IEEE.
UnivIS-Import:2015-04-16:Pub.2001.tech.IMMD.inform.optima

Optimal free-space management and routing-conscious dynamic placement for reconfigurable devices - Ahmadinia, Ali; Bobda, Christophe; Fekete, Sandor P.; Teich, Jürgen; Van Der Veen, Jan C. (IEEE Transactions on Computers, 2007)
We describe algorithmic results on two crucial aspects of allocating resources on computational hardware devices with partial reconfigurability. By using methods from the field of computational geometry, we derive a method that allows correct maintenance of free and occupied space of a set of n rectangular modules in time O(n log n); previous approaches needed a time of O(n) for correct results and O(n) for heuristic results. We also show a matching lower bound of Ω(n log n), so our approach is optimal. We also show that finding an optimal feasible communication-conscious placement (which minimizes the total weighted Manhattan distance between the new module and existing demand points) can be computed with Θ(n log n). Both resulting algorithms are practically easy to implement and show convincing experimental behavior. © 2007 IEEE.
Keywords: Field-programmable gate array (FPGA); Free-space manager; Geometric optimization; Line-sweep technique; Lower bounds; Module placement; Optimal runtime; Reconfigurable hardware; Routing-conscious placement

Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators - Sim, Joon Edward; Wong, Weng-Fai; Teich, Jürgen (Proc. 17th IEEE Symposium on Field Programmable Custom Computing Machines, 2009)
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time algorithm for scheduling reconfiguration tasks given a trace of actors (invocations of hardware kernels) that is both provably optimal and placement-aware. In addition, we will propose a dependence analysis to determine whether for each actor instance, a reconfiguration task is needed prior to its execution in hardware. A case study using the H.264 encoder is presented to compare our algorithm against the state-of-the-art heuristics. © 2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.optima

Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices - Ahmadinia, Ali; Bobda, Christophe; Fekete, Sandor P.; Teich, Jürgen; Van Der Veen, Jan C. (Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), 2004)
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.optima_5

Optimal tradeoffs between size and slowdown for universal parallel networks - Wanka, Rolf; Meyer auf der Heide, Friedhelm; Storch, Martin (Theory of Computing Systems, 1997)
A parallel processor network is called n-universal with slowdown s if it can simulate each computation of each constant-degree processor network with n processors with slowdown s. We prove the following lower bound tradeoff: for each constant-degree n-universal network of size m with slowdown s,m·s = Ω(n log m) holds. Our tradeoff holds for a very general model of simulations. It covers all previously considered models and all known techniques for simulations among networks. For m ≥ n, this improves a previous lower bound by a factor of log log n, proved for a weaker simulation model. For m ≥ n, this is the first nontrivial lower bound for this problem. In this case this lower bound is asymptotically tight.

Optimistic Regular Expression Matching on FPGAs for Near-Data Processing - Becher, Andreas; Wildermann, Stefan; Teich, Jürgen (Data Management on New Hardware (DaMoN), 2018)

Optimization Algorithms for Dynamically Reconfigurable Embedded Systems - Ahmadinia, Ali (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2006)

Optimization Algorithms for Dynamic Reconfigurable Embedded Systems - Ahmadinia, Ali (Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), 2004)

Optimization Flow for Algorithm Mapping on Graphics Cards - Membarth, Richard; Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.optimi

Optimization of Dynamic Hardware Reconfigurations - Fekete, Sandor P.; Schepers, Jörg; Teich, Jürgen (Journal of Supercomputing, 2001)
Recent generations of Field Programmable Gate Arrays (FPGA) allow the dynamic reconfiguration of cells on the chip during run-time. For a given problem consisting of a set of tasks with computation requirements modeled by rectangles of cells, several optimization problems such as finding the array of minimal size to accomplish the tasks within a given time limit are considered. Existing approaches based on ILP formulations to solve these problems as multi-dimensional packing problems turn out not to be applicable for problem sizes of interest. Here, a breakthrough is achieved in solving these problems to optimality by using the new notion of packing classes. It allows a significant reduction of the search space such that problems of the above type may be solved exactly using a special branch-and-bound technique. We validate the usefulness of our method by providing computational results.
UnivIS-Import:2015-03-09:Pub.2001.tech.IMMD.inform.optimi
Keywords: Multi-dimensional placement and packing; Reconfigurable hardware

Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures - Wolinski, Christophe; Kuchcinski, Krzysztof; Teich, Jürgen; Hannig, Frank (Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines, 2008)
In this paper, we present a constraint programmingbased approach for optimization of routing and reconfiguration overhead for a class of reconfigurable processor array architectures called weakly programmable. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for optimal routing of data between processor elements as well as for minimization of the routing area and the reconfiguration overhead when switching between the execution of these algorithms. Our experiments confirm that our method can minimize routing overhead and reduce reconfiguration time significantly. © 2008 IEEE.
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.optimi

Optimized Software Synthesis for Digital Processing Algorithms - An Evolutionary Approach - Bhattacharyya, Shuvra; Teich, Jürgen; Zitzler, Eckart (1998)

Optimized Software Synthesis for Digital Signal Processing Algorithms: An Evolutionary Approach - Bhattacharyya, Shuvra; Teich, Jürgen; Zitzler, Eckart (Proc. of the 1998 Workshop on Signal Processing Systems, 1998)
Based on the model of synchronous data flow (SDF), so called single appearance schedules are known to provide memory-optimal schedules. Among these the problem of buffer memory optimization is treated: (1) An Evolutionary Algorithm (EA) is applied to efficiently explore the (in general) exponential search space of actor firing orders. (2) For each order, the buffer costs are evaluated by applying a dynamic programming post-optimization step (GDPPO).
UnivIS-Import:2015-04-16:Pub.1998.tech.IMMD.inform.optimi_1

Optimized Software Synthesis for DSP Using Randomization Techniques - Bhattacharyya, Shuvra S.; Teich, Jürgen; Zitzler, Eckart (1999)

Optimizing Dynamic Hardware Reconfigurations - Teich, Jürgen; Fekete, Sándor; Schepers, Jörg (1998)

Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and its Application to Cellular Modems - Ah Sue, Jonathan; Brand, Peter; Falk, Joachim; Hasholzner, Ralph; Teich, Jürgen (HCII 2019 Late Breaking Work Papers Proceedings, 2019)
As 5G wireless communication technology will be deployed in the next few years, an increasing amount of data becomes available from mobile devices tested out in the field. Exploiting this data, recent investigations show the potential to improve the wireless modem design and performance using data- centric approaches, e.g., power optimization with machine learning (ML) algorithms [1]. As depicted in Figure 1, such data-centric workflows are exploratory and iterative by nature. For instance, time pattern identification is performed by domain experts to derive assumptions on potential optimizations and these assumptions are continuously refined during multiple iterations of data collection and exploration. In this context, we propose 3 ideas to increase the exploration speed: (i) a methodology to minimize the data pre-processing duration in each iteration, (ii) a novel entropy-based data interaction technique for visual event sequence exploration and (iii) a similarity measure to perform subsequence matching in order to identify frequent modem behaviors to be optimized.<br
Keywords: 5G; LTE; machine learning; visualization

Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor - Salcic, Zoran; Nadeem, Muhammad; Park, Heejong; Teich, Jürgen (Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), 2016)

Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks - Smirnov, Fedor; Glaß, Michael; Reimann, Felix; Teich, Jürgen (Proceedings of 54th ACM/EDAC/IEEE Design Automation Conference (DAC 2017), 2017)

Optimizing Performance of Stencil Code with SPL Conqueror - Grebhahn, Alexander; Siegmund, Norbert; Apel, Sven; Kuckuk, Sebastian; Schmitt, Christian; Köstler, Harald (Proceedings of the 1st International Workshop on High-Performance Stencil Computations (HiStencils), 2014)
UnivIS-Import:2015-04-17:Pub.2014.tech.IMMD.lsinfs.optimi

Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning - Schmidt, Bernhard; Ziener, Daniel; Teich, Jürgen; Zöllner, Christian (Integration-The Vlsi Journal, 2017)
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits which will need also state-restoring actions after a recovered SEU and which not. Furthermore, b) an alternative classification approach using fault injection is developed in order to compare both classification techniques. Moreover, c) we will propose a floorplanning approach for reducing the effective number of scrubbed frames and d), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits can be reduced by up to 48.5 % in comparison to standard approaches.
Keywords: Single Event Upsets; FPGA Scrubbing; Configuration Bit Partitioning; Floorplanning; Fault Injection

Optimizing the Efficiency of Parameterized Local Search within Global Search - Bhattacharyya, Shuvra S.; Teich, Jürgen; Zitzler, Eckart (Proc. of CEC'2000, the Int. Conf. on Evolutionary Computation, 2000)
UnivIS-Import:2015-04-16:Pub.2000.tech.IMMD.inform.optimi

Optimizing the Performance of Customizable Stencil Codes with Feature-Interaction Detection - Grebhahn, Alexander; Siegmund, Norbert; Apel, Sven; Kuckuk, Sebastian; Schmitt, Christian (2014)

OrganicBus: Organic Self-organising Bus-Based Communication Systems - Ziermann, Tobias; Wildermann, Stefan; Teich, Jürgen (Organic Computing - A Paradigm Shift for Complex Systems, 2011)
UnivIS-Import:2015-04-20:Pub.2011.tech.IMMD.inform.organi

Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors - Brand, Marcel; Hannig, Frank; Tanase, Alexandru-Petru; Teich, Jürgen (2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017)
We propose a new processor architecture called Orthogonal Instruction Processing (OIP). Contrary to Very Long Instruction Word (VLIW) decoding, we propose to orthogonally decode the sub-instruction words of each Functional Unit (FU) instead. Hereby, the OIP architecture is able to reduce the overall machine code size of VLIW programs significantly. We will show analytically as well as experimentally that, compared to a VLIW processor, the savings in instruction memory size easily compensate the overhead of one separate branch unit needed for each FU. For the analytical analysis, a mathematical model of hardware costs of an OIP processor is developed and compared to a conventional VLIW processor. In addition, we compare the code size of selected representative programs of the new processor architecture and show big savings of program memory. Here, the instruction memory requirements can be decreased by a factor of 0.465. This decrease in instruction memory, despite the discussed overhead, leads to savings in the overall hardware costs of one processor by a factor of 0.98

Output Serialization for FPGA-based and Coarse-grained Processor Arrays - Hannig, Frank; Teich, Jürgen (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005)
This paper deals with the mapping of loop programs onto processor arrays either implemented in an FPGA or available as (reconfigurable) coarse-grained processor architectures. Usually the proportion of processing elements to I/O-interfaces is much higher whereby problems of data transportation and synchronization are arising. In this realm, we propose a systematic approach in order to feed-out data. Here, (a) an efficient routing strategy is presented and (b) a novel retiming strategy is given in order to ensure collision free output serialization.
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.output
Keywords: Hardware mapping; Processor arrays; Serialization

Packet Routing in Dynamically Changing Networks on Chip - Ahmadinia, Ali; Bobda, Christophe; Majer, Mateusz; Teich, Jürgen (Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), 2005)

Parallel Bridging Models and Their Impact on Algorithm Design - Meyer auf der Heide, Friedhelm; Wanka, Rolf (Proceedings of the Int. Conf. on Computational Science (ICCS), 2001)

Paralleles Sortieren - Parallel geht schnell - Wanka, Rolf (Taschenbuch der Algorithmen, 2008)
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.infalg._paral

Paralleles Sortieren - Parallel geht schnell - Wanka, Rolf (Taschenbuch der Algorithmen, 2008)
UnivIS-Import:2018-09-06:Pub.2008.tech.IMMD.inform.parall

Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning - Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of the 22nd International Conference on Architecture of Computing Systems, 2009)
State-of-the-art behavioral synthesis tools barely have high-level transformations in order to achieve highly parallelized implementations. If any, they apply loop unrolling to obtain a higher throughput. In this paper, we employ the PARO behavioral synthesis tool which has the unique ability to perform both loop unrolling or loop partitioning. Loop unrolling replicates the loop kernel and exposes the parallelism for hardware implementation, whereas partitioning tiles the loop program onto a regular array consisting of tightly coupled processing elements. The usage of the same design tool for both the variants enables for the first time, a quantitative evaluation of the two approaches for reconfigurable architectures with help of computationally intensive algorithms selected from different benchmarks. Superlinear speedups in terms of throughput are accomplished for the processor array approach. In addition, area and power cost are reduced. © 2009 Springer Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.parall

Parallel MPSoC Simulation and Architecture Evaluation - Roloff, Sascha; Hannig, Frank; Teich, Jürgen (Modeling and Simulation of Invasive Applications and Architectures, 2019)
CRIS-Team WoS Importer:2019-11-08

Parallel Sorting - The Need for Speed - Wanka, Rolf (Algorithms Unplugged, 2011)
This chapter presents a parallel sorting algorithm. By parallel we mean that many comparisons can be done concurrently so that we need much less time than with an algorithm in which the comparisons have to be done one after the other. Parallel algorithms are particularly interesting for computers with many processors or a processor with many cores that can work concurrently, or for the design of chips or machines dedicated for sorting. © 2011 Springer-Verlag Berlin Heidelberg.
UnivIS-Import:2015-04-20:Pub.2011.tech.IMMD.infalg._paral

Parametric Yield Optimization Using Leakage-Yield-Driven Floorplanning - Xu, Yang; Wang, Bo; Teich, Jürgen (Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014)

Pareto-Front Exploration with Uncertain Objectives - Teich, Jürgen (Proc. First International Conference on Evolutionary Multi-Criterion Optimization, In Lecture Notes in Computer Science (LNCS), Vol. 1993, 2001)
UnivIS-Import:2015-04-16:Pub.2001.tech.IMMD.inform.pareto

PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications - Hannig, Frank; Ruckdeschel, Holger; Dutta, Hritam; Teich, Jürgen (Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing, 2008)
In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications. Key features of PARO are: (1) The design entry in form of a compact and intuitive functional programming language which allows highly parallel implementations. (2) Advanced partitioning techniques are applied in order to balance the trade-offs in cost and performance along with requisite throughputs. This is obtained by distributing computations onto an array of tightly coupled processor elements. (3) We demonstrate the performance of the FPGA synthesized hardware with several selected algorithms from different benchmarks. © 2008 Springer-Verlag Berlin Heidelber
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.parosy

Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs - Ahmadinia, Ali; Bobda, Christophe; Majer, Mateusz; Kurapati, Rajesham; Niyonkuru, Adronis (System Aspects in Organic and Pervasive Computing - Workshop Proceedings - Dynamically Reconfigurable Systems, Self-Organization and Emergence, 2005)
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.partia

Partial Reconfiguration on FPGAs in Practice - Tools and Applications - Koch, Dirk; Torresen, Jim; Beckhoff, Christian; Ziener, Daniel; Dennl, Christopher; Breuer, Volker; Teich, Jürgen; Feilen, Michael; Stechele, Walter (Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS), 2012)
Run-time reconfiguration of FPGAs has been around in academia for more than two decades but it is still applied very seldom in industrial applications. This has two main reasons: a lack of killer applications that substantially benefit from run-time reconfiguration and design tools that permit to quickly implement corresponding reconfigurable systems. This tutorial gives a survey on state-of-the-art trends on reconfigurable architectures and devices, application specific requirements, and design techniques and tools that are essential for implementing partial run-time reconfiguration on FPGAs. This is followed by a demonstration of the floorplanning and constraint generation tool GoAhead. Furthermore, the tutorial will reveal several applications that benefit from partial reconfiguration, including network data processing, digital signal processing, cognitive radio, and systems on a reconfigurable chip. For these applications, the individual challenges and implementation issues are presented together with the achieved results. This tutorial demonstrates that partial FPGA reconfiguration is beneficial and applicable in industrial systems. © 2012 Gesellschaft fuer Informatk.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.partia

Particles Prefer Walking Along the Axes: Experimental Insights into the Behavior of a Particle Swarm - Schmitt, Manuel; Wanka, Rolf (Companion of Proc. 15th Genetic and Evolutionary Computation Conference, 2013)
We study the frequently observed phenomenon of stagna- tion in the context of particle swarm optimization (PSO). We show that in certain situations the particle swarm is likely to move almost parallel to one of the axes, which may cause stagnation. We provide an experimentally supported explanation in terms of a potential of the swarm and are therefore able to adapt the PSO algorithm slightly such that this weakness can be avoided.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.infalg._parti_9
Keywords: Particle swarm optimization; Potential; Stagnation

Particle Swarm Optimization Almost Surely Finds Local Optima - Schmitt, Manuel; Wanka, Rolf (Proc. 15th Genetic and Evolutionary Computation Conference, 2013)
Particle swarm optimization (PSO) is a popular nature-inspired meta-heuristic for solving continuous optimization problems. Although this technique is widely used, up to now only some partial aspects of the method have been formally investigated. In particular, while it is well-studied how to let the swarm converge to a single point in the search space, no general theoretical statements about this point or on the best position any particle has found have been known. For a very general class of objective functions, we provide for the first time results about the quality of the solution found. We show that a slightly adapted PSO almost surely finds a local optimum. To do so, we investigate the newly defined . potential of the swarm. The potential drops when the swarm approaches the point of convergence, but increases if the swarm remains close to a point that is not a local optimum, meaning that the swarm charges potential and continues its movement.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.infalg._parti
Keywords: Fitness landscapes; Particle swarm optimization; Quality of solution

Particle Swarm Optimization Almost Surely Finds Local Optima - Schmitt, Manuel; Wanka, Rolf (Theoretical Computer Science, 2015)
UnivIS-Import:2015-03-11:Pub.2015.tech.IMMD.infalg._parti

Particle Swarm Optimization in High-Dimensional Bounded Search Spaces - Helwig, Sabine; Wanka, Rolf (Proceedings of the 2007 IEEE Swarm Intelligence Symposium, 2007)
When applying Particle Swarm Optimization (PSO) to real world optimization problems, often boundary constraints have to be taken into account. In this paper, we will show that the bound handling mechanism essentially influences the swarm behavior, especially in high-dimensional search spaces. In our theoretical analysis, we will prove that all particles are initialized very close to the boundary with overwhelming probability, and that the global guide is expected to leave the search space in every forth dimension. Afterwards, we investigate the initialization process when optimizing the Sphere function, a widely used benchmark, in more detail in order to provide a first step towards explaining previously observed phenomena. Moreover, we will present a broad experimental study of commonly applied bound handling mechanisms on a variety of benchmark functions which is useful for choosing an appropriate strategy in real world applications. Finally, we will derive some guidelines for the practical application of the PSO algorithm in high-dimensional bounded search spaces. © 2007 IEEE.
UnivIS-Import:2015-04-16:Pub.2007.tech.IMMD.infalg._parti

Particle Swarm Optimization with Velocity Adaptation - Helwig, Sabine; Neumann, Frank; Wanka, Rolf (Proc. 2009 International Conference on Adaptive and Intelligent Systems, 2009)
Particle swarm optimization (PSO) algorithms have gained increasing interest for dealing with continuous optimization problems in recent years. Often such problems involve boundary constraints. In this case, one has to cope with the situation that particles may leave the feasible search space. To deal with such situations different bound handling methods have been proposed in the literature and it has been observed that the success of PSO algorithms depends on a large degree on the used bound handling method. In this paper, we propose an alternative approach to cope with bounded search spaces. The idea is to introduce a velocity adaptation mechanism into PSO algorithms that is similar to step size adaptation used in evolution strategies. Using this approach we show that the bound handling method becomes less important for PSO algorithms and that using velocity adaptation leads to better results for a wide range of benchmark functions. © 2009 IEE
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.infalg._parti

Particle Swarms for Constrained Optimization - Helwig, Sabine (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2010)

Partitioning of processor arrays: A piecewise regular approach - Teich, Jürgen; Thiele, Lothar (Integration-The Vlsi Journal, 1993)
The paper describes the systematic design of processor arrays with a given dimension and given number of processing elements. This problem is called partitioning. A solution to the partitioning problem is described for mapping a class of algorithms with piecewise regular dependence graphs, i.e. piecewise regular algorithms, onto processor arrays. These arrays are also piecewise regular, i.e. they are composed of a number of regularly connected homogenous subarrays. Partitioning deals with the division of the dependence graph of a piecewise regular algorithm into tiles and the scheduling of corresponding operations on a processor array of fixed size and dimension. Different solutions to this problem are termed partitioning schemes. Partitioning schemes may be classified into projection, multiprojection, passive and active clustering. The hereafter presented unified approach to the solution of the partitioning problem is based on the following concepts: (1) Algorithms are represented by programs. These programs can be directly interpreted as a description of hardware. (2) The concept of stepwise refinement of programs is used to solve the partitioning problem by applying a sequence of provably correct program transformations. The transformations basically involve operations on index sets. Two program transformations are introduced: (a) The EXPAND program transformation partitions the iteration space of a given program into a direct sum of lattices. The dimension of the iteration space increases. In contrary to other approaches, also nonperfect tilings may be considered. (b) Operations are scheduled on a processor array of fixed size and dimension using the REDUCE transformation. The dimension of the iteration space and thereby the dimension of the processor array is reduced. The parameters of this program transformation enable the realization of the different partitioning schemes. (3) The whole solution is embedded in the concepts of a systematic design of processor arrays. © 1993.
UnivIS-Import:2015-03-05:Pub.1993.tech.IMMD.inform.partit
Keywords: algorithm transformation; clustering; fixed size arrays; mapping of algorithms; partitioning; VLSI processor arrays

Partitioning Processor Arrays under Resource Constraints - Teich, Jürgen; Thiele, Lothar; Zhang, L (Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 1997)
A single integer linear programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: 1) Not only constraints on the number of available processors and communication capabilities are taken into account, but also local memories and constraints on the size of available memories. 2) Different types of processors can be handled. 3) The size of the optimization model (number of integer variables) is independent of the size of the tiles to be executed. Hence, 4) the number of integer variables in the optimization model is greatly reduced such that problems of relevant size can be solved in practical execution time.
UnivIS-Import:2015-03-05:Pub.1997.tech.IMMD.inform.partit

Path Planning for Highly Automated Driving on Embedded GPUs - Fickenscher, Jörg; Schmidt, Sandra; Hannig, Frank; Bouzouraa, Mohammed Essayed; Teich, Jürgen (Multidisciplinary Digital Publishing Institute, 2018)

P-based System Design with the PARADISE Design Environment - Böke, Carsten; Ditze, C.; Hardt, Wolfram; Kleinjohann, Bernd; Rammig, Franz; Rettberg, Achim; Stroop, Joachim; Teich, Jürgen (EUROMICRO Journal, 2000)
UnivIS-Import:2015-03-09:Pub.2000.tech.IMMD.inform.pbased

Performance Analyses of Embedded Real-time Operating Systems using High-precision Counters - Köker, Kemal; Membarth, Richard; German, Reinhard (Proc. 3rd Int. Conf. on Autonomous Robots and Agents, 2006)
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.IMMD7.perfor_4

Performance analysis and optimization of mixed asynchronous synchronous systems - Martin, Michael; Sriram, Sundararajan; Teich, Jürgen; Thiele, Lothar (1994)

Performance Analysis of Mixed Asynchronous-Synchronous Systems - Martin, Michael; Sriram, Sundararajan; Teich, Jürgen; Thiele, Lothar (Proc. of the IEEE Int. Workshop on VLSI Signal Processing 94, 1994)
The paper is concerned with the timing analysis of a class digital systems we call mixed asynchronous-synchronous systems. In such a system, each computation module is either synchronous (i.e. clocked) or asynchronous (i.e. selftimed). The communication between modules is assumed to be selftimed for all modules. We introduce a graph model called MASS for describing the timing behaviour of such architectures. The graph contains two kinds of nodes, synchronous and asynchronous nodes. The operation model of a MASS is similar to that of a timed marked graph, however, additional schedule constraints are imposed on synchronous nodes: A synchronous node can only fire at ticks of its local module clock. We analyze the behaviour of MASS, in particular period, periodicity and maximal throughput rate.
UnivIS-Import:2015-04-16:Pub.1994.tech.IMMD.inform.perfor_5

Performance Analysis of Mixed Asynchronous-Synchronous Systems - Martin, Michael; Sriram, Sundararajan; Teich, Jürgen; Thiele, Lothar (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997)
UnivIS-Import:2015-03-05:Pub.1997.tech.IMMD.inform.perfor

Performance Comparison between Machine Learning based LTE Downlink Grant Predictors - Nisar, Abdullah; Ah Sue, Jonathan; Teich, Jürgen (Proceedings of the 21st International Conference on Artificial Intelligence, 2019)

Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 22nd International Conference on Architecture of Computing Systems, 2009)
In order to meet demanding challenges of increasing computational requirements and stringent power constraints, there is a gradual trend towards heterogeneous multi-processor system-on-chip (MPSoC) designs integrating application specific acceleration engines. One major problem faced by the design tools for mapping of algorithms onto MPSoC architectures is the dimensioning of system components through performance analysis. In this paper, we propose a fast and accurate methodology for rate matching of statically scheduled acceleration engines using modular performance analysis. Given a set of Pareto-optimal hardware accelerator designs and an input workload behavior, the proposed methodology determines cost efficient hardware accelerators that can handle the workload. A motion JPEG case study illustrates the benefit of coupling high level synthesis tools with performance analysis. © 2009 Springer Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.perfor

Performance Modeling and Parallelization of Environment Perception and Path Planning Algorithms for Heterogeneous Advanced Driver Assistance System Architectures - Fickenscher, Jörg (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2020)

Periodic Load Balancing on the N-Cycle: Analytical and Experimental Evaluation - Riess, Christian; Wanka, Rolf (Proceedings of the 13th International Euro-Par Conference, 2007)

Periodic Load Balancing on the N-Cycle: Analytical and Experimental Evaluation - Riess, Christian; Wanka, Rolf (Proc. 13th European Conference in Parallel Processing (Euro-Par), 2007)

Periodification scheme: Constructing sorting networks with constant period - Kutylowski, Miroslaw; Lorys, Krzysztof; Oesterdiekhoff, Brigitte; Wanka, Rolf (Journal of the Acm, 2000)
We consider comparator networks M that are used repeatedly: while the output produced by M is not sorted, it is fed again into M. Sorting algorithms working in this way are called periodic. The number of parallel steps performed during a single run of M is called 'Us period, the sorting time of M is the total number of parallel steps that are necessary to sort in the worst case. Periodic sprting networks have the advantage that they need little hardware (control logic, wiring, area) and that they are adaptive. We are interested in comparator networks of a constant period, due to their potential applications in hardware design. Previously, very little was known on such networks. The fastest solutions required time O(n), where the depth was roughly 1/∈. We introduce a general method called periodiflcation scheme that converts automatically an arbitrary sorting network that sorts n items in time T(n) and that has layout area A(n) into a sorting network that has period 5, sorts (n · T(n)) items in time O(T(n) · log n), and has layout area O(A(n) ·T(n)). In particular, applying this scheme to Batcher's algorithms, we get practical period 5 comparator networks that sort in time O(log n). For theoretical interest, one may use the AKS network resulting in a period 5 comparator network with runtime 0(log n). © 2000 ACM.
Keywords: Comparator network

Phase smoothing in a virtually synchronized pseudolite system using stochastic clock modelling - Patino-Studencki, Lucila; Thielecke, Jörn; Batzer, Ulrich (Ubiquitous Positioning Indoor Navigation and Location Based Service (UPINLBS), 2010)
A derivation of phase smoothing for a pseudolite system is given. The distinction to phase smoothing known from literature arises from the setup of the system. As of the employed free-running pseudolites, the main challenge is to properly estimate the pseudolite clocks. The better the pseudolite clocks are estimated, the more precise are the phase measurements and the more effective is phase smoothing. Two different methods for clock estimation are examined in terms of their applicability to phase smoothing. Simulated as well as real data are used in order to evaluate the precision gain by phase smoothing. Optimal solutions according to system restrictions are presented. © 2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IE.komele.phases
Keywords: Clock modeling; Phase smoothing; Pseudolite

Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks - Streichert, Thilo (Proceedings of 16th International Conference on Field Programmable Logic and Applications, 2006)
A novel framework shows the potential of FPGA-based systems for increasing fault-tolerance and flexibility by placing functionality onto free hardware (HW) or software (SW) resources at runtime. Based on Field-Programmable Gate Arrays (FPGAs) in combination with CPUs, tasks implemented in HW or SW will migrate between computational nodes in a network. Moreover, if not enough HW/SW resources are available, the migration of functionality from HW to SW or vice versa is provided. By integrating this resource management, also called online HW/SW partitioning, in a distributed operating system for networked systems, a substantial step towards self-adaptive systems has been done. Besides a short motivation for this project and the presentation of related work, this paper gives an idea about a novel approach and a powerful experimental setup. © 2006 IEEE.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.placin

Placing Multi-mode Streaming Applications on Dynamically Partially Reconfigurable Architectures - Wildermann, Stefan; Angermeier, Josef; Sibirko, Eugen; Teich, Jürgen (International Journal of Reconfigurable Computing, 2012)
UnivIS-Import:2015-03-09:Pub.2012.tech.IMMD.inform.placin

Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures - Angermeier, Josef; Wildermann, Stefan; Sibirko, Eugen; Teich, Jürgen (Proc. International Conference on ReConFigurable Computing and FPGAs, 2010)
By means of partial reconfiguration, parts of the hardware can be dynamically exchanged during operation what allows to adapt the system to changing requirements, and even enables the implementation of self-managing systems. This however requires sophisticated system architectures as well as proper algorithmic runtime support. In this paper, we present an algorithm for placing streaming applications at runtime. The approach considers the heterogeneity of common FPGAs, such as Block-RAMs, as well as the routing restrictions of on-chip streaming interconnections. To reduce reconfiguration time, we extend the data flow graphs by OR-nodes to describe differing parts of applications while keeping their similarities. This allows us to model systems which only reconfigure differing parts when switching between applications. The proposed algorithm is implemented as runtime support on an FPGA-based system-on-chip. © 2010 IEEE.
UnivIS-Import:2015-04-16:Pub.2010.tech.IMMD.inform.placin

Platform-Independent Methodology for Partial Reconfiguration - Koch, Dirk; Teich, Jürgen (Proceedings of the 2004 ACM conference Computing Frountiers, 2004)
In this paper we present a novel methodology for partial (re-)configuration that can be used for most bitstream configured hardware (HW). In particular low priced and not for partial reconfiguration designed devices can be used by our technique. Furthermore, the methodology is platform independent and requires neither specialized HW synthesis tools nor a documented bitstream. We manage configuration data by extracting and compressing (sub-) module data from complete bitstreams. Experiments demonstrated that this extracted bitstreams could be compressed down by orders of the primary bitstream size for some submpdules.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.platfo
Keywords: Bitstream Extraction; Configuration Compression; Partial Reconfiguration

Playing Tetris on Meshes and Multi-Dimensional SHEARSORT - Kutylowski, Miroslaw; Wanka, Rolf (In Proc. of 8th International Symposium on Algorithms and Computation (ISAAC), 1997)

Polyhedral Fragments: An Efficient Representation for Symbolically Generating Code for Processor Arrays - Witterauf, Michael; Hannig, Frank; Teich, Jürgen (Proceedings of the International Conference on Formal Methods and Models for System Design (MEMOCODE), 2019)

Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures. - Weichslgartner, Andreas; Heißwolf, Jan; Zaib, Aurang; Wild, Thomas; Herkersdorf, Andreas; Becker, Jürgen; Teich, Jürgen (Proceedings of the second International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), 2015)

Position Paper: Towards Redundant Communication through Hybrid Application Mapping - Weichslgartner, Andreas; Teich, Jürgen (Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), 2016)

Power Aware Design - Streichert, Thilo (Proceedings of the 1st Chinese-German Summer School, 2006)
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.powera

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores - Khdr, Heba; Pagani, Santiago; Rodrigues Sousa, Ericles; Lari, Vahid; Pathania, Anuj; Hannig, Frank; Shafique, Muhammad; Teich, Jürgen; Henkel, Jörg (IEEE Transactions on Computers, 2017)

Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures - Kissler, Dmitrij; Strawetz, Andreas; Hannig, Frank; Teich, Jürgen (Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2008)

Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures - Kissler, Dmitrij; Strawetz, Andreas; Hannig, Frank; Teich, Jürgen (Journal of Low Power Electronics, 2009)
Coarse-grained reconfigurable architectures deliver high performance and energy efficiency for computationally intensive applications like mobile multimedia and wireless communication. This work deals with the aspect of power-efficient dynamic reconfiguration control techniques in such architectures. Proper clock domain partitioning with custom clock gating combined with automatic clock gating resulted in a 38% total power reduction. This is more than a threefold as compared to the single clock gating techniques applied separately. One of the corresponding case study applications with 0.064 milliwatts per megahertz and 124 million operations per second per milliwatt power efficiency outperforms the major coarse-grained and general purpose embedded processor architectures by a factor of 1.7 to 28. Copyright © 2009 American Scientific Publishers All rights reserved Printed in the United States of America.
UnivIS-Import:2015-04-14:Pub.2009.tech.IMMD.inform.powere
Keywords: Coarse-Grained Reconfigurable Architectures (CGRA); Hierarchical Clock Gating; Low Power Adaptive Architectures

Power-Efficient Tightly-Coupled Processor Arrays for Digital Signal Processing - Kissler, Dmitrij (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2011)

Power Management Strategies for Serial RapidIO Endpoints in FPGAs - Schmid, Moritz; Hannig, Frank; Teich, Jürgen (Proc. of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), 2012)
We propose a novel data budget-based approach to dynamically control the average power consumption of Serial RapidIO endpoint controllers in FPGAs. The key concept of the approach is to not only perform clock-gating on the FPGA-internal components of the communication controller, but to disable the multi-gigabit transceivers during idle periods. The clock synchronization, inherent to serial interfaces, enables us to omit the often needed periodic link sensing, and only enable the controller according to a predefined schedule to transmit the allocated amount of data during a specific interval. Following this approach, we are able to reduce the dynamic power consumption by up to 77 % on average. © 2012 IEEE.
UnivIS-Import:2015-04-16:Pub.2012.tech.IMMD.inform.powerm

Power Signature Watermarking of IP Cores for FPGAs - Ziener, Daniel; Teich, Jürgen (Journal of Signal Processing Systems For Signal Image and Video Technology, 2008)
In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method where the signature is extracted in this way. We are able to sign IP cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected. In principle, the proposed power watermarking method works for all kinds of FPGAs. For Xilinx FPGAs, we demonstrate in detail that we can integrate the watermarking algorithms and the signature into the functionality of the watermarked core. So it is very hard to remove the watermark without destroying the core. Furthermore, we introduce a detection algorithm which can decode the signature from a voltage trace with high reliability. Additionally, two enhanced robustness algorithms are introduced which improve the detection probability in case of considerable noise sources. Using these techniques, it is possible to decode the signature even if other cores operate on the same device at the same time. © 2007 Springer Science+Business Media, LLC.
UnivIS-Import:2015-03-09:Pub.2008.tech.IMMD.inform.powers
Keywords: FPGA; IP cores; IPP; Power analysis; Signature; Watermarking

Precision- and Accuracy-Reconfigurable Processor Architectures—An Overview - Brand, Marcel; Hannig, Frank; Keszöcze, Oliver; Teich, Jürgen (IEEE Transactions on Circuits and Systems II: Express Briefs, 2022)
High performance and, at the same time, energy efficiency are important yet often conflicting requirements in many fields of emerging applications. Those applications range from multi-dimensional and multi-sensor digital signal processing to machine learning, such as neural network processing. Whereas conventional fixed-point and floating-point processor architectures cannot adapt to quite diverging demands related to required precision and accuracy of computations, even within a single application, e.g., in different layers of a neural network, domain-specific accelerators may be much too specific and thus rigid to cover a wide enough spectrum of applications. In this tutorial brief, we give an overview of existing processor solutions that are reconfigurable or tunable in precision or accuracy of computations. The spectrum of reviewed architectures ranges from processors with vectorizable processors over multi- and trans-precision solutions, including GPUs to any-time instruction-set processors. The latter works with a fixed precision, but the accuracy of the result of floating-point operations is encoded in the instruction word. It can thus vary from instruction to instruction. This allows realizing accuracy vs. execution time or energy tradeoffs. Subsequently, we investigate several application domains, including neural network processing, linear algebra, and approximate computing, where such emerging processor architectures can be beneficially use
Keywords: Computer architecture; Arithmetic; Circuits and systems; Neural networks; Adders; Machine learning algorithms; Linear algebra; Accuracy; Reconfigurable architectures; Convolutional neural networks

*-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing - Brand, Marcel; Witterauf, Michael; Sousa, Éricles; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Concurrency and Computation-Practice & Experience, 2019)
The fulfillment of non-functional requirements like timing or energy consumption is of utmost importance in many embedded systems and respective applications. Especially, with the introduc- tion of multi-core architectures, the ability to predict non-functional execution qualities becomes more and more difficult, as multiple concurrent application programs may interfere in execution when typcially sharing all the resources. In this paper, we advocate a novel parallel computing paradigm called invasive computing that allows to isolate application programs on multi-core targets. For a presented case study of a cyber-physical real-time control system, we show that invasive computing enables composability that in fact allows to characterize and analyze each ap- plication program statically and independent from each other. More specifically, it is shown that a distributed object detection algorithm for controlling an inverted pendulum and implemented on a heterogeneous invasive multi-processor SoC (MPSoC) is able to provide real-time guarantees as well as reliability requirements on demand. <br
Keywords: Invasive computing; processor arrays; symbolic parallelization; mapping; loop programs

Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems - Pourmohseni, Behnaz; Wildermann, Stefan; Glaß, Michael; Teich, Jürgen (Proceedings of the 25th International Conference on Real-Time Networks and Systems (RTNS), 2017)

Preemptive Hardware Task Management - Koch, Dirk (Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), 2004)
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.preemp

Probabilistic Curriculum-based Examination Timetabling - Bassimir, Bernd; Wanka, Rolf (Proc 12th International Conference on the Practice and Theory of Automated Timetabling (PATAT), 2018)
In the literature, the examination timetabling problem (ETTP) is mostly described as a post enrollment problem (PE-ETTP). As such, it is known at optimization time how many students will take an exam and consequently how big a room is needed and which exams should not be held at the same time because of overlapping student lists. To compute a timetable using this approach, students need to register for exams before the timetable is generated. A direct consequence is that at registration time students have no idea when their exams are being held. Furthermore as timetables are often released at the end of the semester, it is hard for lecturers to plan their other responsibilities accordingly. This leads to a negative reaction from both the student body and the staff holding the exams. In this paper, we describe a curriculum-based examination timetabling variant that is similar to the curriculum-based examination timetabling problem model (CB-ETTP) introduced by Cataldo et al. 2017. The aim of the model introduced in this work is to combine the positive aspects of PE-ETTP and CB-ETTP by the use of machine learning while reducing the problems of the CB-ETTP, namely the overestimation in the number of students taking an exam. We describe an approach to calculate the number of students taking an exam by using old planning data. Furthermore we give an example for integrating the knowledge from past experience as a new soft constraint. Through the addition of this new soft constraint, we get a measure for the robustness of the timetable in respect to the uncertainty in the data. Finally, we present experiments based on real world data from the University of Erlangen-Nuremberg (FAU) showing that the approach gives a good estimation for the number of students with only slight deviations from the actual numbers. <br
Keywords: Examination Timetabling; Curriculum-based Timetabling; Machine Learning

Probabilistic Dominance in Robust Multi-Objective Optimization - Khosravi, Faramarz; Borst, Michael; Teich, Jürgen (IEEE Congress on Evolutionary Computation (CEC), 2018)

Probabilistic Error Propagation through Approximated Boolean Networks - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Keszöcze, Oliver; Teich, Jürgen (Proceedings of the 57th Annual Design Automation Conference, 2020)
Keywords: Approximate Computing; Error propagation